drivers: pinctrl: add pinctrl driver for the Xilinx Zynq-7000
Add pinctrl driver for the Xilinx Zynq-7000 series SoCs. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
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4 changed files with 95 additions and 0 deletions
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@ -22,3 +22,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC13XX_CC26XX pinctrl_cc13xx_cc26xx.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_ESP32 pinctrl_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_XLNX_ZYNQ pinctrl_xlnx_zynq.c)
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@ -6,6 +6,10 @@ menuconfig PINCTRL
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if PINCTRL
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module = PINCTRL
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module-str = PINCTRL
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source "subsys/logging/Kconfig.template.log_config"
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config PINCTRL_STORE_REG
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bool
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help
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@ -47,5 +51,6 @@ source "drivers/pinctrl/Kconfig.lpc_iocon"
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source "drivers/pinctrl/Kconfig.cc13xx_cc26xx"
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source "drivers/pinctrl/Kconfig.esp32"
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source "drivers/pinctrl/Kconfig.rv32m1"
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source "drivers/pinctrl/Kconfig.xlnx"
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endif # PINCTRL
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12
drivers/pinctrl/Kconfig.xlnx
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12
drivers/pinctrl/Kconfig.xlnx
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@ -0,0 +1,12 @@
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# Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_XLNX_PINCTRL_ZYNQ := xlnx,pinctrl-zynq
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config PINCTRL_XLNX_ZYNQ
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bool "Xilinx Zynq 7000 processor system MIO pin controller driver"
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depends on SOC_FAMILY_XILINX_ZYNQ7000
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default $(dt_compat_enabled,$(DT_COMPAT_XLNX_PINCTRL_ZYNQ))
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select SYSCON
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help
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Enable the Xilinx Zynq 7000 processor system MIO pin controller driver.
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77
drivers/pinctrl/pinctrl_xlnx_zynq.c
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77
drivers/pinctrl/pinctrl_xlnx_zynq.c
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@ -0,0 +1,77 @@
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/*
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* Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/drivers/syscon.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(pinctrl_xlnx_zynq, CONFIG_PINCTRL_LOG_LEVEL);
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#define DT_DRV_COMPAT xlnx_pinctrl_zynq
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
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"Unsupported number of instances");
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/* Relative SLCR register offsets for use in asserts */
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#define MIO_PIN_53_OFFSET 0x00d4
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#define SD0_WP_CD_SEL_OFFSET 0x0130
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#define SD1_WP_CD_SEL_OFFSET 0x0134
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static const struct device *slcr = DEVICE_DT_GET(DT_INST_PHANDLE(0, syscon));
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static mm_reg_t base = DT_INST_REG_ADDR(0);
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K_SEM_DEFINE(pinctrl_lock, 1, 1);
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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uint16_t addr;
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uint32_t val;
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uint8_t i;
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int err = 0;
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ARG_UNUSED(reg);
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if (!device_is_ready(slcr)) {
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LOG_ERR("SLCR device not ready");
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return -ENODEV;
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}
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/* Guard the read-modify-write operations */
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k_sem_take(&pinctrl_lock, K_FOREVER);
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for (i = 0; i < pin_cnt; i++) {
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__ASSERT_NO_MSG(pins[i].offset <= MIO_PIN_53_OFFSET ||
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pins[i].offset == SD0_WP_CD_SEL_OFFSET ||
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pins[i].offset == SD1_WP_CD_SEL_OFFSET);
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addr = base + pins[i].offset;
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err = syscon_read_reg(slcr, addr, &val);
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if (err != 0) {
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LOG_ERR("failed to read SLCR addr 0x%04x (err %d)", addr, err);
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break;
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}
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LOG_DBG("0x%04x: mask 0x%08x, val 0x%08x", addr, pins[i].mask, pins[i].val);
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LOG_DBG("0x%04x r: 0x%08x", addr, val);
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val &= ~(pins[i].mask);
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val |= pins[i].val;
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LOG_DBG("0x%04x w: 0x%08x", addr, val);
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err = syscon_write_reg(slcr, addr, val);
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if (err != 0) {
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LOG_ERR("failed to write SLCR addr 0x%04x (err %d)", addr, err);
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break;
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}
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}
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k_sem_give(&pinctrl_lock);
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return err;
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}
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