drivers: pinctrl: introduce new Telink B91 Pinctrl driver
Pinctrl driver basic support for Telink B91 platform. Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
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4 changed files with 185 additions and 0 deletions
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@ -3,6 +3,7 @@
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zephyr_library()
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zephyr_library_sources(common.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_TELINK_B91 pinctrl_b91.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AF pinctrl_gd32_af.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NRF pinctrl_nrf.c)
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@ -29,6 +29,7 @@ config PINCTRL_DYNAMIC
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runtime. This can be useful, for example, to change the pins assigned to a
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peripheral at early boot stages depending on a certain input.
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source "drivers/pinctrl/Kconfig.b91"
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source "drivers/pinctrl/Kconfig.gd32"
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source "drivers/pinctrl/Kconfig.nrf"
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source "drivers/pinctrl/Kconfig.rcar"
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11
drivers/pinctrl/Kconfig.b91
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11
drivers/pinctrl/Kconfig.b91
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# Copyright (c) 2022 Telink Semiconductor
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_TELINK_B91_PINCTRL := telink,b91-pinctrl
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config PINCTRL_TELINK_B91
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bool "Telink B91 pin controller driver"
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depends on SOC_RISCV_TELINK_B91
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default $(dt_compat_enabled,$(DT_COMPAT_TELINK_B91_PINCTRL))
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help
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Enables Telink B91 pin controller driver
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172
drivers/pinctrl/pinctrl_b91.c
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172
drivers/pinctrl/pinctrl_b91.c
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/*
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* Copyright (c) 2022 Telink Semiconductor
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "analog.h"
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#include <drivers/pinctrl.h>
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#include <dt-bindings/pinctrl/b91-pinctrl.h>
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#define DT_DRV_COMPAT telink_b91_pinctrl
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/**
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* GPIO Function Enable Register
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* ADDR PINS
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* gpio_en: PORT_A[0-7]
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* gpio_en + 1*8: PORT_B[0-7]
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* gpio_en + 2*8: PORT_C[0-7]
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* gpio_en + 3*8: PORT_D[0-7]
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* gpio_en + 4*8: PORT_E[0-7]
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* gpio_en + 5*8: PORT_F[0-7]
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*/
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#define reg_gpio_en(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, gpio_en) + \
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((pin >> 8) * 8)))
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/**
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* Function Multiplexer Register
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* ADDR PINS
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* pin_mux: PORT_A[0-3]
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* pin_mux + 1: PORT_A[4-7]
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* pin_mux + 2: PORT_B[0-3]
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* pin_mux + 3: PORT_B[4-7]
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* pin_mux + 4: PORT_C[0-3]
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* pin_mux + 5: PORT_C[4-7]
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* pin_mux + 6: PORT_D[0-3]
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* pin_mux + 7: PORT_D[4-7]
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* pin_mux + 0x20: PORT_E[0-3]
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* pin_mux + 0x21: PORT_E[4-7]
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* pin_mux + 0x26: PORT_F[0-3]
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* pin_mux + 0x27: PORT_F[4-7]
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*/
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#define reg_pin_mux(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, pin_mux) + \
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(((pin >> 8) < 4) ? ((pin >> 8) * 2) : 0) + \
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(((pin >> 8) == 4) ? 0x20 : 0) + \
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(((pin >> 8) == 5) ? 0x26 : 0) + \
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((pin & 0x0f0) ? 1 : 0)))
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/**
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* Pull Up resistors enable
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* ADDR PINS
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* pull_up_en: PORT_A[0-3]
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* pull_up_en + 1: PORT_A[4-7]
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* pull_up_en + 2: PORT_B[0-3]
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* pull_up_en + 3: PORT_B[4-7]
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* pull_up_en + 4: PORT_C[0-3]
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* pull_up_en + 5: PORT_C[4-7]
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* pull_up_en + 6: PORT_D[0-3]
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* pull_up_en + 7: PORT_D[4-7]
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* pull_up_en + 8: PORT_E[0-3]
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* pull_up_en + 9: PORT_E[4-7]
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* pull_up_en + 10: PORT_F[0-3]
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* pull_up_en + 11: PORT_F[4-7]
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*/
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#define reg_pull_up_en(pin) ((uint8_t)(DT_INST_REG_ADDR_BY_NAME(0, pull_up_en) + \
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((pin >> 8) * 2) + \
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((pin & 0xf0) ? 1 : 0)))
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/* Pinctrl driver initialization */
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static int pinctrl_b91_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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/* set pad_mul_sel register value from dts */
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reg_gpio_pad_mul_sel |= DT_INST_PROP(0, pad_mul_sel);
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return 0;
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}
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SYS_INIT(pinctrl_b91_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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/* Act as GPIO function disable */
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static inline void pinctrl_b91_gpio_function_disable(uint32_t pin)
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{
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uint8_t bit = pin & 0xff;
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reg_gpio_en(pin) &= ~bit;
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}
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/* Get function value bits start position (offset) */
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static inline int pinctrl_b91_get_offset(uint32_t pin, uint8_t *offset)
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{
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switch (B91_PINMUX_GET_PIN_ID(pin)) {
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case B91_PIN_0:
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*offset = B91_PIN_0_FUNC_POS;
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break;
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case B91_PIN_1:
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*offset = B91_PIN_1_FUNC_POS;
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break;
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case B91_PIN_2:
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*offset = B91_PIN_2_FUNC_POS;
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break;
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case B91_PIN_3:
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*offset = B91_PIN_3_FUNC_POS;
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break;
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case B91_PIN_4:
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*offset = B91_PIN_4_FUNC_POS;
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break;
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case B91_PIN_5:
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*offset = B91_PIN_5_FUNC_POS;
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break;
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case B91_PIN_6:
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*offset = B91_PIN_6_FUNC_POS;
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break;
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case B91_PIN_7:
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*offset = B91_PIN_7_FUNC_POS;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/* Set pin's function */
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static int pinctrl_configure_pin(const pinctrl_soc_pin_t *pinctrl)
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{
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int status;
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uint8_t mask;
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uint8_t offset = 0;
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uint8_t pull = B91_PINMUX_GET_PULL(*pinctrl);
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uint8_t func = B91_PINMUX_GET_FUNC(*pinctrl);
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uint32_t pin = B91_PINMUX_GET_PIN(*pinctrl);
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uint8_t pull_up_en_addr = reg_pull_up_en(pin);
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/* calculate offset and mask for the func and pull values */
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status = pinctrl_b91_get_offset(pin, &offset);
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if (status != 0) {
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return status;
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}
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mask = (uint8_t) ~(BIT(offset) | BIT(offset + 1));
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/* disable GPIO function (can be enabled back by GPIO init using GPIO driver) */
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pinctrl_b91_gpio_function_disable(pin);
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/* set func value */
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func = func << offset;
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reg_pin_mux(pin) = (reg_pin_mux(pin) & mask) | func;
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/* set pull value */
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pull = pull << offset;
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analog_write_reg8(pull_up_en_addr, (analog_read_reg8(pull_up_en_addr) & mask) | pull);
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return status;
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}
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/* API implementation: configure_pins */
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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int status = 0;
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for (uint8_t i = 0; i < pin_cnt; i++) {
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status = pinctrl_configure_pin(pins++);
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if (status < 0) {
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break;
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}
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}
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return status;
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}
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