Commit graph

125 commits

Author SHA1 Message Date
Martí Bolívar
02b45f522f soc: riscv-ite: use new DT pinctrl accessors
Update to use the new APIs.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-08-25 18:09:00 -04:00
Henrik Brix Andersen
e6a3e238b9 soc: riscv: privilege: define soc_interrupt_init() as weak symbol
Define soc_interrupt_init as a weak symbol in the common RISC-V
privileged instruction set SoC support.

This allows overriding soc_interrupt_init for SoCs which are not fully
compliant with the RISC-V privileged specification.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-25 18:05:50 -04:00
Henrik Brix Andersen
d8e0027082 soc: riscv: privilege: define __soc_handle_irq as weak symbol
Define __soc_handle_irq as a weak symbol in the common RISC-V privileged
instruction set SoC support.

This allows overriding __soc_handle_irq for SoCs which are not fully
compliant with the RISC-V privileged specification.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-25 18:05:50 -04:00
Tim Lin
9938519c93 ITE: soc: it8xxx2: add register build asserts to validate the offsets
Add build asserts to validate the offsets are the expected value.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-08-25 18:04:37 -04:00
Tim Lin
033eb55aca ITE: riscv: it8xxx2: declare gctrl dts node and registers
Add general control(gctrl) node in dts, and declare gctrl registers

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-08-25 18:04:37 -04:00
Jim Shu
f3e926b6d0 soc: riscv: esp32c3: apply CONFIG_RISCV_GP option
esp32c3 has already supported RISC-V GP, just apply new kconfig option
to it. Forcely select CONFIG_RISCV_GP in esp32c3 at first because it
seems to be necessary in the esp32c3 SoC.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-20 18:53:23 -04:00
Jim Shu
9d34256ea4 soc: riscv: telink_b91: add GP relative addressing support
Add norelax option before initializing GP at common entry point.

Remove __global_pointer$ symbol in the SoC linker script because it's
in the arch one. Remove -mno-relax when GP support is enabled.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-20 18:53:23 -04:00
Jim Shu
c3ecf5331b soc: riscv: riscv-privilege: add GP relative addressing support
Initialize GP at common entry point of riscv-privilege SoCs so that
this commit add GP support of these SoCs at once.

As some privilege SoCs want to customize the entry point, they should
disable linker relaxation by `.norelax option` before entrying the
common entry point `__start`.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-20 18:53:23 -04:00
Shubham Kulkarni
60caed8d54 soc: esp32c3: Fix symbol placement in linker script
Creating static libraries for drivers moves some symbols out of IRAM.
This change fixes it.

Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
2021-08-20 18:25:22 -04:00
Dino Li
9c47f314a5 flash: it8xxx2: add a short delay before #CS be driven high
The delay will ensure last byte has been latched in before

This also change the method of reading status register from re-send
read status command on each read to read status register continuously.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-08-18 20:10:05 -04:00
Sylvio Alves
57e7fba288 soc: esp32: move board config to soc context
log and libc optimization default config are soc related
and should be moved out from board context.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-08-18 07:46:29 -04:00
Jim Shu
2cff73d3ba soc: riscv: esp32c3: remove RISCV_SOC_INIT_GP_VALUE option.
As this option is not needed and has been removed, also remove it
in the esp32c3 SoC.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-18 05:18:55 -04:00
Jim Shu
97fa203330 Revert "arch: riscv: added support for custom initialization of gp register"
This reverts commit 7b09d031fa. Because
context save of GP register is removed, we don't need to initialize GP
at thread init. GP will be a constant value so that it could only be
initialized at program start.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-18 05:18:55 -04:00
Sylvio Alves
1d219250bc soc: esp32c3: fix implicit declaration
replace HAL call to direct read reg function

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-08-09 13:15:47 -04:00
Sylvio Alves
6ea12f0fbb linker: esp32c3: add thread storage area
This adds missing _end area and remove
unused definitions present in the linker script

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-08-09 13:15:47 -04:00
Fabio Baltieri
ef93bbad57 linker: add an initialized DATA_SECTIONS linker location option
Current location options for linker source files includes init and
noinit ram data, but only a noinit ram section. This makes it impossible
for application code to define an initialized RAM output section,
such as with the Z_ITERABLE_SECTION_RAM() helpers.

Adding a DATA_SECTIONS linker source option for this use case.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2021-08-07 20:26:41 -04:00
Felipe Neves
4a0b5ce277 soc: riscv: esp32c3: fix ble controller init
By appending the right link layer controller configurarion

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-08-07 19:59:27 -04:00
Felipe Neves
2a5c37829d soc: riscv: esp32c3: make use of atomic in C
esp32c3 SoC is an rv32imc, so it does not support the atomic builtin.

Since it relies in atomic instructions.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-08-07 19:59:27 -04:00
Felipe Neves
2474c9b3f3 soc: riscv: esp32c3: added initial support for ble
subsystem by linking esp32 vhci adapter to the
espressif ble controller adapter

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-08-07 19:59:27 -04:00
Felipe Neves
d368087fc0 drivers: serial: added minimal uart driver for esp32c3
based on uart rom functions, also enable console driver
on top if this driver enabling logging

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-08-03 11:20:06 -05:00
Tim Lin
438bc9ec2a ITE: soc/riscv riscv-ite: create a shared macro to access the pinctrl_0
Create a shared macro to access the pinctrl_0 property. The pinctrl_0
property includes pinmux phandle, pin and alternate function.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-07-29 11:48:13 -04:00
Dino Li
eba3ed1668 soc: it8xxx2: correct extensions
it8xxx2 supports 'm', 'a', and 'c' extensions.
Enable them to save flash space and also improve
latency of fetching code from flash.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-26 19:30:33 -04:00
Ruibin Chang
21f0f958fe ITE drivers/ite_it8xxx2_timer: re-write ite timer driver
Re-write ite timer driver.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-07-24 21:26:49 -04:00
Ruibin Chang
97d2d7317c ITE soc/riscv/ite/it8xxx2/Kconfig: correct hw clock freq
Correct SYS_CLOCK_HW_CYCLES_PER_SEC and
SYS_CLOCK_TICKS_PER_SEC to match our real setting value
for precise timing.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-07-24 21:26:49 -04:00
Yuriy Vynnychek
3de6c05f63 soc: riscv: telink_b91: new Telink B91 (TLSR9) SoC system
A new RISC-V platform SoC for Telink B91 (TLSR9).

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2021-07-21 05:37:12 -04:00
Dino Li
b316d18cb0 drivers: gpio: it8xxx2: add support for GPIO_VOLTAGE_ flags
Support GPIO_VOLTAGE_1P8, GPIO_VOLTAGE_3P3 flags on IT8xxx2 chips.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-15 13:53:54 -05:00
Dino Li
7d5411d6e0 soc: it8xxx2: introduce SOC_IT8XXX2_PLL_FLASH_48M option
Enable SOC_IT8XXX2_PLL_FLASH_48M at default to reduce latency of
fetching code from flash.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-13 09:44:29 -04:00
Dino Li
a42be2f071 soc: riscv-ite: fix __soc_handle_irq
Save ra to caller saved register is wrong because it might get
overwritten after another function is called, so we fix this.

Remove clear mip register operation. (it8xxx2 supports machine-mode
only, and MEIP bit of mip is read-only).

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-09 12:45:01 -05:00
Felipe Neves
600f8c64e1 soc: riscv: esp32c3: use the new esp_rom prefix
For esp32c3 related ROM located functions instead
of esp32c3_rom.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves
2d1bdd86b6 soc: riscv: esp32c3: adds _PrepC to the startup code
The _PrepC() function is the standard risc-v way
of zephyr entry point, so let it call the z_cstart instead
of calling this function directly.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves
4c60d2ccc7 soc: riscv: esp32c3: add z_bss_zero in startup code
replaces the plain memcpy to zero the bss with
the standard zephyr function that does this task.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves
132ab922a8 drivers: timer: esp32c3: add esp32c3 systimer driver to CODEOWNERS
Also added maintainer to the entry

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves
7b09d031fa arch: riscv: added support for custom initialization of gp register
Plus added implementation for esp32c3 SoC.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves
5d736766ed soc: esp32c3: added initial soc support files for esp32c3
by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Kumar Gala
0b7824aba9 riscv: openisa_rv32m1: Fix booting of rv32m1_vega
rv32m1_vega don't boot due to device init ordering and changes with the
device model.  The soc code is looking for a device pointer for the
intmux.  Change to using DEVICE_DT_GET here as that will ensure we get
a valid pointer and by the time we need to utilize the pointer the
intmux driver will have been initialized and thus the device pointer
will be ready.

Also set BUILD_OUTPUT_HEX since we utilize openocd to flash and west
flash is looking for a hex file for openocd targets.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-07-01 17:03:17 -05:00
Ruibin Chang
d0ce9bb877 ITE drivers/pwm: add PWM for it8xxx2
Add pulse width modulator (PWM) for it8xxx2.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-07-01 13:21:06 -04:00
Dino Li
512ff06f84 ITE: soc: it8xxx2: correct the offset of eflash signature
This change corrects the offset to 80h and also add description
of flash signature.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-06-24 20:17:54 -04:00
Tim Lin
ef3c8507a6 ite: drivers/flash: add flash driver for it8xxx2
Add flash driver for it8xxx2. The driver can implement
flash read, write and erase that will be mapped to the
ram section for executing.

TEST="flash write 0x80000 0x10 0x20 0x30 0x40 ..."
     "flash read 0x80000 0x100"
     "flash erase 0x80000 0x1000"

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-06-22 15:15:20 -04:00
Rajnesh Kanwal
1c584127ba boards: risc-v: add BeagleV Starlight JH7100 board support
Adding support for beagleV Starlight board based on Starfive JH7100
SoC. It's a base support, no drivers other than uart has been tested.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
2021-06-22 08:45:00 -04:00
Ruibin Chang
d45668480a ITE driver/watchdog: add watchdog timer for it8xxx2
Add watchdog timer for it8xxx2.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-06-18 11:21:53 +02:00
Ruibin Chang
0c3bb75a05 ITE soc/riscv/riscv-ite/common/chipregs: add registers and IRQ num
Add registers and IRQ number for PD control.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-06-17 12:42:19 +02:00
Tim Lin
8ea58d4389 ite: drivers/adc: create pinmux phandle to the ADC driver node
Create the pinmux phandle to the ADC driver node in the
devicetree. When the pinmux_pin_set function in
adc_it8xxx2_channel_setup can refer to the setting of
this phandle. It is more flexible to use.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-06-11 15:47:25 +02:00
Ruibin Chang
3360637aff ITE Keyboard scan: add registers for ITE keyboard scan driver
Add registers for it8xxx2 keyboard scan driver.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2021-05-17 15:24:11 -04:00
Tim Lin
5f5fb7d792 ite: drivers/adc: it8xxx2: fix adc driver flow
This commit fixes the ADC driver flow. And add internal
reference voltage to ADC driver API. And correct the
data buffer that only need to store raw data.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-05-13 11:54:05 -04:00
Tim Lin
caa3328cc7 ite: drivers/pinmux: modify pinmux driver
Modify the pinmux control method and add support the fun3
& fun4 alternation function.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-05-05 08:45:16 -04:00
Ruibin Chang
37de0c4987 drivers/interrupt_controller/intc_ite_it8xxx2: global ite_intc_isr_clear()
We need to clear interrupt status, before we enable the interrupt.
So I let ite_intc_isr_clear() to be global function.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-05-03 19:58:40 -04:00
Dino Li
ee39291553 dts: it8xxx2: change flash size to 1M byte
Flash size of IT8xxx2 is 1M byte.

Change-Id: Ic1464b6e36f16291f14024a6fb49acbf3a243176
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-04-29 16:47:47 -05:00
Tim Lin
14e9e7a814 soc: riscv/riscv-ite: chip_chipregs: add chip register address
Add register address including external timer and watchdog(ETWD),
general control(GCTRL), serial peripheral interface(SPI).


Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-04-23 07:03:10 -04:00
Dino Li
0ab51ff657 drivers: gpio: ite_it8xxx2: enable more gpio groups
This change enables A, C, D, E, G, H, I, J, K, and L groups,
and fix gpio interrupt function.

This change also pull (and rename) dt-bindings/irq.h to
dt-bindings/interrupt-controller/ite-intc.h, because it is
chip-specific.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ifee039981c2cc4cf5980e663702a9921e629fc1e
2021-04-23 06:31:56 -04:00
Tim Lin
cd96046bee ite: drivers/adc: add adc drivers on it8xxx2_evb platform
This commit is about the it8xxx2 analog to digital converter
driver. Support 8 channels ch0~ch7 and 10-bit resolution.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-04-13 13:01:56 -04:00