Chip siwx91x has 672kB of SRAM shared between the Cortex-M4 (Zephyr) and
the NWP (Network Processor). 3 memory configurations are possible for
the Cortex-M4:
- 196kB
- 256kB
- 320kB
Less memory is allocated to Zephyr, more memory is allocated to NWP,
better are the WiFi and BLE performances.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Silabs siwx91x hardware use specific memory areas to store descriptors
for DMA requests. These areas are tightly coupled between the CPU and
the hardware. This helps in reducing the wait cycles.
Until now these addresses was also hard coded in the DT and in the
linker script. This patch leverage the zephyr,memory-region driver to
centralize the information in the DT.
Then, with this new implementation, the memory mapping is easier to
understand for the reader.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Remove sleeptimer as default soc timer and it should be only
used as soc timer if PM is enabled.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Add support for fixed GPIO routes that don't have a configurable
route register, but still require mode configuration and enabling.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
In the case where more than a full tick was unannounced when
sys_clock_set_timeout() was called, the timer driver would
subtract it from the next timeout. However, this is already
done by the caller through the elapsed() function in timeout.c,
leading to the timer interrupt firing too early.
With this fix, SYS_CLOCK_TICKS_PER_SEC can be increased to the
full speed of the low frequency timer. The underlying sleeptimer
API must be called with a timeout of at least 1, and will if needed
increase the value to the minimum value required by the hardware.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
silabs_s2 uses simplicity_sdk hal library, which already have by default
a zero latency IRQs mechanism with a hardcoded value. In order to be
aligned with simplicity_sdk, we need to activate Zero Latency IRQ in
Zephyr by default. The level (2) depends on the hardcoded
value in simplicity_sdk (CORE_ATOMIC_BASE_PRIORITY_LEVEL). Without this
fix, if you use an IRQ with a priority of 0 or 1, irq_lock() and
irq_unlock() have no effect for this IRQ.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
This driver allow to use Zephyr native IP stack or the IP stack provided
by HAL / WiseConnect.
The WiseConnect implementation may take advantage of the specific
features provided by the 917 (power consumption, speed,
validation...).
Some notable features are not available with this interface:
- It seems Zephyr does not provide API to offload multicast membership
management. User should be to directly call WiseConnect APIs
- Support for ICMP frames is difficult. Note that WiseConnect
automatically answer to ping request. It is just not possible to
send ping requests and receive ping responses.
- Zephyr and WiseConnect both support TLS offloading. However this
patch does not implement it.
- Reentrancy in the WiseConnect side is uncertain.
This implementation has been tested with samples/net/wifi/ (which relies
on subsys/net/lib/shell).
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Driver was tested with a custom application which enabled the BT_SHELL.
Basic functionalities were verified:
- Scanning
- Advertising
- Connecting
Configuration needed for the test:
- CONFIG_BT=y
- CONFIG_BT_PERIPHERAL=y
- CONFIG_BT_CENTRAL=y
- CONFIG_BT_SHELL=y
- CONFIG_SHELL=y
Co-authored-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Network Processor (NWP) is used to run WiFi, Bluetooth and Flash
drivers.
Co-authored-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Report DMA configuration in the board definitions.
Note the addresses of the DMA buffers are hardcoded in the HAL. So,
these areas have to be declared in the linker file.
Co-authored-by: Sai Santhosh Malae <santhosh.malae@silabs.com>
Signed-off-by: Sai Santhosh Malae <santhosh.malae@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
This device is included on Silabs SiWx91x series. The current driver is
able to manage "High Power" and "Ultra Low Power" pins.
Co-authored-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Introduce minimal support for Silicon Labs SiWx91x family. SiWx91x
provide many device and especially Bluetooth and Wifi connectivity. This
patch prepare Zephyr to receive further drivers.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
When the SiSDK HAL was introduced, a corresponding Kconfig option
was not. Update Series 2 SoCs to use the new option.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The ACMP module is enabled with this change in the gecko
and simplicity_sdk hal libraries for development on silabs
devices. This is a pre-requisite for implementing the
comparator driver that is compatible with silabs acmp
peripherals.
Signed-off-by: Christian Galante <christian.galante@silabs.com>
The GPIO peripheral on Silabs Series 2 devices is responsible for
allocating analog buses to analog peripherals. Enable support for
this in the pinctrl driver. Since these bus allocations are not
digital pins, introduce a new property silabs,analog-bus for this
purpose.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
sl_power_manager_sleep() doesn't expect the PRIMASK to be set when called.
Setting BASEPRI to 0 was moved to sl_power_manager_is_ok_to_sleep(),
this function is called after sl_power_manager_sleep() has set the PRIMASK.
Added sli_power_manager_on_wakeup() to force a clock restore before the
interrupt are handled. Added a call to retrieve the startup measurements,
reducing the early wakeup time.
Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
k_cpu_idle() and sl_power_manager_sleep() call WFI.
Remove the call to k_cpu_idle() and add back its tracing and
hook functions.
Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
The BT Link Layer needs to get runtime in a timely manner to keep
connections alive and handle other time-critical tasks. This is achieved by
adding a separate thread for it with a meta-IRQ priority, which means it
can preempt other threads. The driver also has an RX thread that passes HCI
messages from the controller to the host stack. This can be a lower
priority cooperative thread, as it doesn't have strict timing requirements.
Signed-off-by: Kalle Kietäväinen <kalle.kietavainen@silabs.com>
Silabs Series-2 (all the EFR32xg2x chips) use the new clock driver
introduced in commit bda8ae8c3f ("drivers: clock_control: silabs: Add
clock control driver"). This driver get all the configuration from the
Device Tree.
The CMU (Clock Management Unit) options (CMU_HFXO_FREQ, CMU_HFRCO_FREQ,
CMU_NEED_LFXO, CMU_HFCLK_HFXO, etc...) are now only used for Series-0
and Series-1. It does not make sense to bother the users with them.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The EFR32MG24B210F1536IM48 has 4 more GPIOs than the
EFR32MG24B310F1536IM48, and does not support the high accuracy
mode for the IADC.
Signed-off-by: Daniel Fuchs <software@sagacioussuricata.com>
Silicon Labs Series 2 and newer devices do alternate function
configuration fundamentally differently from Series 0 and 1. Pin routing
is done in a centralized fashion in the GPIO peripheral, as opposed to
having ROUTE registers in every peripheral. The concept of alternate
function location numbers also does not exist, functions are directly
assigned to GPIOs by their port and pin number.
This commit adds a new pinctrl driver for devices that use DBUS. It fully
makes use of pinctrl design principles as outlined in the Zephyr
documentation. The previous driver hard-codes pin properties such as filter
and pull-up/down in the driver itself, while the new driver leaves this up
to the user as configurable DeviceTree properties. The previous driver has
hard-coded support for UART, SPI and I2C, while the new driver has generic
support for all DBUS signals.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Only initialize the HFXO Manager HAL driver if the HFXO is enabled in
DeviceTree, the device uses SYSRTC for timekeeping, and Power Manager
is enabled. HFXO Manager integrates with the Sleeptimer HAL driver for
SYSRTC to autonomously wake the HFXO prior to Sleeptimer wakeup from
deep sleep. It is not needed on devices that don't have HFXO-SYSRTC
integration, and it is not needed if the application doesn't use deep
sleep.
Add missing call to init_hardware() prior to init().
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Power Manager no longer requires the Counter driver. This seems to have
been a hack to get the Sleeptimer HAL included in the build, as the
Sleeptimer is the real dependency of the Silabs Power Manager HAL.
Since Sleeptimer is now used for the OS timer, this hack is not needed.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add OS timer implementation making use of the Sleeptimer HAL.
Sleeptimer integrates tightly with the Silabs Power Manager HAL,
and must be used as the OS timer to achieve optimal power consumption
when using the radio.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
CMSIS SystemInit is not used in Zephyr. Implement the functionality
that isn't already done by Zephyr startup using soc_prep_hook().
The reason the lack of TrustZone init did not create immediately obvious
issues previously is that SMU faults can only happen if the SMU clock is
enabled.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Series 2 always uses the device init HAL, while Series 0/1 never do.
Create a separate soc.c for Series 2 to make both versions easier to read.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Swap from the deprecated device_init_* functions to clock manager
for clock tree configuration. Populate config headers using
device tree representation of clock tree and oscillator config.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Switch EFR32MG21 to use the device init HAL. This makes the init sequence
the same as the rest of Series 2.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
On Series 2, set the SYS_CLOCK_HW_CYCLES_PER_SEC Kconfig option from
DeviceTree, rather than separately configuring it in board-level
defconfig.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Defconfig was only available at the vendor and series level,
make it possible to have family specific definitions too.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The DC-DC converter was unconditionally initialized with default
settings on Series 2. Add device tree binding and nodes, and guard
call to init function. Map DT options to config header from HAL.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Added a new driver to support SPI communication via EUSART. Since the
Silabs EFR32MG24 family SoCs have only one USART, EUSART support is
necessary for implementing SPI functionality.
Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
It is a good practice to add a comment after #endif when the condition
is not obvious. However, when the condition is well known, "Don't Repeat
Yourself" rule applies and no comment should be added.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Most of the Kconfig files in soc/silabs start with a comment describing
the chip. This comment is redundant with the help message in associated
to the chip. Let's don't repeat ourselves.
This patch also ensure the Kconfig help message the full name the chip.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Update HAL for Series 2 devices to Simplicity SDK 2024.6.
This HAL deprecates sl_device_init_emu(). Equivalent functions
are now performed by sl_power_manager_init().
For now, soc.c remains compatible with both the Gecko SDK based
HAL for Series 0 and 1, and the Simplicity SDK based HAL for
Series 2. In a future commit, soc.c will be split between the
two platforms.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This serves two main purposes:
- change the CPU clock via devicetree nodes
- provide the APB frequency to device drivers via the clock driver
interface
Theoretically this could also support choosing between the available
clock sources, but right now we only support LPOSC0 going into PLL0,
going into AHB.
Turning the PLL back off is also not supported since the only current
use case is to set the PLL frequency, turn it on, and switch the AHB
over to it.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
This is the bare minimum and includes the SoC, pinctrl, flash and
devicetree.
I had to include the flash driver that early because I couldn't make
Zephyr compile without flash driver nodes in the device tree.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
