soc: silabs: Initialize clock manager HAL from DT
Swap from the deprecated device_init_* functions to clock manager for clock tree configuration. Populate config headers using device tree representation of clock tree and oscillator config. Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit is contained in:
parent
634976f535
commit
955aca6c09
5 changed files with 511 additions and 27 deletions
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@ -92,8 +92,6 @@ zephyr_include_directories(
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${COMMON_DIR}/inc
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${EMLIB_DIR}/inc
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${PERIPHERAL_DIR}/inc
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${SERVICE_DIR}/device_init/config/s2
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${SERVICE_DIR}/device_init/config/s2/sdid${CONFIG_SOC_GECKO_SDID}
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${SERVICE_DIR}/clock_manager/inc
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${SERVICE_DIR}/device_init/inc
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${SERVICE_DIR}/device_manager/inc
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@ -130,6 +128,8 @@ zephyr_library_sources(
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${EMLIB_DIR}/src/em_system.c
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${SERVICE_DIR}/clock_manager/src/sl_clock_manager.c
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${SERVICE_DIR}/clock_manager/src/sl_clock_manager_hal_s2.c
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${SERVICE_DIR}/clock_manager/src/sl_clock_manager_init.c
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${SERVICE_DIR}/clock_manager/src/sl_clock_manager_init_hal_s2.c
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${SERVICE_DIR}/device_manager/devices/sl_device_peripheral_hal_efr32xg${SILABS_DEVICE_FAMILY_NUMBER}.c
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${SERVICE_DIR}/device_manager/gpios/sl_device_gpio_common.c
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${SERVICE_DIR}/device_manager/src/sl_device_clock.c
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@ -153,10 +153,6 @@ zephyr_library_sources_ifdef(CONFIG_DT_HAS_SILABS_SERIES2_DCDC_ENABLED
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)
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endif()
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zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_DEV_INIT
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${SERVICE_DIR}/device_init/src/sl_device_init_dpll_s2.c
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${SERVICE_DIR}/device_init/src/sl_device_init_hfrco.c
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${SERVICE_DIR}/device_init/src/sl_device_init_hfxo_s2.c
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${SERVICE_DIR}/device_init/src/sl_device_init_nvic.c
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${SERVICE_DIR}/power_manager/src/sl_power_manager.c
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${SERVICE_DIR}/power_manager/src/sl_power_manager_hal_s2.c
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${SERVICE_DIR}/hfxo_manager/src/sl_hfxo_manager.c
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@ -0,0 +1,78 @@
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/*
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* Copyright (c) 2024 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H
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#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H
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#include <zephyr/devicetree.h>
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#include <em_device.h>
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/* HFXO */
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#define SL_CLOCK_MANAGER_HFXO_EN DT_NODE_HAS_STATUS(DT_NODELABEL(hfxo), okay)
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#define SL_CLOCK_MANAGER_HFXO_MODE DT_ENUM_IDX(DT_NODELABEL(hfxo), mode)
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#define SL_CLOCK_MANAGER_HFXO_FREQ DT_PROP(DT_NODELABEL(hfxo), clock_frequency)
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#define SL_CLOCK_MANAGER_HFXO_CTUNE DT_PROP(DT_NODELABEL(hfxo), ctune)
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#define SL_CLOCK_MANAGER_HFXO_PRECISION DT_PROP(DT_NODELABEL(hfxo), precision)
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#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0
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/* LFXO */
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#define SL_CLOCK_MANAGER_LFXO_EN DT_NODE_HAS_STATUS(DT_NODELABEL(lfxo), okay)
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#define SL_CLOCK_MANAGER_LFXO_MODE (DT_ENUM_IDX(DT_NODELABEL(lfxo), mode) << _LFXO_CFG_MODE_SHIFT)
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#define SL_CLOCK_MANAGER_LFXO_CTUNE DT_PROP(DT_NODELABEL(lfxo), ctune)
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#define SL_CLOCK_MANAGER_LFXO_PRECISION DT_PROP(DT_NODELABEL(lfxo), precision)
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#define SL_CLOCK_MANAGER_LFXO_TIMEOUT \
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(DT_ENUM_IDX(DT_NODELABEL(lfxo), timeout) << _LFXO_CFG_TIMEOUT_SHIFT)
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/* HFRCODPLL */
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#define SL_CLOCK_MANAGER_HFRCO_BAND \
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(DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 1500000 ? 1000000U \
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: DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 3000000 ? 2000000U \
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: DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 5500000 ? 4000000U \
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: DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 10000000 ? 7000000U \
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: DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 14500000 ? 13000000U \
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: DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 17500000 ? 16000000U \
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: DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 23000000 ? 19000000U \
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: DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 29000000 ? 26000000U \
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: DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 35000000 ? 32000000U \
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: DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 44000000 ? 38000000U \
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: DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 52000000 ? 48000000U \
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: DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 60000000 ? 56000000U \
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: DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 72000000 ? 64000000U \
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: DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 90000000 ? 80000000U \
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: 100000000U)
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#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN DT_NUM_CLOCKS(DT_NODELABEL(hfrcodpll))
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#define SL_CLOCK_MANAGER_DPLL_FREQ DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency)
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#define SL_CLOCK_MANAGER_DPLL_N DT_PROP(DT_NODELABEL(hfrcodpll), dpll_n)
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#define SL_CLOCK_MANAGER_DPLL_M DT_PROP(DT_NODELABEL(hfrcodpll), dpll_m)
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#define SL_CLOCK_MANAGER_DPLL_REFCLK \
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(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(hfrcodpll)), DT_NODELABEL(hfxo)) \
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? CMU_DPLLREFCLKCTRL_CLKSEL_HFXO \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(hfrcodpll)), DT_NODELABEL(lfxo)) \
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? CMU_DPLLREFCLKCTRL_CLKSEL_LFXO \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(hfrcodpll)), DT_NODELABEL(clkin0)) \
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? CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 \
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: CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED)
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#define SL_CLOCK_MANAGER_DPLL_EDGE DT_ENUM_IDX(DT_NODELABEL(hfrcodpll), dpll_edge)
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#define SL_CLOCK_MANAGER_DPLL_LOCKMODE DT_ENUM_IDX(DT_NODELABEL(hfrcodpll), dpll_lock)
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#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER DT_PROP(DT_NODELABEL(hfrcodpll), dpll_autorecover)
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#define SL_CLOCK_MANAGER_DPLL_DITHER DT_PROP(DT_NODELABEL(hfrcodpll), dpll_dither)
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/* HFRCOEM23 */
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#if DT_NODE_EXISTS(DT_NODELABEL(hfrcoem23))
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#define SL_CLOCK_MANAGER_HFRCOEM23_BAND DT_PROP(DT_NODELABEL(hfrcoem23), clock_frequency)
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#endif
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/* LFRCO */
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#if DT_NODE_EXISTS(DT_NODELABEL(lfrco))
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#define SL_CLOCK_MANAGER_LFRCO_PRECISION DT_PROP(DT_NODELABEL(lfrco), precision_mode)
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#endif
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/* CLKIN0 */
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#define SL_CLOCK_MANAGER_CLKIN0_FREQ DT_PROP(DT_NODELABEL(clkin0), clock_frequency)
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#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */
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@ -0,0 +1,429 @@
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/*
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* Copyright (c) 2024 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H
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#define SL_CLOCK_MANAGER_TREE_CONFIG_H
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#include <zephyr/devicetree.h>
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#include <em_device.h>
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/* Internal macros that must be defined to make parameter validation in the HAL pass,
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* but are unused since Zephyr derives all clock tree configuration from DeviceTree
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*/
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#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE 0xFF
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#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF
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#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE 0xFC
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#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC
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#define SL_CLOCK_MANAGER_INVALID 0xFF
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/* SYSCLK */
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#define SL_CLOCK_MANAGER_SYSCLK_SOURCE \
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(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(fsrco)) \
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? CMU_SYSCLKCTRL_CLKSEL_FSRCO \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(hfrcodpll)) \
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? CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(hfxo)) \
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? CMU_SYSCLKCTRL_CLKSEL_HFXO \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(clkin0)) \
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? CMU_SYSCLKCTRL_CLKSEL_CLKIN0 \
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: SL_CLOCK_MANAGER_INVALID)
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#if SL_CLOCK_MANAGER_SYSCLK_SOURCE == SL_CLOCK_MANAGER_INVALID
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#error "Invalid clock source selection for SYSCLK"
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#endif
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#define SL_CLOCK_MANAGER_HCLK_DIVIDER \
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CONCAT(CMU_SYSCLKCTRL_HCLKPRESC_DIV, DT_PROP(DT_NODELABEL(hclk), clock_div))
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#define SL_CLOCK_MANAGER_PCLK_DIVIDER \
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CONCAT(CMU_SYSCLKCTRL_PCLKPRESC_DIV, DT_PROP(DT_NODELABEL(pclk), clock_div))
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/* TRACECLK */
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#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK)
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#if DT_NUM_CLOCKS(DT_NODELABEL(traceclk)) == 0
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#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_DISABLE
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#else
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#if defined(CMU_TRACECLKCTRL_CLKSEL_SYSCLK)
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/* TRACECLK can be clocked from SYSCLK */
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#define SL_CLOCK_MANAGER_TRACECLK_SOURCE \
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(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(sysclk)) \
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? CMU_TRACECLKCTRL_CLKSEL_SYSCLK \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(hfrcodpllrt)) \
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? CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT \
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: COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(hfrcoem23)), ( \
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DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), \
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DT_NODELABEL(hfrcoem23)) \
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? CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 \
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: SL_CLOCK_MANAGER_INVALID), (SL_CLOCK_MANAGER_INVALID)))
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#else
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/* TRACECLK can be clocked from HCLK */
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#define SL_CLOCK_MANAGER_TRACECLK_SOURCE \
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(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(hclk)) \
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? CMU_TRACECLKCTRL_CLKSEL_HCLK \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(hfrcoem23)) \
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? CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 \
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: SL_CLOCK_MANAGER_INVALID)
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#endif /* defined(CMU_TRACECLKCTRL_CLKSEL_SYSCLK) */
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#if SL_CLOCK_MANAGER_TRACECLK_SOURCE == SL_CLOCK_MANAGER_INVALID
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#error "Invalid clock source selection for TRACECLK"
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#endif
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#endif /* DT_NUM_CLOCKS(traceclk) */
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#endif /* defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) */
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#if DT_NODE_HAS_PROP(DT_NODELABEL(traceclk), clock_div)
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#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER \
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CONCAT(CMU_TRACECLKCTRL_PRESC_DIV, DT_PROP(DT_NODELABEL(traceclk), clock_div))
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#endif
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/* EM01GRPACLK */
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#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE \
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(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpaclk)), DT_NODELABEL(hfrcodpll)) \
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? CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpaclk)), DT_NODELABEL(hfxo)) \
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? CMU_EM01GRPACLKCTRL_CLKSEL_HFXO \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpaclk)), DT_NODELABEL(fsrco)) \
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? CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO \
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: COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(hfrcoem23)), ( \
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DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpaclk)), \
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DT_NODELABEL(hfrcoem23)) \
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? CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 \
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: COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(hfrcodpllrt)), ( \
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DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpaclk)), \
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DT_NODELABEL(hfrcodpllrt)) \
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? CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpaclk)), \
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DT_NODELABEL(hfxort)) \
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? CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT \
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: SL_CLOCK_MANAGER_INVALID), (SL_CLOCK_MANAGER_INVALID))), \
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(SL_CLOCK_MANAGER_INVALID)))
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#if SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE == SL_CLOCK_MANAGER_INVALID
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#error "Invalid clock source selection for EM01GRPACLK"
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#endif
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/* EM01GRPBCLK */
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#if DT_NODE_EXISTS(DT_NODELABEL(em01grpbclk))
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#define SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE \
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(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpbclk)), DT_NODELABEL(hfrcodpll)) \
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? CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpbclk)), DT_NODELABEL(hfxo)) \
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? CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpbclk)), DT_NODELABEL(fsrco)) \
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? CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpbclk)), DT_NODELABEL(clkin0)) \
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? CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 \
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: COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(hfrcodpllrt)), ( \
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DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpbclk)), \
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DT_NODELABEL(hfrcodpllrt)) \
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? CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpbclk)), \
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DT_NODELABEL(hfxort)) \
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? CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT \
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: SL_CLOCK_MANAGER_INVALID), (SL_CLOCK_MANAGER_INVALID)))
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#if SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE == SL_CLOCK_MANAGER_INVALID
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#error "Invalid clock source selection for EM01GRPBCLK"
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#endif
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#endif /* DT_NODE_EXISTS(em01grpbclk)*/
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/* EM01GRPCCLK */
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#if DT_NODE_EXISTS(DT_NODELABEL(em01grpcclk))
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#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE \
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(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpcclk)), DT_NODELABEL(hfrcodpll)) \
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? CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpcclk)), DT_NODELABEL(hfxo)) \
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? CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpcclk)), DT_NODELABEL(fsrco)) \
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? CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO \
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: COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(hfrcoem23)), ( \
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DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpcclk)), \
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DT_NODELABEL(hfrcodpllrt)) \
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? CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpcclk)), \
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DT_NODELABEL(hfxort)) \
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? CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpcclk)), \
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DT_NODELABEL(hfrcoem23)) \
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? CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 \
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: SL_CLOCK_MANAGER_INVALID), (SL_CLOCK_MANAGER_INVALID)))
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#if SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE == SL_CLOCK_MANAGER_INVALID
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#error "Invalid clock source selection for EM01GRPCCLK"
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#endif
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#endif /* DT_NODE_EXISTS(em01grpcclk)*/
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/* IADCCLK */
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#if DT_NODE_EXISTS(DT_NODELABEL(iadcclk))
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#define SL_CLOCK_MANAGER_IADCCLK_SOURCE \
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(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(iadcclk)), DT_NODELABEL(em01grpaclk)) \
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? CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(iadcclk)), DT_NODELABEL(fsrco)) \
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? CMU_IADCCLKCTRL_CLKSEL_FSRCO \
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: COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(hfrcoem23)), ( \
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DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(iadcclk)), \
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DT_NODELABEL(hfrcoem23)) \
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? CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 \
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: SL_CLOCK_MANAGER_INVALID), (SL_CLOCK_MANAGER_INVALID)))
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#if SL_CLOCK_MANAGER_IADCCLK_SOURCE == SL_CLOCK_MANAGER_INVALID
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#error "Invalid clock source selection for IADCCLK"
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#endif
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#endif /* DT_NODE_EXISTS(iadcclk) */
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/* LESENSEHFCLK */
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#if DT_NODE_EXISTS(DT_NODELABEL(lesensehfclk))
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#define SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE \
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(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(lesensehfclk)), DT_NODELABEL(hfrcoem23)) \
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? CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 \
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: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(lesensehfclk)), DT_NODELABEL(fsrco)) \
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? CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO \
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: SL_CLOCK_MANAGER_INVALID)
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|
||||
#if SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for LESENSEHFCLK"
|
||||
#endif
|
||||
#endif /* DT_NODE_EXISTS(lesensehfclk) */
|
||||
|
||||
/* EM23GRPACLK */
|
||||
#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em23grpaclk)), DT_NODELABEL(lfrco)) \
|
||||
? CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em23grpaclk)), DT_NODELABEL(lfxo)) \
|
||||
? CMU_EM23GRPACLKCTRL_CLKSEL_LFXO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em23grpaclk)), DT_NODELABEL(ulfrco)) \
|
||||
? CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
|
||||
#if SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for EM23GRPACLK"
|
||||
#endif
|
||||
|
||||
/* EM4GRPACLK */
|
||||
#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em4grpaclk)), DT_NODELABEL(lfrco)) \
|
||||
? CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em4grpaclk)), DT_NODELABEL(lfxo)) \
|
||||
? CMU_EM4GRPACLKCTRL_CLKSEL_LFXO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em4grpaclk)), DT_NODELABEL(ulfrco)) \
|
||||
? CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
|
||||
#if SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for EM4GRPACLK"
|
||||
#endif
|
||||
|
||||
/* RTCCCLK */
|
||||
#if DT_NODE_EXISTS(DT_NODELABEL(rtccclk))
|
||||
#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(rtccclk)), DT_NODELABEL(lfrco)) \
|
||||
? CMU_RTCCCLKCTRL_CLKSEL_LFRCO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(rtccclk)), DT_NODELABEL(lfxo)) \
|
||||
? CMU_RTCCCLKCTRL_CLKSEL_LFXO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(rtccclk)), DT_NODELABEL(ulfrco)) \
|
||||
? CMU_RTCCCLKCTRL_CLKSEL_ULFRCO \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
|
||||
#if SL_CLOCK_MANAGER_RTCCCLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for RTCCCLK"
|
||||
#endif
|
||||
#endif /* DT_NODE_EXISTS(rtccclk) */
|
||||
|
||||
/* SYSRTCCLK */
|
||||
#if DT_NODE_EXISTS(DT_NODELABEL(sysrtcclk))
|
||||
#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysrtcclk)), DT_NODELABEL(lfrco)) \
|
||||
? CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysrtcclk)), DT_NODELABEL(lfxo)) \
|
||||
? CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysrtcclk)), DT_NODELABEL(ulfrco)) \
|
||||
? CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
|
||||
#if SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for SYSRTCCLK"
|
||||
#endif
|
||||
#endif /* DT_NODE_EXISTS(sysrtcclk) */
|
||||
|
||||
/* WDOG0CLK */
|
||||
#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(wdog0clk)), DT_NODELABEL(lfrco)) \
|
||||
? CMU_WDOG0CLKCTRL_CLKSEL_LFRCO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(wdog0clk)), DT_NODELABEL(lfxo)) \
|
||||
? CMU_WDOG0CLKCTRL_CLKSEL_LFXO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(wdog0clk)), DT_NODELABEL(ulfrco)) \
|
||||
? CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(wdog0clk)), DT_NODELABEL(hclkdiv1024)) \
|
||||
? CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
|
||||
#if SL_CLOCK_MANAGER_WDOG0CLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for WDOG0CLK"
|
||||
#endif
|
||||
|
||||
/* WDOG1CLK */
|
||||
#if DT_NODE_EXISTS(DT_NODELABEL(wdog1clk))
|
||||
#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(wdog1clk)), DT_NODELABEL(lfrco)) \
|
||||
? CMU_WDOG1CLKCTRL_CLKSEL_LFRCO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(wdog1clk)), DT_NODELABEL(lfxo)) \
|
||||
? CMU_WDOG1CLKCTRL_CLKSEL_LFXO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(wdog1clk)), DT_NODELABEL(ulfrco)) \
|
||||
? CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(wdog1clk)), DT_NODELABEL(hclkdiv1024)) \
|
||||
? CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
|
||||
#if SL_CLOCK_MANAGER_WDOG1CLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for WDOG1CLK"
|
||||
#endif
|
||||
#endif /* DT_NODE_EXISTS(wdog1clk) */
|
||||
|
||||
/* LCDCLK */
|
||||
#if DT_NODE_EXISTS(DT_NODELABEL(lcdclk))
|
||||
#define SL_CLOCK_MANAGER_LCDCLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(lcdclk)), DT_NODELABEL(lfrco)) \
|
||||
? CMU_LCDCLKCTRL_CLKSEL_LFRCO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(lcdclk)), DT_NODELABEL(lfxo)) \
|
||||
? CMU_LCDCLKCTRL_CLKSEL_LFXO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(lcdclk)), DT_NODELABEL(ulfrco)) \
|
||||
? CMU_LCDCLKCTRL_CLKSEL_ULFRCO \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
|
||||
#if SL_CLOCK_MANAGER_LCDCLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for LCDCLK"
|
||||
#endif
|
||||
#endif /* DT_NODE_EXISTS(lcdclk) */
|
||||
|
||||
/* PCNT0CLK */
|
||||
/* FIXME: allow clock selection from S0 pin */
|
||||
#if DT_NODE_EXISTS(DT_NODELABEL(pcnt0clk))
|
||||
#if DT_NUM_CLOCKS(DT_NODELABEL(pcnt0clk)) == 0
|
||||
#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_DISABLED
|
||||
#else
|
||||
#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(pcnt0clk)), DT_NODELABEL(em23grpaclk)) \
|
||||
? CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
|
||||
#if SL_CLOCK_MANAGER_PCNT0CLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for PCNT0CLK"
|
||||
#endif
|
||||
#endif /* DT_NUM_CLOCKS(pcnt0clk) */
|
||||
#endif /* DT_NODE_EXISTS(pcnt0clk) */
|
||||
|
||||
/* EUART0CLK */
|
||||
#if DT_NODE_EXISTS(DT_NODELABEL(euart0clk))
|
||||
#if DT_NUM_CLOCKS(DT_NODELABEL(euart0clk)) == 0
|
||||
#define SL_CLOCK_MANAGER_EUART0CLK_SOURCE CMU_EUART0CLKCTRL_CLKSEL_DISABLED
|
||||
#else
|
||||
#define SL_CLOCK_MANAGER_EUART0CLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(euart0clk)), DT_NODELABEL(em01grpaclk)) \
|
||||
? CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(euart0clk)), DT_NODELABEL(em23grpaclk)) \
|
||||
? CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
|
||||
#if SL_CLOCK_MANAGER_EUART0CLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for EUART0CLK"
|
||||
#endif
|
||||
#endif /* DT_NUM_CLOCKS(euart0clk) */
|
||||
#endif /* DT_NODE_EXISTS(euart0clk) */
|
||||
|
||||
/* EUSART0CLK */
|
||||
#if DT_NODE_EXISTS(DT_NODELABEL(eusart0clk))
|
||||
#if DT_NUM_CLOCKS(DT_NODELABEL(eusart0clk)) == 0
|
||||
#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_DISABLED
|
||||
#else
|
||||
#if DT_NODE_EXISTS(DT_NODELABEL(em01grpbclk))
|
||||
/* If EM01GRPB clock exists, EUSART0 is in EM01GRPA or EM23GRPA */
|
||||
#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(eusart0clk)), DT_NODELABEL(em01grpaclk)) \
|
||||
? CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(eusart0clk)), DT_NODELABEL(em23grpaclk)) \
|
||||
? CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(eusart0clk)), DT_NODELABEL(fsrco)) \
|
||||
? CMU_EUSART0CLKCTRL_CLKSEL_FSRCO \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
#else
|
||||
/* Otherwise, EUSART0 is in EM01GRPC or directly connected to oscillators */
|
||||
#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(eusart0clk)), DT_NODELABEL(em01grpcclk)) \
|
||||
? CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(eusart0clk)), DT_NODELABEL(hfrcoem23)) \
|
||||
? CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(eusart0clk)), DT_NODELABEL(lfrco)) \
|
||||
? CMU_EUSART0CLKCTRL_CLKSEL_LFRCO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(eusart0clk)), DT_NODELABEL(lfxo)) \
|
||||
? CMU_EUSART0CLKCTRL_CLKSEL_LFXO \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
#endif /* DT_NODE_EXISTS(em01grpbclk) */
|
||||
#if SL_CLOCK_MANAGER_EUSART0CLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for EUSART0CLK"
|
||||
#endif
|
||||
#endif /* DT_NUM_CLOCKS(eusart0clk) */
|
||||
#endif /* DT_NODE_EXISTS(eusart0clk) */
|
||||
|
||||
/* SYSTICKCLK */
|
||||
#if DT_NODE_EXISTS(DT_NODELABEL(systickclk))
|
||||
#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(systickclk)), DT_NODELABEL(hclk)) ? 0 \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(systickclk)), DT_NODELABEL(em23grpaclk)) \
|
||||
? 1 \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
|
||||
#if SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for SYSTICKCLK"
|
||||
#endif
|
||||
#endif /* DT_NODE_EXISTS(systickclk) */
|
||||
|
||||
/* VDAC0CLK */
|
||||
#if DT_NODE_EXISTS(DT_NODELABEL(vdac0clk))
|
||||
#if DT_NUM_CLOCKS(DT_NODELABEL(vdac0clk)) == 0
|
||||
#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_DISABLED
|
||||
#else
|
||||
#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(vdac0clk)), DT_NODELABEL(em01grpaclk)) \
|
||||
? CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(vdac0clk)), DT_NODELABEL(em23grpaclk)) \
|
||||
? CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(vdac0clk)), DT_NODELABEL(fsrco)) \
|
||||
? CMU_VDAC0CLKCTRL_CLKSEL_FSRCO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(vdac0clk)), DT_NODELABEL(hfrcoem23)) \
|
||||
? CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
|
||||
#if SL_CLOCK_MANAGER_VDAC0CLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for VDAC0CLK"
|
||||
#endif
|
||||
#endif /* DT_NUM_CLOCKS(vdac0clk) */
|
||||
#endif /* DT_NODE_EXISTS(vdac0clk) */
|
||||
|
||||
/* VDAC1CLK */
|
||||
#if DT_NODE_EXISTS(DT_NODELABEL(vdac1clk))
|
||||
#if DT_NUM_CLOCKS(DT_NODELABEL(vdac1clk)) == 0
|
||||
#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_DISABLED
|
||||
#else
|
||||
#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE \
|
||||
(DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(vdac1clk)), DT_NODELABEL(em01grpaclk)) \
|
||||
? CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(vdac1clk)), DT_NODELABEL(em23grpaclk)) \
|
||||
? CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(vdac1clk)), DT_NODELABEL(fsrco)) \
|
||||
? CMU_VDAC1CLKCTRL_CLKSEL_FSRCO \
|
||||
: DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(vdac1clk)), DT_NODELABEL(hfrcoem23)) \
|
||||
? CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 \
|
||||
: SL_CLOCK_MANAGER_INVALID)
|
||||
|
||||
#if SL_CLOCK_MANAGER_VDAC1CLK_SOURCE == SL_CLOCK_MANAGER_INVALID
|
||||
#error "Invalid clock source selection for VDAC1CLK"
|
||||
#endif
|
||||
#endif /* DT_NUM_CLOCKS(vdac1clk) */
|
||||
#endif /* DT_NODE_EXISTS(vdac1clk) */
|
||||
|
||||
#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */
|
|
@ -1,17 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Antmicro <www.antmicro.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H
|
||||
#define SL_DEVICE_INIT_HFXO_CONFIG_H
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
|
||||
#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal
|
||||
#define SL_DEVICE_INIT_HFXO_FREQ DT_PROP(DT_NODELABEL(clk_hfxo), clock_frequency)
|
||||
#define SL_DEVICE_INIT_HFXO_CTUNE DT_PROP(DT_NODELABEL(clk_hfxo), ctune)
|
||||
#define SL_DEVICE_INIT_HFXO_PRECISION DT_PROP(DT_NODELABEL(clk_hfxo), precision)
|
||||
|
||||
#endif /* SL_DEVICE_INIT_HFXO_CONFIG_H */
|
|
@ -21,8 +21,7 @@
|
|||
|
||||
#ifdef CONFIG_SOC_GECKO_DEV_INIT
|
||||
#include <sl_device_init_dcdc.h>
|
||||
#include <sl_device_init_dpll.h>
|
||||
#include <sl_device_init_hfxo.h>
|
||||
#include <sl_clock_manager_init.h>
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
#include <sl_hfxo_manager.h>
|
||||
|
@ -217,8 +216,7 @@ void soc_early_init_hook(void)
|
|||
if (DT_HAS_COMPAT_STATUS_OKAY(silabs_series2_dcdc)) {
|
||||
sl_device_init_dcdc();
|
||||
}
|
||||
sl_device_init_hfxo();
|
||||
sl_device_init_dpll();
|
||||
sl_clock_manager_init();
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
sl_power_manager_init();
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue