zephyr/soc/silabs
Jérôme Pouiller 2bbafa7072 soc: silabs: siwx91x: Allow alternative memory partition
Chip siwx91x has 672kB of SRAM shared between the Cortex-M4 (Zephyr) and
the NWP (Network Processor). 3 memory configurations are possible for
the Cortex-M4:
  - 196kB
  - 256kB
  - 320kB

Less memory is allocated to Zephyr, more memory is allocated to NWP,
better are the WiFi and BLE performances.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
2025-04-17 17:23:32 +02:00
..
common drivers: pinctrl: silabs: Add support for fixed routes 2025-04-07 08:54:38 +02:00
silabs_s0 soc: silabs: Introduce family specific defconfig 2024-10-22 20:41:23 +02:00
silabs_s1 soc: Remove re-defining some defined types 2024-11-18 07:41:23 -05:00
silabs_s2 drivers: timer: silabs: Fix calculation of next tick 2025-03-18 16:42:42 +01:00
silabs_sim3 soc: Remove re-defining some defined types 2024-11-18 07:41:23 -05:00
silabs_siwx91x soc: silabs: siwx91x: Allow alternative memory partition 2025-04-17 17:23:32 +02:00
CMakeLists.txt soc: silabs: Introduce new SoC SiWG917 2025-02-11 22:07:11 +01:00
Kconfig soc: silabs: add configuration to enable acmp module 2025-02-03 11:16:57 +01:00
Kconfig.defconfig drivers: bluetooth: silabs: Add separate thread for BT Link Layer 2025-01-21 11:11:36 +01:00
Kconfig.soc soc: silabs: Introduce new SoC SiWG917 2025-02-11 22:07:11 +01:00
soc.yml soc: silabs: Introduce new SoC SiWG917 2025-02-11 22:07:11 +01:00