Commit c6e3bac4f changed the core clock frequency of LPC55XXX series.
That clock is used by the cortex-m systick timer, which is the
default timer used for system time in zephyr on this series.
The bug is that the config SYS_CLOCK_HW_CYCLES_PER_SEC default was not
updated on the affected platforms to account for this change, so system
time is currently recorded as 150% of reality. Fix this by changing the
kconfig to be set automatically at SOC level and remove board defaults.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
For this SoC, an additional section is conditionally included on top of
the default linker script for Cortex-M. Set `SOC_LINKER_SCRIPT` to the
local `linker.ld`.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Remove CONFIG_IPM_IMX_REV2, as this Kconfig is no longer needed. The
driver can now be enabled with CONFIG_IPM_IMX.
Update NXP HAL to remove this Kconfig as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible
Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit updates all arm SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Locate common mpu code together with other arm / nxp mpu code in the
arch folder where it logically belongs.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add initial support for Renesas RA clock generation circuit.
It returns a fixed value to simplify the first commit to get the UART
working now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
PM should not be enabled by default at the soc level. This is an
application decision and not a platform decision whether to enable or
disable PM features.
Enabling PM by default will result in descripencies and test scope and
failures in tests that do not account for PM being enabled.
Fixes#60359
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Force STM32_ENABLE_DEBUG_SLEEP_STOP option when running tests.
This option enables Debug in Sleep/stop states and disables it when
disabled (default state).
When disabled, it may be impossible to flash the device with runner
such as openocd. It's generally working using cubeprogrammer, but it might
fail as well with fault configuration.
Instead of fixing each test or breaking CI each time a new test is created
with CONFIG_PM=y, force this option to be enabled when ZTEST=y (as it was
already the case when DEBUG=y).
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Cortex-R52 supports both Arm and Thumb-2 mode, but Zephyr's ASM
code for Armv-8 Aarch32 is written for Arm mode only. This Soc
has a general purpose register that can set the core TEINIT signal
to change the mode exceptions are taken before booting up the core.
The debugger startup scripts or firmware booting up the core may
configure this bit to Thumb mode, as is the case of the NXP S32 debug
probe startup scripts for S32ZE.
Due to above reason, clear SCTLR.TE bit at reset so that TEINIT value
is ignored and exceptions are always taken into Arm mode, compatible
with current Zephyr ASM code. At least until taking execeptions in Thumb
mode is supported in Zephyr.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit adds an implementation of poweroff, which first
uses SUPC to enable all defined wakeup sources (except for
sam4l), followed by entering backup mode.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Now the API to manage GPREGRET register is unified for all devices
having one or more GPREGRET entries.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Add generic SoC support for the supported nordic SoCs:
- nrf5340
- nrf9160
- nrf9120
Add generic SoC support by taking board specific configurations from
zephyr devicetree and kconfig.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Let's make the sync_rtc kconfig depend on the SOC_COMPATIBLE
options which are set both by the real and simulated targets,
so this code works in the same way for both.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The Kconfig option HAS_PM, which must be needed for SoCs providing PM
hooks, is missing in npcx4.
This commit adds it to soc/arm/nuvoton_npcx/npcx4/Kconfig.series.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commits adds the DA14695 variant.
The main difference with the DA14699 is a smaller package with less
GPIO.
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
- if we have input enable use CY_GPIO_DM_xxxx else
CY_GPIO_DM_xxx_IN_OFF;
- added bias_high_impedance option
- Updated HIGHZ drive mode, now it sets if:
--- we have bias_high_impedance
--- or if input_enable and no addition bias mode
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Coupling in code between workarounds for anomaly 160 and anomaly 165
(pretick) is decreased.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
It might happen that while some interrupt handler other than for RTC0
or RTC1 (e.g. for RADIO) is executed, the scheduled pretick CC triggers.
This starts pretick pulses due to the loop through IPC. The change
in pretick schedule did not stop the pretick pulses going through IPC
loop, what caused heavy increase in power consumption.
This commit fixes this behavior.
Added also clarifications for Kconfig option `SOC_NRF53_RTC_PRETICK`.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
For RTC0 events the RTC1 pretick event was not cleared what caused the
WDT to be not stopped. This resulted in increased power usage.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
rand32.h does not make much sense, since the random subsystem
provides more APIs than just getting a random 32 bits value.
Rename it to random.h and get consistently with other
subsystems.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Do not clock the LPC55xxx cores from PLL1 when CONFIG_FLASH is set. This
is required due to the following limitation of the flash controller
(documented in the reference manual):
Flash operations (erase, blank check, program) and reading a single word
can only be performed for CPU frequencies of up to 100 MHz. These
operations cannot be performed for frequencies above 100 MHz.
The PLL1 clock source will result in a core clock of 150MHz, which
violates this requirement.
Fixes#62963
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added SOC_GECKO_HAS_RADIO symbol, to indicate that a SoC has a radio
phy, so that radio related code would only apply to devices with radio.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
The `SOC_NRF53_RTC_PRETICK` option is now allowed to be used with
`NRF_802154_RADIO_DRIVER`.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
The nrf53 pretick can be used with non-zero
`NRF_RTC_TIMER_USER_CHAN_COUNT` Kconfig option.
The nrf53 pretick requires just one RTC1 CC channel.
The nrf53 pretick handles also RTC1 and RTC0 both CCs and OVERFLOW
events by examination of events scheduled on them. The pretick is set
based on number of ticks to the closest event scheduled that can trigger
an interrupt.
Because the operation in `z_arm_on_enter_cpu_idle` hook would
take too much time with interrupts disabled, the
`z_arm_on_enter_cpu_idle_prepare` hook enabled by Kconfig option
`ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK` is used. It performs RTC0 and RTC1
examination, and sets pretick without interrupts being blocked.
The LDREX/STREX are leveraged to detect if exception took place
between start of `z_arm_on_enter_cpu_idle_prepare` and
`z_arm_on_enter_cpu_idle`. If exception has not been taken, the pretick
calculation can be trusted because source data could not changed and
too much time could not pass. Otherwise the sleep attempt is disallowed,
the idle will loop again and try later.
Prompt for `SOC_NRF53_RTC_PRETICK` Kconfig option allows to control
this option by an user and turn the feature off if necessary.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Add RTC pretick option that triggers HW activity one tick before and
RTC event that leads to the interrupt. Option is active only on nrf53
network core.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
On S32K344, the offset in memory map between each channel
is 0x4000 for most channels, but there is specific case is
between channel 11 and 12 which is 0x1D4000 instead. As a
consequence, 32 channels are divided to two parts: one
starts from channel 0 -> 11. The other is from channel 128
to 145. The channel gap is from 12 -> 127.
For user and data structures in shim driver, the channel's
value comes from 0 --> 31. Above constraint will be counted
when interact with the mcux sdk
Beside that, the DMAMUX register in this platform is very
specific, not in identical with DMAMUX channel, so shim
driver is updated to cover this case
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
MEC172X has 2 package sizes with additional pins on the -LJ package.
This commit separates the package-specific parts into different files.
In addition, this patch removes unnecessary package-specific enums in
favor of calculated offsets into the desired registers.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
These headers are using things like `uint32_t` & devicetree
macros, so they should include the `devicetree.h` & `types.h`.
Otherwise they depend on the parent file to have those headers
included before they are included.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Select the newly introduced nrf53 compatible kconfig options.
These are common both for real HW and for simulated HW,
allowing SW to behave appropriately for both.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add support for SMARTDMA to RT5xx SOCs. SMARTDMA ram banks will be
powered up, so code can be programmed into this region for the SMARTDMA
engine.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP to allow debugger attaching in
sleep/stop mode of STM32 parts. Mainly useful for debugging. Move DBGMCU
from part-sepcific power.c to common soc_config.c. CONFIG_USE_SEGGER_RTT
depends on this as well.
Signed-off-by: Roland Lezuo <roland.lezuo@embedded-solutions.at>
Add node for VREF0 peripheral to LPC55S3X SOC DT
Clock VREF peripheral if status = okay in DT
Enable VREF on lpcxpresso55s36
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
