Commit graph

1403 commits

Author SHA1 Message Date
Kumar Gala
128d2e2bd1 soc: riscv32: openisa_rv32m1: Support Zephyr toolchain
The 0.10 version of the Zephyr toolchain supports building on the
openisa_rv32m1 SoC.  So if the ZEPHYR_TOOLCHAIN_VARIANT is 'zephyr'
than select RISCV_GENERIC_TOOLCHAIN.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-02-06 14:25:47 +01:00
Piotr Zięcik
b6bf56c3fc power: pm_ctrl: Allow fine-grained power state locking
This commit enables fine-grained power state locking.
Now, each power state could be independently enabled or disabled.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-02-06 14:24:01 +01:00
Daniel Leung
f7a42a70f8 gpio: intel_apl: rework driver for pin_mask callback
To avoid confusion, callbacks using ordinal pin numbers
is going to be reverted. So the driver has to be re-worked
to expose multiple devices so each device has 32 pins.

Also fixes #12765

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-06 07:18:15 -05:00
Daniel Leung
7695a72e3c drivers/interrupt_controller: shared_irq: configure by device tree
This allows the shared_irq driver to be configured by device tree.
With previous implementation, only the board configuration can
override the IRQ trigger, as the trigger config is a "choice" rather
than "config". With this patch, the driver can be fully configued at
the SoC level.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-06 07:18:15 -05:00
Andrew Boie
2d9bbdf5f3 x86: remove support for non-PAE page tables
PAE tables introduce the NX bit which is very desirable
from a security perspetive, back in 1995.

PAE tables are larger, but we are not targeting x86 memory
protection for RAM constrained devices.

Remove the old style 32-bit tables to make the x86 port
easier to maintain.

Renamed some verbosely named data structures, and fixed
incorrect number of entries for the page directory
pointer table.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-05 20:51:21 -08:00
Aurelien Jarno
847a33d161 soc: same70: always enable data cache
Now that the SAM Ethernet driver can work when the cached is enabled, it
is possible to unconditionally enable the data cache on the SAM E70 SoC.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-02-05 15:03:35 -06:00
Piotr Zięcik
28576260c3 power: Remove sys_is_valid_power_state() interface
Each platform is now specifying list of supported power states
as a Kconfig options. Some of the specified states could be
disabled in runtime. As result there is no need for the removed
interface.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-02-04 18:08:47 +01:00
Piotr Zięcik
fdb62f7565 power: Make power_state enum global
Currently each SoC has to define own list of power states.
However all these definitions have to be the same, as common power
management code uses them.

This commit replaces per-soc power state list by global definition.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-02-04 13:36:29 +01:00
Sathish Kuttan
04e72b7dae soc: intel_s1000: Encoded IRQ definitions for I2S
Use IRQ encoding macro to define the IRQ identifiers for I2S

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-02-04 00:52:15 -05:00
Sathish Kuttan
22c217b7ba soc: intel_s1000: Macro to encode multi-level IRQ
Add Macro to encode multi-level aggregation of interrupts
into an encoded IRQ value

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-02-04 00:52:15 -05:00
Erwan Gouriou
7ae381a808 drivers/watchdog: stm32: move driver to dts based configuration
STM32 watchdog driver is now configured from device tree settings.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-02-01 19:16:59 -05:00
Erwan Gouriou
1a05f2fae3 soc: stm32: Extended watchdog support to all series
STM32F2, STM32F7 and STM32L0 were missing wtachdog API support.
Fix this.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-02-01 19:16:59 -05:00
Daniel Leung
659c892b29 soc/intel_s1000: update DTS fixup due to CONFIG_SRAM_* changes
Commit ce7ed18989 moved CONFIG_SRAM_*
so dts_fixup.h needs to be updated for properly generated linker
script.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-01 19:14:29 -05:00
Piotr Mienkowski
bca692ee8c drivers: i2c_gecko: use DT_<COMPAT>_<INSTANCE>_<PROP> defines
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-02-01 19:09:06 -05:00
Kumar Gala
55e02d2b99 soc: riscv32: openisa_rv32m1: Remove duplicated HAS_DTS
HAS_DTS is selected at the arch level so we don't need to duplicate the
select in the SoC Kconfig.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-02-01 12:44:21 -06:00
Savinay Dharmappa
40e0f18e21 dts: qemu_xtensa/xt-sim: Enable device tree support
patch enables dts support for boards qemu_xtensa and xt-sim

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2019-02-01 07:49:28 -06:00
Piotr Mienkowski
91786e96aa drivers: leuart_gecko: use DT_<COMPAT>_<INSTANCE>_<PROP> defines
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-02-01 04:18:50 -06:00
Kumar Gala
d3623a2fba soc: xtensa: intel_s1000: Encode IRQ in dts
Move IRQ number encoding out of dts_fixup.h and into the dtsi files.
For now just change devices on the dw_intc.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-02-01 04:09:01 -06:00
Anas Nashif
a93651085e boards: remove pulpino board
This board is unmaintained and unsupported. It is not known to work and
has lots of conditional code across the tree that makes code
unmaintainable.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-01-31 22:47:18 -05:00
Andrei Gansari
6d36f2e2f4 mimxrt1050_evk: cache enable
Cacheing mechanisms enabled and non-cache area added.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-01-31 13:22:58 -06:00
Piotr Zięcik
2587ed0090 soc: arm: nrf51: Backport power management code from nRF52
This commit ports power management code from nRF52 to the nRF51 SoC,
enabling usage of Zephyr Power Management policies on this platform.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-01-31 17:39:27 +01:00
Piotr Zięcik
4ce523094f soc: arm: nrf52: Update power management code for nRF52
This commit updates the power management code for nRF52 SoC
series after recent changes in Zephyr power management subsystem.

Changes:
- Removed LPS modes, as they are not supported by HW.
  (previous implemntation used CONSTLAT and LOWPWR settings
  in NRF_POWER to implement low power modes, however these
  knobs should be used only when application needs ultra low
  CPU wake-up time).

- Reworked code in order to allow adding custom power levels
  on the application level and provide better integration
  with power management subsystem.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-01-31 17:39:27 +01:00
Wayne Ren
1e392fbd0a drivers: uart_ns16550: remove soc specific codes and bug fixes
* remove soc specific codes
* optimize the caculation of baudrate.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-01-31 09:03:41 -05:00
Erwan Gouriou
a985e03349 drivers/interrupt_controller: stm32: Use LL API
exti driver implementation does not fit all SoCs because
some EXTI ip does not match stm32_exti register map provided.
Instead of providing exti register map for all SoCs, use LL API
which abstracts IP variations and enable uniform use of the drivers
on all STM32SoCs.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-01-31 03:18:36 -06:00
Piotr Mienkowski
a148e11e2a drivers: uart_gecko: use DT_<COMPAT>_<INSTANCE>_<PROP> defines
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-01-31 03:14:51 -06:00
Michael Scott
3588b94b06 drivers: serial: mcux: Introduce support for HW flow control
Now that a hw-flow-control DTS binding has been added for MCUX uart,
let's check for the DT_ define and enable support in the MCUX HAL
layer.

Signed-off-by: Michael Scott <mike@foundries.io>
2019-01-30 02:53:12 -06:00
Martin Benda
9653e15139 drivers: timer: Add RTC-based system timer for Atmel SAM0 series MCU
Add sam0_rtc_driver that implements system timer API on top of the RTC
and can be used as a replacement for the default systick timer.

Signed-off-by: Martin Benda <martin.benda@omsquare.com>
2019-01-29 17:58:05 +01:00
Savinay Dharmappa
3bec750268 dts: xtensa: esp32: Add device tree support.
add device tree support for esp32

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2019-01-29 09:47:17 -06:00
Maureen Helm
501db1e0b9 soc: nxp_imx: Promote driver defaults to soc series level
Streamlines repetitious code enabling default drivers by promoting it to
the soc series level.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-28 21:21:01 -05:00
Maureen Helm
605e599b1a ext: mcux: Add HAS_MCUX_ENET config
Adds a new config HAS_MCUX_ENET to constrain which socs can enable the
mcux ethernet driver. This will prevent users from enabling the driver
on socs like kl25z or kw41z which do not have ethernet mac hardware.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-28 21:21:01 -05:00
Ioannis Glaropoulos
2a3852fc75 soc: nrf: add include of nrfx_config_nrf9160.h in nrf9160 soc.h
In soc.h of nRF9160 SoC we need to explicitly include
nrfx_config_nrf9160.h to have the standard peripheral
base address macro mappings in Zephyr builds for nRF9160
SoC. (We need to do this spefically for nRF9160, as those
macros are not present in the nRF9160 MDK header).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-01-25 22:16:49 +01:00
Michael Scott
13c794bc1c serial: RV32M1: introduce lpuart driver / DT bindings
Add a UART driver.

Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Marti Bolivar <marti@foundries.io>
2019-01-25 11:59:46 -05:00
Michael Scott
0f314ebdda gpio: RV32M1: introduce gpio driver / DT bindings
Add a GPIO driver.

Signed-off-by: Michael Scott <mike@foundries.io>
2019-01-25 11:59:46 -05:00
Michael Scott
cdb1714c6c pinmux: RV32M1: introduce pinmux driver / DT bindings
Add a pinmux driver.

Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Marti Bolivar <marti@foundries.io>
2019-01-25 11:59:46 -05:00
Marti Bolivar
58d8afb476 interrupt_controller: RV32M1: add intmux driver / DT bindings
Add a level 2 interrupt controller for the RV32M1 SoC. This uses the
INTMUX peripheral.

As a first customer, convert the timer driver over to using this,
adding nodes for the LPTMR peripherals. This lets users select the
timer instance they want to use, and what intmux channel they want to
route its interrupt to, using DT overlays.

Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Mike Scott <mike@foundries.io>
2019-01-25 11:59:46 -05:00
Michael Scott
521f4778a1 clock_control: RV32M1: introduce PCC driver / DT bindings
Add a Peripheral Clock Controller (PCC) driver. This gates and ungates
clocks to various peripherals on the SoC.

Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Marti Bolivar <marti@foundries.io>
2019-01-25 11:59:46 -05:00
Marti Bolivar
502d306630 soc: riscv32: add RV32M1 SoC as openisa_rv32m1
The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V
32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two
cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC
enablement for the RISC-V cores:

- basic dtsi, to be extended as additional drivers are added
- SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY
- system timer driver for RI5CY, based on LPTMR0 peripheral

The timer driver will be generalized a bit soon once proper
multi-level interrupt support is available.

Emphasis is on supporting the RI5CY core as the more capable of the
two; the ZERO-RISCY SoC definitions are a good starting point, but
additional work setting up a dtsi and initial drivers is needed to
support that core.

Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Michael Scott <mike@foundries.io>
2019-01-25 11:59:46 -05:00
Kumar Gala
61cb8b6c4f drivers: wdog: cmsdk: Convert to new DT_<COMPAT>_<INSTANCE> defines
Convert cmsdk driver to use new defines so we can remove the
dts_fixup.h code for it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-01-25 08:55:06 -06:00
Kumar Gala
4b6cec44ff drivers: uart: cmsdk_apb: Convert to new DT_<COMPAT>_<INSTANCE> defines
Convert cmsdk_apb driver to use new defines so we can remove the
dts_fixup.h code for it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-01-25 08:55:06 -06:00
Ryan QIAN
fe9ea3b26c arch: arm: nxp: imxrt1064: add device support
- Add SoC information for RT1064

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-24 07:59:52 -06:00
Georgij Cernysiov
3b77737208 soc: st: add STM32L452XC
Adds STM32 L452 soc with L452xC variant. L452 has 160 KB SRAM;
therefore, mpu mem config has been extended; IRQ number is based on
'stm32l452xx.h'.

Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
2019-01-23 03:19:15 -06:00
Aurelien Jarno
0e7a6ec9ab boards: mimxrt1020_evk: Enable mcux ethernet driver and pins
Enables the mcux ethernet driver and pin muxes on the mimxrt1020_evk
board, the same way it is done on the mimxrt1050_evk board. Updates the
board documentation and yaml supported list accordingly.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-01-22 08:37:39 -06:00
Aurelien Jarno
ba459d002c soc: nxp_imx: Fix enabling ENET PLL outputs
The ENET PLL should be enabled if the SoC is the MIMXRT1021 (it used by
the ARM core) or if the ENET device is enabled.

The 500MHz clock should be enabled if the SoC is the MIMXRT1021.

The ENET clock should be enabled if the ENET device is enabled.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-01-22 08:37:39 -06:00
Aurelien Jarno
17f4d6bec7 soc: nxp_imx: fix ENET_PLL selection for MIMXRT1021
Kconfig currently emits a warning when building for a MIMXRT1021 SoC:

  warning: INIT_ENET_PLL (defined at
  soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052:66) has direct
  dependencies NET_L2_ETHERNET && SOC_MIMXRT1052 && SOC_SERIES_IMX_RT
  with value n, but is currently being y-selected by the following
  symbols:
   - SOC_MIMXRT1021 (defined at soc/arm/nxp_imx/rt/Kconfig.soc:12),
  with value y, direct dependencies <choice> (value: y), and select
  condition <choice> (value: y)

This is due to the fact the ENET PLL is the one used by the ARM core on
the MIMXRT1021 so it is always enabled, while it is declared protected
by NET_L2_ETHERNET and SOC_SERIES_IMX_RT.

Fix that by declaring the symbol in Kconfig.defconfig.series.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-01-22 08:37:39 -06:00
Ioannis Glaropoulos
704e4b446b soc: nrf: clean up inclusions and style fixes
Remove redundant inclusion of nrf.h (included by nrfx.h).
Group the logging/log.h inclusion together with the other
inclusions in this file (make inclusions' list look as in
nrf9160/soc.c).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-01-18 18:27:12 -05:00
Ioannis Glaropoulos
bc5b8e24fe soc: nrf: remove unnecessary macros in mpu_regions.c
Remove the locally-defined macros which define the base
addresses for XICR, Peripheral space and PPB. The macros
are not used.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-01-18 18:27:12 -05:00
Kumar Gala
717b647c30 ieee802154: mcr20a: Convert to new DT_<COMPAT>_<INSTANCE> defines
Convert mcr20a driver to use new defines so we can remove the
dts_fixup.h code for it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-01-18 09:06:10 -06:00
Anas Nashif
15a5fedca7 qmsi: remove handling of qmsi library
Use built-in by default. We do not use external library of QMSI anymore
and rely on integrated HAL. Remove this option and simplify HAL
configuration.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-01-18 06:50:04 -05:00
Maureen Helm
9cad30814d soc: nxp_imx: Enable mcux lpi2c driver and clocks
Enables the mcux lpi2c shim driver and clocks on all imx rt socs when
the i2c driver interface is enabled.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-18 06:49:35 -05:00
Rajavardhan Gundi
e584b05215 dts: intel_s1000: Exclude sram space dedicated for mcubootloader
The starting 192kB SRAM is reserved for the mcubootloader. Exclude
this region while building an application to be loaded by mcubootloader.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2019-01-16 21:22:56 -05:00