drivers/watchdog: stm32: move driver to dts based configuration
STM32 watchdog driver is now configured from device tree settings. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
parent
12166b61ee
commit
7ae381a808
10 changed files with 15 additions and 3 deletions
|
@ -9,6 +9,7 @@
|
|||
menuconfig IWDG_STM32
|
||||
bool "Independent Watchdog (IWDG) Driver for STM32 family of MCUs"
|
||||
depends on SOC_FAMILY_STM32
|
||||
select HAS_DTS_WDT
|
||||
help
|
||||
Enable IWDG driver for STM32 line of MCUs
|
||||
|
||||
|
|
|
@ -172,11 +172,10 @@ static int iwdg_stm32_init(struct device *dev)
|
|||
}
|
||||
|
||||
static struct iwdg_stm32_data iwdg_stm32_dev_data = {
|
||||
.Instance = IWDG
|
||||
.Instance = (IWDG_TypeDef *)DT_ST_STM32_WATCHDOG_0_BASE_ADDRESS
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(iwdg_stm32, CONFIG_WDT_0_NAME,
|
||||
DEVICE_AND_API_INIT(iwdg_stm32, DT_ST_STM32_WATCHDOG_0_LABEL,
|
||||
iwdg_stm32_init, &iwdg_stm32_dev_data, NULL,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&iwdg_stm32_api);
|
||||
|
||||
|
|
|
@ -177,4 +177,6 @@
|
|||
#define DT_TIM_STM32_17_CLOCK_BITS DT_ST_STM32_TIMERS_40014800_CLOCK_BITS
|
||||
#define DT_TIM_STM32_17_CLOCK_BUS DT_ST_STM32_TIMERS_40014800_CLOCK_BUS
|
||||
|
||||
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -198,4 +198,6 @@
|
|||
#define DT_TIM_STM32_8_CLOCK_BITS DT_ST_STM32_TIMERS_40013400_CLOCK_BITS
|
||||
#define DT_TIM_STM32_8_CLOCK_BUS DT_ST_STM32_TIMERS_40013400_CLOCK_BUS
|
||||
|
||||
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -138,4 +138,6 @@
|
|||
#define DT_USB_RAM_SIZE DT_ST_STM32_OTGFS_50000000_RAM_SIZE
|
||||
#define DT_USB_MAXIMUM_SPEED DT_ST_STM32_OTGFS_50000000_MAXIMUM_SPEED
|
||||
|
||||
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -254,4 +254,6 @@
|
|||
#define DT_RTC_0_IRQ DT_ST_STM32_RTC_40002800_IRQ_0
|
||||
#define CONFIG_RTC_0_NAME DT_ST_STM32_RTC_40002800_LABEL
|
||||
#define CONFIG_RTC_PRESCALER DT_ST_STM32_RTC_40002800_PRESCALER
|
||||
|
||||
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -366,4 +366,5 @@
|
|||
#define CONFIG_RTC_0_NAME DT_ST_STM32_RTC_40002800_LABEL
|
||||
#define CONFIG_RTC_PRESCALER DT_ST_STM32_RTC_40002800_PRESCALER
|
||||
|
||||
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -358,4 +358,5 @@
|
|||
#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32F7_FLASH_CONTROLLER_40023C00_BASE_ADDRESS
|
||||
#define DT_FLASH_DEV_NAME DT_ST_STM32F7_FLASH_CONTROLLER_40023C00_LABEL
|
||||
|
||||
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -126,4 +126,5 @@
|
|||
#define DT_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS
|
||||
#define DT_USB_RAM_SIZE DT_ST_STM32_USB_40005C00_RAM_SIZE
|
||||
|
||||
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -298,4 +298,5 @@
|
|||
#define DT_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS
|
||||
#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS
|
||||
|
||||
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue