Add support for specifying PWM flags for the NXP Kinetis FlexTimer
(FTM) PWM driver through the device tree.
All in-tree clients of this PWM controller are active-low LEDs.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit fixes the following problems with the RPU device tree:
1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not
Cortex-R4.
2. RPU and APU use different interrupt controllers (PL390 GICv1 and
GIC-400 GICv2, respectively) mapped to the same CPU local bus address
region but with different offsets for the distributor and CPU
interrupt control register sets. The GIC address mapping specified by
the current dts is that of an APU and does not apply to the PL390
GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register
Reference" document from Xilinx for more information).
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and
Cortex-A for APU.
Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within one project, the RPU and APU should be considered
separate platforms.
This commit relocates the device tree nodes that are not common between
RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi).
When Cortex-A53 APU support is added in the future, an additional dtsi
file (zynqmp_apu.dtsi) for specifying the APU device tree should be
added.
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This enables LiteX PRBS random number generator driver
for litex_vexriscv board.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This adds PRBS ranom number generator driver for
LiteX SoC builder with its bindings.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Rename the NXP FTM instances in the KE1xF SoC to PWM to match the
other SoCs/boards using the FlexTimer as PWM generator.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Johann Fischer pointed out that the driver for this sensor
(master/drivers/sensor/tmp116/tmp116.c) doesn't use GPIOs, in
https://github.com/zephyrproject-rtos/zephyr/pull/21605, though there
seems to be an ALERT pin from looking at the datasheet
(http://www.ti.com/lit/ds/symlink/tmp116.pdf).
Remove the unused property declaration.
I was originally just going to change a 'category: optional' to
'required: false' (and 'type: compound' to 'type: phandle-array').
Either solution is fine with me. Could keep the declaration if people
are planning to use it soon.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
'category' is deprecated. See commit fcd665a26c ("dts: bindings: Have
'required: true/false' instead of 'category: ...'").
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This patchset enables USART3 on the 96Boards STM32 Mezzanine.
It is broken out to J10 Grove Connector.
Changes:
- Enabled USART3 in board dts.
- Updated board index.rst with uart pinouts.
- soc dtsi: enabled usart3.
Test: Tested USART3 as console at 115200 baud
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Define a binding for the Aosong DHT family of temperature/humidity
sensors. Remove the Kconfig settings, and update the driver to use
devicetree information.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Currently most SPI NOR serial flash devices are accessed through the
spi-nor flash driver, but there are pending enhancements that will
access these devices through other driver implementations. Several of
the descriptive properties of the flash memories are common regardless
of the interface selected. Pull those out to a separate yaml file to
be included into the bindings for interface-specific node descriptions.
Also revise the documentation to note that the jedec,spi-nor
compatible depends on a commands set compatible with the Micron M25P80
serial nor flash; there is no JEDEC standard for these commands.
These devices do generally provide descriptive structures defined by
JESD216, but currently Zephyr doesn't make use of these structures.
The JEDEC CFI standard previously referenced in the description is not
relevant to these devices.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
I keep mixing these up, so that's probably a sign that the names are
bad. The root of the problem is that "parent-bus" can be read as both
"this is the parent bus" and as "the parent bus is this".
Use 'bus:' for the bus "provider" and 'on-bus:' for nodes on the bus
instead, which is less confusing.
Support the old keys for backwards compatibility, along with a
deprecation warning.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This patch enables SPI4 on the 96Boards STM32 Sensors Mezzanine.
SPI4 has been broken out to a Grove Connector on the board.
Changes:
- Updated board dts to enable spi4
- Updated board Kconfig
- Updated board documentation
- Update board pinmux
- Updated stm32f4 pinmux header file
- Updated stm32f401 dtsi
- Updated stm32f4 defconfig to enable PORTE GPIO
- Added board to spi_loopback test
Test: spi_loopback test passed
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Add any useful information from 'title:' to the 'description:' strings
(e.g. explanations of acronyms), and remove 'title:' as well as any
copy-pasted "this binding gives a ..." boilerplate.
Also clean some description strings up a bit.
Some other things could probably be cleaned up (replacing 'GPIO node'
with 'GPIO controller' on controllers for consistency, for example), but
I kept things close to the original to avoid accidentally messing up.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Most bindings look something like this:
title: Foo
description: This binding provides a base representation of Foo
That kind of description doesn't add any useful information, as it's
just the title along with some copy-pasted text. I'm not sure what "base
representation" was supposed to mean originally either.
Many bindings also put something that's closer to a description in the
title, because it's not clear what's expected or how the title is used.
In reality, the title isn't used anywhere. 'description:' on the other
hand shows up as a comment in the generated header.
Deprecate 'title:' and generate a long informative warning if it shows
up in a binding.
Next commits will clean up the 'description:' strings (bringing them
closer to 'title:' in most cases) and remove 'title:' from all bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This is just a cosmetic change to avoid a warning:
"unit-address and first reg (0xb0000000)
don't match for ethernet@e0009800"
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and
.yaml files.
Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.
Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst
to get rid of the trailing blank line there. It was probably misplaced.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Adds spi device tree bindings and nodes for the lpc54xxx and lpc55s6x
socs in preparation for adding a new spi driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The GIC-400 driver currently only supports SPIs because the (32) offset
for the INTIDs is hard-coded in the driver. At the driver level there is
no really difference between PPIs and SPIs so we can easily extend the
driver to support PPIs as well.
This is useful if we want to add support for the ARM Generic Timers that
use INTIDs in the PPI range.
SPI interrupts are in the range [0-987]. PPI interrupts are in the range
[0-15].
This commit adds interrupt 'type' cell to the GIC device tree binding
and changes the 'irq' cell to use interrupt type-specific index, rather
than a linear IRQ number.
The 'type'+'irq (index)' combo is automatically fixed up into a linear
IRQ number by the scripts/dts/gen_defines.py script.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add property for specifying the bus idle timeout for the NXP
i.MX/Kinetis LPI2C I2C controller.
Enabling the bus idle timeout helps the controller to recover from
e.g. EMC causing false clock pulses/spikes on the SCL line.
Without a timeout the LPI2C controller will assume that another bus
master took over the I2C bus and thus refuses to issue a I2C START
condition.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
On power-on boot-ROM is mapped to address 0 in HSDK board.
Normally later when U-Boot gets started by boot-ROM we change mappings
so that real DDR is mapped to entire address space including 0:
https://elixir.bootlin.com/u-boot/latest/source/board/synopsys/hsdk/hsdk.c#L474
But if U-Boot is not started (which is controlled by the BIM dip-switch
on the board) boot-ROM remains mapped to 0, and essentially any attempt
to write to that location fails, thus we cannot upload contents of our
target Elf there even with JTAG.
The next logical option is to use beginning of the non-translated
memory region 0x8000_0000 which we typically use for loading
U-Boot & Linux kernel on ARC boards. But in case of HSDK
we have DCCM (Data Closely-Coupled MEmory - fast on-chip SRAM)
mapped there and since we cannot execute code from DCCM
we need to skip that region as well which gives us the next option
being 0x9000_0000 . That's because DCCM owns entire 256 MiB "aperture"
even though it may have much smaller size up-to 8 MiB.
We are mapping only 5 apertures because the last two
(0xe000_0000-0xffff_ffff) are used for peripherals and AXI.
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Erroring out for 'status = "ok"' broke backwards compatibility for a
downstream project. Accept it instead.
Maybe the error could be selectively re-enabled later.
The rest of the code only checks for 'status = "disabled"' (like the old
scripts), so no other updates are needed.
(It's a bit weird that we duplicate the property check in base.yaml.
Thinking of including base.yaml implicitly. Could clean things up then.)
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Add support for the built-in Programmable Interrupt Controller
found in the SweRV EH1 RISC-V CPU
Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
After switching to nrfx 2.0.0, the Kconfig choice options that allowed
enabling of pull-up or pull-down for MISO lines in SPIs and SPIMs are
not properly supported, they are simply ignored. This commit restores
the possibility of applying pull configuration for MISO lines.
In earlier nrfx versions, the MISO pull configuration could be only
set globally, in nrfx_config files, for all SPI and SPIM instances
together. Since nrfx 2.0.0, this configuration can be applied per
instance. This commit takes advantage of this possibility and instead
of using a common Kconfig option as a global setting for all instances,
allows applying individual instance settings via devicetree.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add new bindings for already supported (by lis2dh.c driver) lsm303agr
accelerometer. Using st,lsm303agr-accel compatible will allow in
subsequent commit to apply different sensitivity scale.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Add device tree elements for all gpio ports of the efr32mg12p including
the dts fixup entries.
Also remove gpio port e since this is not available in efr32mg12p socs.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
NXP's LPC family of MCU's GPIOs parameters is udated.
Boards LPC54xxx and LPC55xxx have updated values according
pin and interrupt layout.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This commit adds basic support for nRF52833 SoC.
Changes affect introducing:
- architecuture files (dtsi)
- configuration of nrfx drivers
- adaptation of inclusions based on chosen SoC
- configuration of NFCT_PINS_AS_GPIOS depends on HAS_HW_NRF_NFCT.
Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
This patch introduces the support of the Low Power Timer
for the STM32WBxx from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Provide a clear description of the how the binding maps nexus parent
pin indexes to header pin locations. Also use the standard name "Uno"
when identifying the header physical layout, contrasted with Mega/Due
which is a different physical layout.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Provide information required to allow the driver to put the flash chip
into a deep power down mode. This can reduce standby current by as
much as 90%.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The SPI NOR driver requires that the size (in bits) be provided in the
devicetree node. Update the binding to make the property required,
and update all nodes based on the memory chip identified.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
