This breaks down the GPIO controller definition in DTS into
multiple entries. This allows these controllers to be
referenced by other DTS, and test board overlay files.
And also we can remove the entries in the dts fixup file.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There were complains about the unit-address and first reg
not matching. So update the DTS file to match.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Converts the fxos8700 sensor driver to the new gpio api. Updates device
trees for all boards with this sensor to active low gpio interrupts by
default.
Tested on frdm_k64f and rv32m1_vega_ri5cy boards. The latter verifies
that the reset output works correctly.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Converts the usdhc driver to the new gpio api. Updates the
device tree for the mimxrt1050_evk board to set appropriate active
high/low polarity for the power and card detect pins.
Note that the driver doesn't actually support interrupts yet. It
initializes a gpio callback for the card detect pin, but never actually
enables the gpio interrupt. This incomplete behavior is left as-is,
since the purpose of this patch is only to convert the driver to the new
gpio api, not to add new features.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commits adds GPIO driver for LiteX SoC builder.
Due to the fact that GPIO in LiteX is unidirectional and can be
configured with different pins amount per port, additional entries
were added to the dts file.
Signed-off-by: Robert Winkler <rwinkler@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
IO extenders may provide input signals to LEDs or sensors where
leaving the signal undriven may result in increased power consumption
or misbehavior. The SX1509B powers up with all signals configured as
inputs. Provide a way to indicate which pins should be set as output,
and their initial signal level, when the device is configured.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Update ALERT active level in all devicetree files. Capture GPIO flags
in static configuration. Add internal API to enable and disable
interrupt, to release the handlers when an alert occurs, and to
re-enable the signal when the handler completes. Check for alerts
received during periods when the interrupt was disabled.
Extend the example to handle both above and below range triggers and
alerts that are present on startup.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Convert the GPIO based driver to the new GPIO API. (Only the
gpio_configure() call is affected).
Move configuration to DT where appropriate for both SPI and GPIO
drivers, only leaving the SPI vs. GPIO decision in Kconfig (in
addition to the basic enable for the driver.) Move some files around
to clean up as a result of this change.
led_ws2812 sample changes:
- make the pattern easier to look at by emitting less light
- use led_strip alias from DT to get strip device, allocate
appropriate struct led_rgb buffer, etc.
- move the pins around and remove 96b_carbon support (I have no board
to test with)
GPIO driver specific changes:
- str is required to write OUTSET/OUTCLR, not strb. The registers
are word-sized.
- the str[b] registers must all be in r0-r7, so "l" is the correct GCC
inline assembly constraint for both "base" and "pin"
SPI driver specific changes:
- match the GPIO driver in not supporting the update_channels API
method, which never made sense for this type of strip
- return -ENOMEM when the user tries to send more pixel data
than we have buffer space for instead of -EINVAL
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Mark the INT signal to be active low and use the new functions to get
gpio state and configure the gpio interrupt flanks.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
Correct DRDY active level to default active-high, switch to new
interrupt configuration.
Also fix a common bug where an already-active DRDY signal is not
properly handled.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This commit adds the following:
- EFR32FG1P SoC support for the watchdog
- efr32_slwstk6061a board support for the watchdog
Signed-off-by: Oane Kingma <o.kingma@interay.com>
This commit adds the following:
- EFR32MG SoC support for the watchdog
- efr32mg_sltb004a board support for the watchdog
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
This commit adds the following:
- device tree bindings for Gecko watchdog driver
- EFM32PG SOC support for the watchdog driver
- EFM32PG board support for the watchdog driver
- DTS aliases for testing with default watchdog driver test
Signed-off-by: Oane Kingma <o.kingma@interay.com>
Define a binding for a voltage divider circuit with one or more analog
input channels. Add devicetree nodes for several boards that have
battery voltage measurement support.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Adds device tree bindings for the focaltech ft5336 touch panel
controller, which will be used on several i.mx rt evk boards.
Moves address-cells and size-cells properties from the base kscan
bindings to the specific microchip,xec bindings since they are not
required for the ft5336.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Enable the shared IRQ for the UART line and enable the remaining tasks
that depends on a separated declaration of the TX/RX/Err/... IRQs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
ARM cores may have a per-core architected timer, which provides per-cpu
timers, attached to a GIC to deliver its per-processor interrupts via
PPIs. This is the most common case supported by QEMU in the virt
platform.
This patch introduces support for this timer abstracting the way the
timer registers are actually accessed. This is needed because different
architectures (for example ARMv7-R vs ARMv8-A) use different registers
and even the same architecture (ARMv8-A) can actually use different
timers (ELx physical timers vs ELx virtual timers).
So we introduce the common driver here but the actual SoC / architecture
/ board must provide the three helpers (arm_arch_timer_set_compare(),
arm_arch_timer_toggle(), arm_arch_timer_count()) using an header file
imported through the arch/cpu.h header file.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Lot of misdefined variables that went in undetected due to lack of CI on
this board. Fix them and test build with new SDK.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit adds the remaining gpio ports I, J and K to the device
tree and dts_fixup headers of the EFM32JG12B and EFM32PG12B SoCs.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
The blocks were moved into the soc block in samd5x.dtsi,
so we also have to move them for the the actual SoC definitions
that inherit from that.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
The Silicon Labs EFM32 Jade Gecko MCU includes:
* Cortex-M3 core at 40MHz
* up to 1024KB of flash and 256KB of RAM
* multiple low power peripherals
This is basically the same as the EFM32 Pearl Gecko, but with an ARM
Cortex-M3 core instead of a Cortex-M4F.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Extended nrf_uarte driver to support TX only UARTE instances.
When RX pin is not provided then RX is not started at all. This
allows to achieve low power with logging/console enabled.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The driver for STM32's independent watchdog already exists and is
compatible with the stm32l1 SoC. Enable the independent watchdog
for the stm32l1 series for use with this driver.
Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
Update the hal_nordic module revision, to switch to nrfx 2.1.0.
Because the list of peripherals for nRF5340 has changed as follows:
- SPIM2 has been renamed to SPIM4
- SPIM2-3, SPIS2-3, TWIM2-3, TWIS2-3, and UARTE2-3 have been added
a couple of related corrections needed to be applied in dts and Kconfig
files, plus the spi_nrfx_spim driver has been extended with the support
for SPIM4.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
DesignWare driver can manage different amount of irqs so let's make it
configurable via DTS.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This patch introduces the periph to/from memory dma transfer
define new values for dma cells on client side
Signed-off-by: Francois Ramu <francois.ramu@st.com>
