There's desire for a "log only" mode like the older adsplog script
had. Add a few other quality of life command line options too. And
catch the most obvious user errors to print a message instead of a
stack dump.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is based closely on the older cavsload.sh script, but updated to
keep up with interesting new twister behavior, with a cleaner
interface for CI integration that doesn't require editing the file,
somewhat better internal documentation, and with a more focused eye on
use as a twister tool specifically.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The existing scripting for these platforms has gotten a little stale.
The loader had bifurcated into a v15 and v25 variant, both of which
lived in the cavs15 board directory. Building off Shao Ming's
excellent (if somewhat surprisingly committed) rework to unify
unchanged parts of the scripts, let's finish the job.
This adds a "cavstool.py" script with the following advantages:
+ It's just one script for everything, with a single unified load
process that works reliably on both 1.5 and 1.8+ hardware.
+ It runs on all cAVS platforms (with a compatible kernel, those
requirements haven't changed)
+ It automatically emitts logging synchronously after loading,
eliminating the race between adsplog.py and cavs-fw.py where you
could see logging from a previous test run.
+ It automatically detects and unloads a linux kernel module managing
the same device (even if SOF has renamed the module again, heh).
+ Timings have been tuned up in general, it's about 2 seconds faster
to get to first log output now.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Re-organize the SoC family/series/model configuration data so that:
* Board definitions can distinguish between the single-core (XC7ZxxxS)
and dual-core (XC7Zxxx) ARM Cortex-A9 models. Further descriptions
of on-chip resources, in particular relating to the programmable logic
capabilities if support of this functionality is to be implemented,
can be added at a later time.
* Separate SoC initialization code exists for the two series, so that
the init code of the XC7Zxxx series can consider SMP while the init
code of the single-core XC7ZxxxS series doesn't have to.
* Device drivers which don't have to distinguish between the single-
and double-core series of the SoC family can use a common configuration
item whenever the pre-processor is used to enable Zynq-7000-specific
code.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
1. Setup VDD_SOC with the appropriate setting
depending on the SoC
2. Do not configure PLL_SYS and PLL_USB. These
are already configured by the ROM code using
the DCD
3. Fix setting for USDHC clock
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Fix for issue #41012 to allow compiler to treat
IRQn_Type to be more than 8-bit. This will ensure NVIC numbers
more than 127 (required for MEC172x device) will work
correctly with irq_enable() API
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The MIPS Malta is an ATX form factor evaluation board made by MIPS
Technologies. Malta board is the most popular platform for MIPS
full-system emulation.
See https://www.linux-mips.org/wiki/MIPS_Malta for details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Remy Luisant <remy@luisant.ca>
Add a module which is responsible for getting offset between RTCs
used for system clock on NET and APP cores. After getting an offset
between NET and APP clocks, it can be used for logging timestamping
on NET core to ensure that timestamping is in sync on both cores.
Synchronization is done using PPI, IPM task and events and RTC
capture feature.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
All options in Kconfig.soc are only for nrf53 series. Added file
wide guard instead of option specific options.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This sets CONFIG_KERNEL_VM_SIZE to define the size of virtual
memory region which can be used by the TLB driver. The size is
derived from the actual SOF code where they say the TLB register
space is of size 0x1000. There are 2048 TLB entries (for 2 bytes
per entry), which translates to 8MB of virtual memory space with
4KB pages.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Enables basic power management for the RT11xx series SOCs. The following
power saving measures are currently implemented:
- system reduces core voltage during sleep
- core clock can be gated in deep sleep
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
GPC driver is used for power management operations on RT series SoCs.
Enable inclusion of the driver into the build.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Arm Cortex-M3 DesignStart FPGA-Xilinx edition doesn't have to use XIP.
Our board doesn't need it. Make it optional by replacing "select" with
"imply".
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Change the stm32_power_init to be executed PRE_KERNEL_1
for all the devices with the low power mode (power.c)
When GPIO and UART are not yet up and running.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
gPTP module clock is enabled for rt11xx. gPTP is not working correctly
on the RT10xx or RT11xx series, but this module clock needs to be
enabled
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The SAM spi driver depends on GPIO driver to work. It seems that this
dependency chain it is not handled. This select GPIO driver when SPI
driver is enabled. It rework GPIO and SPI Kconfig to select driver by
devicetree and drop entries at Kconfig.defconfig.series file.
Fixes#41525
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This configures soc and flash size definition
using DTSI information instead of hardcoded
values.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Introduce Pin Function Controller for Renesas R-Car family.
This first implementation support to set a given pin as gpio
or peripheral (GPSR), to set a peripheral function to a
pin (IPSR), to set pull-up, pull-down (PUEN, PUD).
In addition this driver allows to set driving capabilies(DRVCTRL).
Pins are identified thanks to the per SoC binding for
pin definition which also contains pin alternate function
parameters.
Some pins can also have driving capabilities, some have bias
capabilities.
In order to find the correct bias and drive registers pfc_r8a77951.c
describes the different registers.
Each SoCs or package will need to define getters
for these registers: pfc_rcar_get_bias_regs() and
pfc_rcar_get_drive_regs().
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
BBRAM content should be cleared when boot from cutoff. Compare magic
number to decide whether to clear entire BBRAM.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The Q variant is the same as non-Q, except the Q has SMPS built-in.
This symbol addition is to have the correct
SOC definition ("STM32H7A3XXQ")
Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
The newer sys_winstream utility is considerably simpler and much
faster for the reader. Use that instead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
It's not uncommon to have Zephyr running in environments where it
shares a memory bus with a foreign/non-Zephyr system (both the older
Intel Quark and cAVS audio DSP systems share this property). In those
circumstances, it would be nice to have a utility that allows an
arbitrary-sized chunk of that memory to be used as a unidirectional
buffered byte stream without requiring complicated driver support.
sys_winstream is one such abstraction.
This code is lockless, it makes no synchronization demands of the OS
or hardware beyond memory ordering[1]. It implements a simple
file/socket-style read/write API. It produces small code and is high
performance (e.g. a read or write on Xtensa is about 60 cycles plus
one per byte copied). It's bidirectional, with no internal Zephyr
dependencies (allowing it to be easily ported to the foreign system).
And it's quite a bit simpler (especially for the reader) than the
older cAVS trace protocol it's designed to replace.
[1] Which means that right now it won't work reliably on arm64 until
we add a memory barrier framework to Zephyr! See notes in the code;
the locations for the barriers are present, but there's no utility to
call.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is no need to call soc_mp_init() if CONFIG_MP_NUM_CPUS
indicates only 1 CPU is being used. This also fixes an undefined
reference to soc_mp_init() since mp_cavs.c is not compiled
unless the build is targeting more than 1 CPU.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The reg_def.h was not self-contained: it uses DT API but doesn't
include <devicetree.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This is trick (mapping RAM twice so you can use alternate Region
Protection Option addresses to control cacheability) is something any
Xtensa hardware designer might productively choose to do. And as it
works really well, we should encourage that by making this a generic
architecture feature for Zephyr.
Now everything works by setting two kconfig values at the soc level
defining the cached and uncached regions. As long as these are
correct, you can then use the new arch_xtensa_un/cached_ptr() APIs to
convert between them and a ARCH_XTENSA_SET_RPO_TLB() macro that
provides much smaller initialization code (in C!) than the HAL
assembly macros. The conversion routines have been generalized to
support conversion between any two regions.
Note that full KERNEL_COHERENCE still requires support from the
platform linker script, that can't be made generic given the way
Zephyr does linkage.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Continue the previous work, moving the cAVS hardware dependencies into
a separate file, leaving soc_mp.c with only OS-generic details to
track.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Clean up soc_mp.c a bit. Put all cAVS register use in functions
dedicated to hardware details (e.g. "soc_start_core()"), leave the
Zephyr OS tracking (e.g. the CPU start record, the active cores array,
etc...) in generic code.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
So far board name was used as IDF target. This worked, as the only board
in tree that is based on 'esp32' SoC is actually 'esp32'.
Use CONFIG_SOC instead of CONFIG_BOARD, so that new boards based on
'esp32' SoC can be successfully introduced both downstream or upstream.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Many ARM SoCs included <devicetree.h> likely due to:
1. nvic.h not being self-contained
2. As a result of copy-paste
Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:
sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h
soc.h files that make a legitimate usage of the API have not been
changed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The header was not self-contained: it uses DT and utility macros but
<devicetree.h> and <sys/util_macro.h> were not included.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The source file uses boolean types internally, however, <stdbool.h> was
not included. It was likely included indirectly before via
<devicetree.h> -> <sys/util.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Almost none of the soc_*.h headers were self-contained. This patch adds
all necessary includes to improve the situation.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The default I2C channel 3 is used by alternate function of GPIO H1/H2
Krabby uses GPIO F2/F3 as I2C channel 3, so we need to add the
compatibility of the GPIO F2/F3.
TEST=test on it8xxx2_evb:
zmake configure -b zephyr/projects/it8xxx2_evb/
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Enable CONFIG_RISCV_PMP in qemu virt soc. Use this SoC as CI testing
platform of RISC-V PMP and Userspace.
Signed-off-by: Jim Shu <cwshu@andestech.com>
