Commit graph

5973 commits

Author SHA1 Message Date
Andy Ross
4f39b62d57 soc/intel_adsp: Polish cavstool
There's desire for a "log only" mode like the older adsplog script
had.  Add a few other quality of life command line options too.  And
catch the most obvious user errors to print a message instead of a
stack dump.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-21 14:48:36 -05:00
Andy Ross
e71b1a1148 soc/intel_adsp: Add twister integration script
This is based closely on the older cavsload.sh script, but updated to
keep up with interesting new twister behavior, with a cleaner
interface for CI integration that doesn't require editing the file,
somewhat better internal documentation, and with a more focused eye on
use as a twister tool specifically.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-21 14:48:36 -05:00
Andy Ross
f581d59821 soc/intel_adsp: Add unified "cavstool" loader/logger script
The existing scripting for these platforms has gotten a little stale.
The loader had bifurcated into a v15 and v25 variant, both of which
lived in the cavs15 board directory.  Building off Shao Ming's
excellent (if somewhat surprisingly committed) rework to unify
unchanged parts of the scripts, let's finish the job.

This adds a "cavstool.py" script with the following advantages:

+ It's just one script for everything, with a single unified load
  process that works reliably on both 1.5 and 1.8+ hardware.

+ It runs on all cAVS platforms (with a compatible kernel, those
  requirements haven't changed)

+ It automatically emitts logging synchronously after loading,
  eliminating the race between adsplog.py and cavs-fw.py where you
  could see logging from a previous test run.

+ It automatically detects and unloads a linux kernel module managing
  the same device (even if SOF has renamed the module again, heh).

+ Timings have been tuned up in general, it's about 2 seconds faster
  to get to first log output now.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-21 14:48:36 -05:00
Hake Huang
a59e994322 soc: add auido clock init per soc
RT11xx and RT10xx have different audio clock settings
so add them in soc.c

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-01-21 11:26:45 -06:00
Hake Huang
8ae222641d config: soc: add i2s support in rt1170 soc
add HAS_MCUX_I2S in soc config

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-01-21 11:26:45 -06:00
Immo Birnbaum
dffcb1d6f9 soc: arm: xilinx_zynq7000: Re-organize SoC data and init code
Re-organize the SoC family/series/model configuration data so that:
* Board definitions can distinguish between the single-core (XC7ZxxxS)
and dual-core (XC7Zxxx) ARM Cortex-A9 models. Further descriptions
of on-chip resources, in particular relating to the programmable logic
capabilities if support of this functionality is to be implemented,
can be added at a later time.
* Separate SoC initialization code exists for the two series, so that
the init code of the XC7Zxxx series can consider SMP while the init
code of the single-core XC7ZxxxS series doesn't have to.
* Device drivers which don't have to distinguish between the single-
and double-core series of the SoC family can use a common configuration
item whenever the pre-processor is used to enable Zynq-7000-specific
code.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
2022-01-21 11:34:09 -05:00
Mahesh Mahadevan
6f23f55e4b soc: mxrt10xx: Update the clock init code
1. Setup VDD_SOC with the appropriate setting
   depending on the SoC
2. Do not configure PLL_SYS and PLL_USB. These
   are already configured by the ROM code using
   the DCD
3. Fix setting for USDHC clock

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-21 08:36:09 -06:00
Jay Vasanth
4495f43dca soc arm: MEC172x soc.h - Include custom IRQn_Type
Fix for issue #41012 to allow compiler to treat
IRQn_Type to be more than 8-bit. This will ensure NVIC numbers
more than 127 (required for MEC172x device) will work
correctly with irq_enable() API

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-01-20 13:42:16 -05:00
Andy Ross
ca7024e1d6 arch/xtensa: Use ZSR assignments for the CPU pointer
Use the zsr.h assignments for the special register containing the
current CPU pointer.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-20 12:58:00 -05:00
Mahesh Mahadevan
a62ff8906d soc: Add support for MXRT595
Add support for MXRT595

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-19 13:35:09 -06:00
Benedikt Schmidt
03297084e5 soc: arm: stm32: activate LPTIM based upon PM
Activate LPTIM by default if PM is selected.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2022-01-19 14:15:29 -05:00
Antony Pavlov
76769a42d0 soc: mips: add Qemu Malta support
The MIPS Malta is an ATX form factor evaluation board made by MIPS
Technologies. Malta board is the most popular platform for MIPS
full-system emulation.

See https://www.linux-mips.org/wiki/MIPS_Malta for details.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Remy Luisant <remy@luisant.ca>
2022-01-19 13:48:21 -05:00
Krzysztof Chruscinski
ff6b5d979f soc: arm: nordic_nrf: nrf53: Add Synchronized RTC
Add a module which is responsible for getting offset between RTCs
used for system clock on NET and APP cores. After getting an offset
between NET and APP clocks, it can be used for logging timestamping
on NET core to ensure that timestamping is in sync on both cores.

Synchronization is done using PPI, IPM task and events and RTC
capture feature.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-01-19 17:46:28 +01:00
Krzysztof Chruscinski
1f445b65fb soc: arm: nordic_nrf: nrf53: Add nrf53 series guards to Kconfig.soc
All options in Kconfig.soc are only for nrf53 series. Added file
wide guard instead of option specific options.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-01-19 17:46:28 +01:00
Daniel Leung
206241acd6 soc: intel_adsp/cavs_v25: set CONFIG_KERNEL_VM_SIZE
This sets CONFIG_KERNEL_VM_SIZE to define the size of virtual
memory region which can be used by the TLB driver. The size is
derived from the actual SOF code where they say the TLB register
space is of size 0x1000. There are 2048 TLB entries (for 2 bytes
per entry), which translates to 8MB of virtual memory space with
4KB pages.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-18 19:18:30 -05:00
Daniel DeGrasse
19bb8e2ec8 soc: rt11xx: Enable power management for RT11xx series SOCs
Enables basic power management for the RT11xx series SOCs. The following
power saving measures are currently implemented:

- system reduces core voltage during sleep
- core clock can be gated in deep sleep

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-18 14:09:45 -05:00
Daniel DeGrasse
f5ebc30087 soc: imx_rt: Enable IMX.RT General Power Controller Driver
GPC driver is used for power management operations on RT series SoCs.
Enable inclusion of the driver into the build.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-18 14:09:45 -05:00
Yasushi SHOJI
611230f80e soc/arm/designstart: Make XIP optional
Arm Cortex-M3 DesignStart FPGA-Xilinx edition doesn't have to use XIP.
Our board doesn't need it.  Make it optional by replacing "select" with
"imply".

Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
2022-01-18 13:21:50 -05:00
Francois Ramu
1b8d2d3dad soc: arm: stm32 mcus should execute stm32_power_init in PRE_KERNEL_1
Change the stm32_power_init to be executed PRE_KERNEL_1
for all the devices with the low power mode (power.c)
When GPIO and UART are not yet up and running.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-01-18 13:17:39 -05:00
Daniel DeGrasse
0fddb3e458 soc: rt11xx: Enabled GPTP module clock
gPTP module clock is enabled for rt11xx. gPTP is not working correctly
on the RT10xx or RT11xx series, but this module clock needs to be
enabled

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-18 12:13:24 -05:00
Daniel DeGrasse
b3a148b22f soc: rt11xx: Enable ethernet clocks
Enable clocks for ethernet module.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-01-18 12:13:24 -05:00
Gerson Fernando Budke
58936e7639 soc: arm: atmel_sam: samv71: Fix SPI build dependency
The SAM spi driver depends on GPIO driver to work. It seems that this
dependency chain it is not handled. This select GPIO driver when SPI
driver is enabled. It rework GPIO and SPI Kconfig to select driver by
devicetree and drop entries at Kconfig.defconfig.series file.

Fixes #41525

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-01-18 12:12:52 -05:00
Sylvio Alves
2b427fd935 soc: esp32: add flash dts values into cmake config
This configures soc and flash size definition
using DTSI information instead of hardcoded
values.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-01-18 10:38:34 -05:00
Julien Massot
feb6e2504e drivers: pinctrl: add Renesas RCar PFC driver
Introduce Pin Function Controller for Renesas R-Car family.
This first implementation support to set a given pin as gpio
or peripheral (GPSR), to set a peripheral function to a
pin (IPSR), to set pull-up, pull-down (PUEN, PUD).
In addition this driver allows to set driving capabilies(DRVCTRL).

Pins are identified thanks to the per SoC binding for
pin definition which also contains pin alternate function
parameters.

Some pins can also have driving capabilities, some have bias
capabilities.
In order to find the correct bias and drive registers pfc_r8a77951.c
describes the different registers.
Each SoCs or package will need to define getters
for these registers: pfc_rcar_get_bias_regs() and
pfc_rcar_get_drive_regs().

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2022-01-17 21:00:58 +01:00
Tim Lin
95ba8e3fe4 ITE: drivers/bbram: add magic number to compare in initial
BBRAM content should be cleared when boot from cutoff. Compare magic
number to decide whether to clear entire BBRAM.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-01-17 11:52:13 -05:00
Manojkumar Subramaniam
bd9415e6bf soc: arm: stm32h7: kconfig workaround to handle SoC H7A3XX-Q P/N
Set the correct soc string so that the correct CMSIS file
is being utilised.

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Manojkumar Subramaniam
881407be6e soc: arm: stm32h7: add stm32h7a3xxq
The Q variant is the same as non-Q, except the Q has SMPS built-in.
This symbol addition is to have the correct
SOC definition ("STM32H7A3XXQ")

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Manojkumar Subramaniam
a268d8b07e soc: arm: stm32h7: add stm32h7a3xx support
Basic kconfig config.

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Andy Ross
8590f67f69 soc/intel_adsp: Replace trace_out code with a sys_winstream
The newer sys_winstream utility is considerably simpler and much
faster for the reader.  Use that instead.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-13 14:01:23 -05:00
Andy Ross
528bef2d22 lib/os: Add sys_winstream lockless shared memory byte stream IPC
It's not uncommon to have Zephyr running in environments where it
shares a memory bus with a foreign/non-Zephyr system (both the older
Intel Quark and cAVS audio DSP systems share this property).  In those
circumstances, it would be nice to have a utility that allows an
arbitrary-sized chunk of that memory to be used as a unidirectional
buffered byte stream without requiring complicated driver support.
sys_winstream is one such abstraction.

This code is lockless, it makes no synchronization demands of the OS
or hardware beyond memory ordering[1].  It implements a simple
file/socket-style read/write API.  It produces small code and is high
performance (e.g. a read or write on Xtensa is about 60 cycles plus
one per byte copied).  It's bidirectional, with no internal Zephyr
dependencies (allowing it to be easily ported to the foreign system).
And it's quite a bit simpler (especially for the reader) than the
older cAVS trace protocol it's designed to replace.

[1] Which means that right now it won't work reliably on arm64 until
we add a memory barrier framework to Zephyr!  See notes in the code;
the locations for the barriers are present, but there's no utility to
call.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-13 14:01:23 -05:00
Tom Burdick
b246de1ba2 intel_adsp: Remove unused soc_idc_init reference
Unused as it was renamed to soc_mp_init, this is a stray left over.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-01-13 13:57:39 -05:00
Daniel Leung
aa20e081d2 arm: remove @return doc for void functions
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-12 16:02:16 -05:00
Daniel Leung
61d0c3cfe7 riscv: remove @return doc for void functions
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-12 16:02:16 -05:00
Christoffer Bask
2091c3752d pwm: Added MCUX_PWM support for MIMXRT1021
It has been tested and working on a custom MIMXRT1021-pcb.

Signed-off-by: Christoffer Bask <christoffer@softube.com>
2022-01-12 15:46:01 +01:00
Daniel Leung
32c492cc0c soc: xtensa/intel_adsp: don't call soc_mp_init if MP_NUM_CPUS==1
There is no need to call soc_mp_init() if CONFIG_MP_NUM_CPUS
indicates only 1 CPU is being used. This also fixes an undefined
reference to soc_mp_init() since mp_cavs.c is not compiled
unless the build is targeting more than 1 CPU.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-11 19:57:01 -05:00
Gerard Marull-Paretas
864888f2ce soc: arm: nuvoton_npcx: add missing include
The reg_def.h was not self-contained: it uses DT API but doesn't
include <devicetree.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 10:03:54 -05:00
Andy Ross
97ada8bc04 arch/xtensa: Promote adsp RPO/cache utilities to an arch API
This is trick (mapping RAM twice so you can use alternate Region
Protection Option addresses to control cacheability) is something any
Xtensa hardware designer might productively choose to do.  And as it
works really well, we should encourage that by making this a generic
architecture feature for Zephyr.

Now everything works by setting two kconfig values at the soc level
defining the cached and uncached regions.  As long as these are
correct, you can then use the new arch_xtensa_un/cached_ptr() APIs to
convert between them and a ARCH_XTENSA_SET_RPO_TLB() macro that
provides much smaller initialization code (in C!) than the HAL
assembly macros.  The conversion routines have been generalized to
support conversion between any two regions.

Note that full KERNEL_COHERENCE still requires support from the
platform linker script, that can't be made generic given the way
Zephyr does linkage.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-11 11:53:53 +01:00
Andy Ross
6aa3d0c72f soc/intel_adsp: Split out mp_cavs.c from soc_mp.c
Continue the previous work, moving the cAVS hardware dependencies into
a separate file, leaving soc_mp.c with only OS-generic details to
track.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-11 11:53:53 +01:00
Andy Ross
9e524d8305 soc/intel_adsp: Refactor mp code to separate hardware from OS details
Clean up soc_mp.c a bit.  Put all cAVS register use in functions
dedicated to hardware details (e.g. "soc_start_core()"), leave the
Zephyr OS tracking (e.g. the CPU start record, the active cores array,
etc...) in generic code.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-01-11 11:53:53 +01:00
Marcin Niestroj
31425c58d1 soc: esp32: use SoC name as IDF target instead of board name
So far board name was used as IDF target. This worked, as the only board
in tree that is based on 'esp32' SoC is actually 'esp32'.

Use CONFIG_SOC instead of CONFIG_BOARD, so that new boards based on
'esp32' SoC can be successfully introduced both downstream or upstream.

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-01-11 11:53:09 +01:00
Tim Lin
263fd9d1d1 ITE: cleanup: it8xxx2: drivers/intc rename the function
The function should be renamed ite_intc_irq_polarity_set.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-01-11 11:52:35 +01:00
Gerard Marull-Paretas
e5e73a70e9 soc: remove unnecessary inclusions of devicetree.h
Many ARM SoCs included <devicetree.h> likely due to:

1. nvic.h not being self-contained
2. As a result of copy-paste

Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:

sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h

soc.h files that make a legitimate usage of the API have not been
changed.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
31ad52336b soc: riscv: telink_b91: fix required headers
The linker script is using the DT API, which was previously included via
<soc.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
130b06a0fd soc: riscv: riscv-privilege: andes_v5: make smu.h self contained
The header was not self-contained: it uses DT and utility macros but
<devicetree.h> and <sys/util_macro.h> were not included.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
a08e87e078 soc: arm: silabs_exx32: make soc_pinmap.h self contained
The soc_pinmap.h uses the DT API, so these headers needs to include
<devicetree.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
7a5ee28755 soc: arm: atmel_sam0: common: soc_port: add missing include
The source file uses boolean types internally, however, <stdbool.h> was
not included. It was likely included indirectly before via
<devicetree.h> -> <sys/util.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
095a21e2cf soc: arm: nuvoton_npcx: make soc_*.h headers self-contained
Almost none of the soc_*.h headers were self-contained. This patch adds
all necessary includes to improve the situation.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Tim Lin
45b6aa4c3b ITE: drivers/i2c: add the compatibility of GPIO F2/F3 for i2c3
The default I2C channel 3 is used by alternate function of GPIO H1/H2
Krabby uses GPIO F2/F3 as I2C channel 3, so we need to add the
compatibility of the GPIO F2/F3.

TEST=test on it8xxx2_evb:
zmake configure -b zephyr/projects/it8xxx2_evb/

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-01-11 11:49:16 +01:00
Jim Shu
74faa18902 soc: riscv: virt: enable RISC-V PMP support
Enable CONFIG_RISCV_PMP in qemu virt soc. Use this SoC as CI testing
platform of RISC-V PMP and Userspace.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00
Henrik Brix Andersen
25433f1414 soc: arm: nxp: lpc55xxx: add MCAN support
Add support for the NXP LPC MCAN CAN-FD controller.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-01-10 12:00:20 +01:00