Update pinctrl driver which used for Renesas RA series with
PFS secure register
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Add support of sys_poweroff API on m2l31x series.
It could support SPD0~2 standby or DPD0~1 deep power down mode.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Enable the driver using the standard mechanism used everywhere else in
the tree. It is possible here as it is a singleton, so there's no
dependency on nrfx instantiation magic.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add new RT118x device, due to structure is different from rt11xx series.
Boot header also differ from rt10xx and rt11xx, so add support for boot
container.
define new container name and new container tag
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Let's link from the deprecated instructions.
To increase visibility and hopefully avoid developers forgetting to
do so.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Now that the dts/bindings filter has been removed from
Devicetree Binding area, this area serves no real purpose.
Move the include/dt-bindings files to their respective areas.
Fix some of the orphaned dts/bindings paths.
Add regex filter for any binding with "zephyr" in the name to be
in the devicetree area.
Fix the imx_spc.h file being in it's own pm/ folder instead of
power/ like the other power related headers.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
XTENSA_CCOUNT_HZ is no longer common to ACE soc series
This will fix Hz value for ACE30 platform
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
The Host Interface Type in the DEVCNT register sets the HIF type
(either eSPI or LPC).
Currently, it is configured in the host-interface-related drivers like
eSPI or SHI. However, some I/O pads sourced from VHIF in the other
modules such as GPIO and I3C also rely on this field. It might be
problematic when using those I/Os without enabling eSPI or SHI drivers.
This commit moves the setting from the specific drivers to the global
system initialization function scfg_init().
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Initial commit to suppor RA8D1 SoC
This is deveop base on RA8M1 so it will have similar stucture and
feature
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Some new Nordic nRF SoCs are based on a common platform, named
'Haltium'. Introduce a selectable Kconfig option available for series to
flag they are part of such common platform. This will allow to easily
enable common code shared across all Haltium based products.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
RA4M1-specific options were being applied system-wide because
conditions were not set properly.
This change fixes this problem.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Instead of forcing users to provide this setting, allow to describe
which signals require CLOCKPIN enablement at device nodes. This is later
captured by the pinctrl macros and applied in the pinctrl driver. Note
that name has been adjusted to nordic,clockpin-enable to avoid confusion
with clock related settings.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
custom arch_cpu_idle and arch_cpu_atomic_idle implementation was done
differently on different architectures. riscv implemented those as weak
symbols, xtensa used a kconfig and all other architectures did not
really care, but this was a global kconfig that should apply to all
architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add config file to host WiFi specific settings.
Introduce CONFIG_ESP_WIFI_MAX_THREAD_PRIO to be used
as a cap for the LL driver runtime.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The power_down() function will lock dcache for the hpsram_mask
array. On some platforms, the dcache lock will fail if the array
is on cache line that can be used for window register context
saves.
Work around this by aligning and padding the hpsram_mask to cacheline
size.
Link: https://github.com/thesofproject/sof/issues/9268
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
After flashed EC image, we needed to manually press the reset button
on it8xxx2_evb. Now, without pressing the button, we can disable
debug mode and trigger a watchdog hard reset for running tests.
After flash EC, running below tests can pass (without pressing the button):
west build -p always -b it8xxx2_evb tests/drivers/watchdog/wdt_basic_api
west build -p always -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p always -b it8xxx2_evb tests/kernel/fatal/exception
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
For stm32 platforms where the sysclock is less or equal to
32MHz, the Ticks per second is reduced to 8000 (instead of
10000).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Many xtensa target jump from soc code directly into cstart and depend on
architecture code being initialized in arch_kernel_init(). Instead of
jumping to cstart, jump to newly introduced prep_c similar to all other
architectures, where common platfotm initialization will happen.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This update is to support clock API for RA8
Move the clock initialize function into clock driver
Peripheral clock now has 2 more property in clock cell for enable
and disable clock to peripheral module
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
This change adds the device tree property for specifying oe-override
(output-enable override behavior), as well as defines for possible values
of the property.
RP2040 GPIOs can be configured to automatically invert the output-enable
signal from the selected peripheral function. This is useful for tasks like
writing efficient PIO code, such as in the i2c example in the rp2040
datasheet.
Signed-off-by: Yiding Jia <yiding.jia@gmail.com>
