The cache operations must be quick, optimized and possibly inlined. The
current API is clunky, functions are not inlined and passing parameters
around that are basically always known at compile time.
In this patch we rework the cache functions to allow us to get rid of
useless parameters and make inlining easier.
In particular this changeset is doing three things:
1. `CONFIG_HAS_ARCH_CACHE` is now `CONFIG_ARCH_CACHE` and
`CONFIG_HAS_EXTERNAL_CACHE` is now `CONFIG_EXTERNAL_CACHE`
2. The cache API has been reworked.
3. Comments are added.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
When MCUBoot is enabled, IRAM region needs to be set
to a smaller value to avoid overlapping. This shall be re-worked
when MCUboot build for ESP32 is performed in Zephyr environment.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a hidden Kconfig option to select the index of the target RTU
(Real-Time Unit) subsystem. This index can be used by peripheral
drivers, for example, to know the peripheral instance index since the
HAL is index-based.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Microchip XEC GPIO pins support inverting the output of
alternate pin functions. This feature may be useful for
those peripherals that do not implement output inversion
in the peripheral. GPIO control register pad input and
parallel input register values are not affected by the
function output invert feature. GPIO interrupt detection
of an output is inverted if the invert polarity is enabled.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Added a missing SDK function POWER_PowerInit
to the clock_init function of the soc in lpc55S36.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
- Put L2C init level in pre_kernel_2 to wait for syscon driver
- Check if SMU exists when preprocessing
Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
Control shared interrupts enabling/disabling via IDU.
With that we can easily enable and disable them for all cores
in one place.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
EXTRA_IMGTOOL_ARGS is used to set additional options by the user.
Any user change will overwrite this option, which
is unintuitive.
Also option ROM_START_OFFSET will be overwritten which is also unintuitive.
Replace hardcoded config option MCUBOOT_EXTRA_IMGTOOL_ARGS
with proper config ROM_START_OFFSET.
Signed-off-by: Maciej Zagrabski <mzi@trackunit.com>
Be consistency with zephyr.strip
This will help with reproducibility issues like the one in
https://github.com/thesofproject/sof-bin/pull/106
Use the `strip_command` introduced by commit c060b075a6 ("cmake:
toolchain: bintools abstraction")
boot.mod is already deterministic because it has no debug symbols; no
need to strip it.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
SOF compilation is sensitive to compilation warnings
Some simple and neutral changes to avoid them
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
IMR save and restore context is a flow implemented for ACE
move boot specific procedures to ace subdir
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
In ACE architecture, only core 0 should receive IPC interrupts from host.
Unmasking secodnary core IPC interrupts was causing race condition in
ipc irq handler after enabling secondary core.
Signed-off-by: Przemyslaw Blaszkowski <przemyslaw.blaszkowski@intel.com>
The linker script for intel_adsp ace was missing the
snippets-sections.ld include, causing it to ignore any custom section
defined in with cmake zephyr_linker_sources().
Adding it in the same location as it's done in xtensa-cavs-linker.ld.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
HAL for NXP S32 is updated to a newer version, hence some headers and
macro definitions must be updated accordingly.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Update rt5xx base address calculation to use the zephyr,chosen flash node
to determine flash base address. Note that due to the external flash
controller, the flexSPI base address must be used when the flash device
is on the flexSPI bus.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update rt6xx base address calculation to use the zephyr,chosen flash node
to determine flash base address. Note that due to the external flash
controller, the flexSPI base address must be used when the flash device
is on the flexSPI bus.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Context save is saving whole memory to persistent
memory area, than turning off memory and CPU
Context restore is a modified boot flow, where
the previously saved context is restored
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Updated the clock_init function to the latest sdk
and added a safe initialization for the flash setup
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Added a selecion on rt6xx that allows the loading of
the safe flash clock initialization to be inside SRAM
if the user code is being executed from flash.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Call CMSIS SystemInit at early platform boot, to ensure that registers
are configured correctly on RT10xx series.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch updates ipc response procedure in power down function. New
flow is only limited to the writs into two registers. We need to clear
the IPCxIDD register in case if its contains any leftovers from a
previous responce. And then write a response to the IPCxIDR.
To prepare response we need to copy incoming request and then mark it as
replay. New message with IPC Busy bit set is then send to host.
The reason for this is a change in the behavior of the IPC driver
compared to how it worked when this function was originaly implemented.
The biggest difference are enabled interrupts in register IPCxCTL.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Zephyr maps start/end of rodata section with variables
using __rodata_region namespace. The exception was Xtensa.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add XIP support with MWDT toolchain. To have it proper tested
add separate nsim platforms for XIP (flash + sram) and
non-XIP (sram) memory organization in addition to existing
nsim_hs platfor with CCMs (ICCM + DCCM) memory organization.
This PR also enables MPU for all nsim hs3x based platforms
(like we previously enabled it for qemu_arc_hs) to have proper
memory regions permissions.
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
Since DTS doesn't contain the BDF anymore (it's looked up at runtime),
hardcode the BDF value for the use of early serial.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Update lpc54114 support to use LMA address offset instead of linking
secondary core image into primary core memory. This will allow support
with sysbuild to be enabled. Additionally, use partitions to select where
the secondary core image will be located in flash
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use LMA adjustment building dual core image with LPC55s69. The load
address adjustment allows the second core image to be flashed onto the chip
by the debugger, into the secure region of the LPC flash.
Additionally, remove the build dependency that was enforced by the SOC.
This requirement to build the secondary core image first can be enforced
by the project itself, instead of the core.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Move setting soc_num_cpus into its own SYS_INIT function such
that we can ensure it happens as one of the first things. We
need soc_num_cpus set before soc_mp_init is called but also before
interrupt controller init functions might be called.
Also, by having it in its own function, it ensures that
soc_num_cpus gets set regardless of how CONFIG_MP_MAX_NUM_CPUS
is set. Since if CONFIG_MP_MAX_NUM_CPUS=1, we do not call
soc_mp_init().
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
\MTL SOF is not compiling when
8d0eb6ce10
(devicetree: remove deprecated DT_CHOSEN_*_LABEL macros)
is applied
Fix - zephyr/toolchain used to be included by
devicetree/zephyr.h. The file has been removed by 8d0eb6ce10
Include is needed for ALWAYS_INLINE macro
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Move regs configuration from previous pinmux.c to soc layer.
This involves the debug interface, configuring the GPIO bank power
and the test clock out pin.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Only include fsl_flexspi_nor_boot when a boot header is present,
as this is the only case where the boot header data will be required.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use spisc_it8xxx2_regs instead of IT83XX_SPI_*** registers declaration
to fix in cros_shi_it8xxx2.c
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The icmsg backend for ipc_service has a limitation of supporting only
on endpoint. This limitation is acceptable for many IPC instances.
However, some require to use multiple endpoints sharing a single
instance. To preserve the simple and the most efficient single-instance
backend, a separated backend is introduced implementing a wrapper
around icmsg core which adds multiple endpoints support.
There are two multi-endpoint ipc_service icmsg backends: one in the
initiator role, and the other one in the follower role. In a IPC
configuration one end of communication must be in the follower role
while the other one is in the initiator. The initiator initiates
an endpoint discovery handshake to establish enpoint identifiers for
requested endpoint names. The follower responds to requests sent by
the initiator.
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
The `mps2_an521_remote` and `mps2_an521_ns` targets have the same
memory layout for code and ram, meaning that you can't use TF-M
(`mps2_an521_ns`) and the second core (`mps2_an521_remote`) at the
same time.
This commit updates the memory map of the `_ns` build targets as
follows:
- Reduces the code memory region from 1 MB to 512 KB, maintaining the
existing base memory address of `0x0010 0000`
- Maintains the existing 512 KB ram memory at `0x2810 0000`
It updates the `_remote` target as follows:
- Reserves 468 KB code memory at address `0x0038 B000`
- Reserves 512 KB ram memory at address `0x2818 0000`
This ensures that the code region for the `_remote` target doesn't
overlap with the code region used by the single flash image layout
defined upstream in TF-M, which the `_ns` target is based upon.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
