Add Nuvoton numaker series clock controller support, including:
1. Do system clock initialization in z_arm_platform_init().
2. Support peripheral clock control API equivalent to BSP
CLK_EnableModuleClock()/CLK_SetModuleClock().
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Added a new function to check whether a clock source is supported by a
platform and to retrieve its frequency.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The word cpu was added to the names of functions, structs, types
and definitions to disambiguate the names and make room in the namespace
for soc clock control functions.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Add simple mechanism to load the image from IMR memory. Basically we are
only setting a flag in power off for the next boot to jump to existing
image in IMR.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
Add a new pinctrl driver for TI CC32XX SoC. The driver has not been
tested, just implemented following datasheet specs and checked that it
compiles. Consider this as a best-effort driver to remove custom pinmux
code in board files.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Disable RT boot header for CM4 core. This will ensure the boot header is
not present when building an application targeting RAM on the CM4.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Zephyr currently only supports CLINT direct mode and CLINT vectored
mode. Add support for CLIC vectored mode as well.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Before adding support for the CLIC vectored mode, rename
CONFIG_RISCV_MTVEC_VECTORED_MODE to CONFIG_RISCV_VECTORED_MODE to be
more generic and eventually include also the CLIC vectored mode.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add support for INTEL FPGA Nios V/g RISC-V based Processors.
Also amended SOC_NIOSV_M to use ATOMIC_OPERATIONS_BUILTIN.
Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
Amount of memory banks should vary depending on platform, otherwise
power down sequence might result in ipc timeout as the memory used by
the ipc itself is shutdown.
Lift the needed defines from sram.c to adsp_memory.h and shorten the
names to avoid collision with sof code. No functional change to sram.c.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
It doesn't make sense to select this option at SoC level. This feature
is meant for subsystems/modules that need device handles to be
modifiable at runtime.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The field offset is incorrect, L1EXP is at bit 24 and L1ETP at bit 25.
Fixes: cc6e9c094a ("soc/intel_adsp: Low level HDA driver and tests")
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
The Nordic board are selecting CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT by
default and rely on some HAL code to implement a cycle accurate busy
delay loop.
This is in general fine for real hardware but when QEMU and emulation is
taken into account, a cycle accurate busy wait implementation based on
delay in executing machine code can be misleading.
Let's take for example qemu_cortex_m0 (that is based on the nRF51
chipset) and this code:
uint32_t before, after;
while (1) {
before = k_cycle_get_32();
k_busy_wait(1000 * 1000);
after = k_cycle_get_32();
printk("diff cycles: %d\n", after - before);
}
With CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 this diff cycles should
be always around 1000000, in reality when executed with:
qemu-system-arm -cpu cortex-m0 -machine microbit -nographic
-kernel build/zephyr/zephyr.elf
This results in something like this:
diff cycles: 22285
diff cycles: 24339
diff cycles: 21483
diff cycles: 21063
diff cycles: 21116
diff cycles: 19633
This is possibly due to the fact that the cycle accurate delay busy loop
is too fast in emulation.
When dealing with QEMU let's use the reliable busy loop implementation
based on k_cycle_get_32() instead.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
As a result of the 11a2107d991b("riscv: timer: driver revamp") commit,
gd32vf103 no longer works properly.
In the
c9c04e491e0f("soc: riscv: Add initial support for GigaDevice GD32V SoC")
that is the first commit of implementation of this SoC,
set the CPU frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
and riscv_machine_timer divide the clock with the value of
CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER.
The CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC should set the timer's clock,
so I fixed to set the config as 27MHz in this PR. Also, remove the
unnecessary CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER setting.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Updated the flash segment alignment on S3,
so that mapping corresponds with the linkage.
Fixed hard-coded flash size for ESP32.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
For Intel cavs2.5, access from LPGPDMAC to Audio Link Hub
RX/TX registers needs to be explicitly enabled before use.
The logic follow hardware initialization done in
SOF project sof/src/platform/intel/cavs/platform.c
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
1. Add support for the USB Full Speed controller
2. Add a Kconfig to specify if a dedicated USB
RAM is available in the SoC.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add FLEXSPI1 and FLEXSPI2 memory sections for RT5xx SOC. These sections
can be used by the user's application as part of a custom linker script,
if the application needs to relocate a buffer to external SRAM connected
to FLEXSPI1 or FLEXSPI2
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds watchdog reset as a reset source at SoC init. This is achieved by:
1. Writing 0x2 to the RESET_EN bitfield register to indicate watchdog
reset is enabled.
2. Writing 0x1 to the CFG_CDC_SYNC register to commit the change.
3. Polling the CFG_CDC_SYNC register until reading 0 to confirm the
change has been processed.
This patch is part of the OpenTitan watchdog (AON Timer) support patch
series. It is needed to ensure that the watchdog reset functionality
is enabled. Note that the timer itself is not enabled here, only the
reset function.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
1. Fixes the number of interrupts in OpenTitan by default. This should
be 32 + 185 = 217 IRQs, as there are 185 configurable registers,
including interrupt 0.
2. Adds 2ND_LVL_INTR_00_OFFSET Kconfig, which is needed to generate a
PLIC interrupt on IRQ 11.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
The SoCs/Boards using those headers were dropped, so remove those
remaining headers that were forgotten.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commits selects the `CONFIG_SOC_GECKO_SE` option for the BG27 SoC
series. This is required for BLE support, as it enables the inclusion of
the `sl_protocol_crypto` component from SiLabs HAL.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Internal bootloader will only run application image if valid product
header is present on flash. This means product header is required for
application that are not linked to code partition. Other applications
that are linked to code partition are meant to be run by MCUboot and
should not touch product header, with the exception of MCUboot itself
which is also run by internal bootloader so requires product header.
Default flash load offset for applications not linked to code partition
is set to 0x2400 as this is where internal bootloader looks for an
application image to run based on product header written by flasher.
Flash load offset for MCUboot is set from boot partition.
Valid product header is added by ezFlashCLI when using "flash_image"
command.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
