Add call to SystemInit for all NXP Kinetis SOCs and remove any
redundant code from initialization flow. This allows watchdog
initialization to be removed from all Kinetis SOCs as it is handled
by SystemInit.
Since Kinetis watchdog is enabled by default at boot, allow watchdog
setup to by bypassed with CONFIG_WDOG_ENABLE_AT_BOOT. This
setting requires the user to provide a watchdog configuration hook
using z_arm_watchdog_init, but will allow the watchdog to remain
enabled.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
update the endpint in dts to 6 to alignd with RM
enable usb-device for LPC55S28
all USB supported tests/samples PASS
samples:
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T samples/subsys/usb/
...
INFO - 7 of 25 test configurations passed (100.00%),\
0 failed, 18 skipped with 0 warnings in 73.49 seconds
...
tests
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T tests/subsys/usb/
...
INFO - 3 of 4 test configurations passed (100.00%),\
0 failed, 1 skipped with 0 warnings in 36.39 seconds
...
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Allow the the SoC to enter deep sleep when CONFIG_PM_DEVICE
is enabled. This will allow to selectively add low power
support for certain drivers like UART and ADC.
The previous checking of ifndef CONFIG_PM_DEVICE was
incorrect. The MEC172x requires the soc power file to perform
some operations when CONFIG_PM_DEVICE is enabled to allow
the hardware to shut down the PLL.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The watchdog is controlled by ll-scheduler and should not be resumed when
a core is bringing up. Watchdog pause control code was removed.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Added intel_adsp_ipc_send_message_emergency function that allows to send an
ipc message notifying about emergency event, such as watchdog timeout.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The non-maskable interrupt have no corresponding bit in INTERRUPT and
INTENABLE registers so its occurrence cannot be confirmed. Removed the code
that checked if the interrupt flag is set.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
rodata section for xtensa overrides the .ctors section
containing the constructor info and the _ZEPHYR_CTOR_LIST_.
Removes the ctor related linker script lines from the rodata
section of the ace linker script to ensure that the .ctors is
properly generated and placed when using the xcc-clang compiler.
Fixes#54730
Signed-off-by: Aastha Grover <aastha.grover@intel.com>
PR #30403 implemented nocache regions for ethernet DMA buffers in sram3 to
fix issue #29915. Unfortunately, some STM32H7 variants do not have any
sram3 so they still suffer from #29915.
All H7 variants have sram2 though, so use that for targets without sram3.
Signed-off-by: Björn Stenberg <bjorn@haxx.se>
When running the blinky example on STM32H747, with the BOOT_CM4 bit set
to 0, the M4 core goes into panic.
Increasing the value of the hardware semaphore retry prevents this.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This patch allows successive reflashing operation on stm32f3
boards by Enabling the Debug Module during SLEEP mode.
This will especially makes reflahing and debugging possible
with pyocd runner on west commands.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Temporary re-enabling interrupts before going to waiti. Right now
secondary cores don't have proper context restore flow and after leaving
D3 state core will return here and stuck. This is temporary workaround.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Adding additional core power-off before core is properly power-up after
power domains is wake up from power gaiting state.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is moving common power configuration code outside of the
section only for the primary core. This should be enabled for all cores
and it was put there probably by mistake.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
When building with picolibc and gcc, the loops to do zeroing/copying
get replaced by gcc with calls to memset/memcpy. This fails this early in
the boot process and results in an illegal instruction exception.
Marking the variables being manipulated in the calls as volatile prevents
the compiler from optimizing the loops (replacing them with memset/memcpy).
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
On some STM32 MCUs SEGGER RTT is only working with realtime updates
when DMA is clocked. The STM32U5 series uses a new DMA controller
module called GPDMA.
Refs: #34324Fixes: #54316
Signed-off-by: Almin Iriskic <almin.iriskic@student.tugraz.at>
Add SOC_CC1352P and SOC_CC2652P chip types to SoC's Kconfig
(with integrated high power amplifiers).
Also requires modifications to HAL TI's family conditions.
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
New KConfig option to set `CCFG_FORCE_VDDR_HH` inside CC13xx/CC26xx
customer configuration file, making it it possible to use 14dBm
TX power (instead of the default 13 dBm limitation).
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
Disables allowing the python argparse library from automatically
shortening command line arguments, this prevents issues whereby
a new command is added and code that wrongly uses the shortened
command of an existing argument which is the same as the new
command being added will silently change script behaviour.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Explicitly define function pointer as (void*)() and not (void*).
In C this cast is done implicitly, but C++ does not allow it.
Also, the const is moved to the correct location. Now it's a constant
pointer to a function(void) that returns void, instead of a pointer
to a function(void) returning (const void).
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
The nRF HW models have been updated to correspond to a 52833 instead
of a 52832. Let's follow them.
The motivation for the change is to enable proper BIS encryption support
(for BT LE Audio ISO).
Changes:
* Point in manifest to latest HW models
* SOC_COMPATIBLE_NRF52832 has been removed, and SOC_COMPATIBLE_NRF52833
added in its place (with no uses at this point)
* Where SOC_COMPATIBLE_NRF52832 was used to set encryption like for a 52832
(to avoid using the MAXPACKETLENGHT), we set the condition to just
SOC_NRF52832.
Note: The MAXPACKETLENGHT register exists in the new simulated nrf52833,
thought it does nothing.
* In the BLE ctrl LLL radio HAL, all macros are renamed accordingly
(timings are NOT changed).
* Board dts definition now refers to the 52833 soc definition. New 52833
features set as not supported by now.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add three xbar nodes and four qdec nodes in the rt10xx devicetree include.
Add xbara to rt1052 in Kconfig.soc
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Introduce DT nodes for NETC complex and enable its usage for
s32z270dc2_r52 boards. Using PSI0 as default networking interface and
Switch Port0 as it's the only port available on this board.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
The parameter doc string for hda was incorrect as the parameters
had been updated to take the IP base address, block size, and stream id
instead. Updates all doc string comments to account for the change.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The DMA API contract specifies that start/stop may be called multiple
times. Prior to adding power management this was perfectly fine as it was.
In adding power management, there are additional side effects that can
cause issues. Instead check the state of the channel prior to start/stop
and do nothing if already in the desired state.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Intel DSP Communication Widget is a device for generic sideband
message transmit/receive between IPs in a SOC.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The interrupt is used to wake up EC from low power mode.
So EC does not defer eSPI bus while transaction is accepted.
Fixes EC host commands slow issue.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit modifies the defconfig for efr32bg22 SoC so that Gecko SPI
selection depends on the DT_HAS_*_ENABLED define.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Update usage of zephyr_code_relocate to follow new API. The old method
of relocating a file was the following directive:
zephyr_code_relocate(file location)
The new API for zephyr_code_relocate uses the following directive:
zephyr_code_relocate(FILES file LOCATION location)
update in tree usage to follow this model. Also, update the NXP HAL SHA,
as NXP's HAL uses this macro as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The names of these peripherals in the device tree
did not match the Reference Manual for the RT500.
Also fixed a typo in a comment referring to USDHC which should have been
about USB.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- Adds the pin controls and ushdc settings in device tree
- Attaches clock to USDHC in soc.c
- Adds binding for mmc
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The value in this bitfield is provided in the two's complement form,
so it requires special handling. Previously, it was read as just an
unsigned value and this could result in a wrongly computed CAPVALUE.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This reverts commit 81908cd367.
This commit introduced a regression on SOF. Value of soc_cpus_active is
set by the core X it self in functions pm_state_set and
pm_state_exit_post_ops. soc_adsp_halt_cpu can by called only by the
primary core.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
For NPCX SMB/I2C SMB modules in FIFO mode, the registers include:
* Common registers, offset 0x00-0x0f, accessible regardless of the value
of BNK_SEL
* Bank 0 registers, offset 0x10-0x1e, accessible if BNK_SEL is set to 0
* Bank 1 registers, offset 0x10-0x1e, accessible if BNK_SEL
is set to 1
In the current driver, it uses two structures, `smb_reg` and
`smb_fifo_reg`, to access `Common + Bank 0` and `Common + Bank 1`
registers. But It might be easy to misunderstand that they are two
different modules.
This CL tries to simplify this by the following steps:
1. Use `union` to combine `Bank 0/1` registers in the same structure.
2. Remove `smb_fifo_reg`. We needn't use two structures to present
SMB registers.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit adds the support for host commands being transported
by the Serial Host Interface on the NPCX SoC.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
The code used the name DFDSPBRCP referring to the DSP Boot / Recovery
Capability Pointer register from DSP Subsystem Capability / Status
Registers range. The address used, however, pointed to DSP Core Shim
(DSPCS) registers block. Changed define names to not be misleading.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
1. Support Sleep, Deep Sleep and Deep Power down modes
2. Enable the MEMC FlexSPI driver when using device power
management so we can reconfigure the FlexSPI pins to
save power. The MEMC FlexSPI driver is enabled when we
enable the Flash subsystem, however we would like to
reconfigure the FlexSPI pins even when the Flash driver
is disabled, hence MEMC is selected when PM_DEVICE
is turned on.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Following updates previously done for other drivers, rename all
occurrences of S32 to NXP S32 to avoid ambiguity.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
hal_espressif systimer HAL calls are based on 1MHz reference.
This changes systimer driver to allow max clocking reference of 16MHz
and increases soc tick resolution by reducing min delay interval.
This also sets all ESP32-C3 socs to 16MHz hardware cycles reference.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add support for configuring FlexSPI1 clock speed to RT5xx soc
initialization, so that memory present on FlexSPI1 can be accessed.
Note that FlexSPI1 is referred to as FlexSPI2 in the dts files for this
SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
