Commit graph

5973 commits

Author SHA1 Message Date
Sylvio Alves
684a755be4 linker: esp32: add wifi rodata content
Map wifi library rodata content in the linker script.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-09-01 21:48:18 +00:00
Boon Khai Ng
ef3c0d2fa3 soc: arm64: intel_socfpga: Increase kernel VM size and memory size
This patch is to increase kernel VM size to 1.5MB and
memory size to 2MB to ready for future driver bring up.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
2022-09-01 14:30:59 -04:00
Antonio Tessarolo
d552338637 soc/imx: imx6sx and imx7 fix pinmux mask
According to RM the daisy chain mask should include both bit 0 and 1, not
only bit 0.
Updated bitmask accordingly

Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
2022-09-01 12:19:00 -05:00
Marcin Niestroj
356960bcb5 ARM: nxp_imx: rt10xx: add XTAL and RTC_XTAL DT clocks
There are two external clocks driving i.MX RT 10xx SoCs: XTAL and
RTC_XTAL. Add "fixed-clock" DT nodes for each. Update also "nxp,imx-ccm"
binding, so that CCM (Clock Control Module) peripheral consumes those
clocks by "xtal" and "rtc-xtal" names.

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-09-01 08:11:50 -05:00
Thomas Stranger
a41606ec52 soc: arch: stm32g0: fix strobe init for g070 an g0b0
The STM32G070 and STM32G0B0 Socs don't have USB power delivery support
but the PINs PD0, PD2, PB15, PA8 pins of these still have the same
pull down on boot configuration options as the SOCs with UCPD support.

This commit skips the check if such a peripheral is enabled,
therefore the configuration will always be applied on these SOCs
and the compile error is resolved.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2022-09-01 10:28:48 +02:00
Erwan Gouriou
7d9b7d2934 soc: stm32u5: Request header-size 1024 when using imgtool
On STM32U5 series, when an image is build with mcuboot,
image starts at offset 0x400 instead of default 0x200.

This should be taken into account when calling imgtool by using
dedicated option to set header-size value.


Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-09-01 10:28:33 +02:00
Kumar Gala
ffb7793a6f soc: esp32: remove Kconfig.defconfig* setting of clock control drivers
Now that clock control drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-09-01 10:26:30 +02:00
Ederson de Souza
a7e9166574 soc/xtensa/intel_adsp/cavs: Fix XTENSA_CCOUNT_HZ value
The default value is actually 400MHz on cavs15 and cavs18.

Fixes: #49711

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-01 10:25:45 +02:00
Kumar Gala
3712e44fe0 intc: remove Kconfig.defconfig* setting of interrupt controller drivers
Now that interrupt controller drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-09-01 10:25:36 +02:00
Marcin Niestroj
611326b667 ARM: nxp_imx: rt10xx: remove unused LPUART peripheral header include
This allows to disable UART peripheral driver and still be able to build
correctly (header is not visible when LPUART driver is not enabled).

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-09-01 10:25:13 +02:00
Marcin Niestroj
b47e6cc8ce ARM: nxp_imx: rt10xx: get systick freq from 'sysclk' DT nodelabel
So far systick frequency was duplicated in 'sysclk' DT nodelabel's
'clock-frequency' property and in per SoC SYS_CLOCK_HW_CYCLES_PER_SEC
default value. Set the latter based on DT configuration.

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-09-01 10:24:55 +02:00
Andrzej Kaczmarek
f19252567c drivers: pinctrl: Add driver for smartbond
This adds pinctrl driver for Renesas SmartBond(tm) MCU family.

Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
2022-08-31 20:32:03 +02:00
Andrzej Kaczmarek
69cddb1a29 soc: Add Renesas SmartBond(tm) DA1469x series SoC
This adds initial support for Renesas SmartBond(tm) DA1469x series SoC.

Initailly only DA14699 is explicitly supported, however this code should
also run on other SoCs in this series since all of them support the same
core features available initially.

Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
2022-08-31 20:32:03 +02:00
Nils Larsen
a3bae01e74 drivers: sdhc: add clock init for USDHC2-block of NXP i.MX-processors
The missing init is added analog to existing init of USDHC1 block.

Signed-off-by: Nils Larsen <nils.larsen@posteo.de>
2022-08-31 13:21:17 -05:00
Mahesh Mahadevan
ce0b24b95a soc: nxp: Remove the no cache linker script
This has been moved to the NXP HAL layer so that all
SDK NonCacheable symbols get placed in the nocache
region
Also pull in the HAL changes associated with this
change.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-08-31 12:16:30 -05:00
Gerard Marull-Paretas
0cd311c4a1 include: fix files using legacy include paths
Some files were still using the already deprecated include path, fix
this.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-31 06:49:00 -04:00
Adam Wojasinski
a04a451a9f soc: arm: nordic_nrf: Replace deprecated nrfx API
This commit replaces API that became deprecated with the release
of nrfx2.9 - see CHANGELOG in zephyrproject-rtos:hal_nordic repository

Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
2022-08-31 10:43:14 +02:00
Kumar Gala
4f2cbdb41a crypto: remove Kconfig.defconfig* setting of crypto drivers
Now that crypto drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-30 10:43:12 +00:00
Anas Nashif
4f81568286 intel_adsp: cavs: move CAVS linker script to series
This linker script is CAVS specific, so move it out of common/ and make
it part of the CAVS series.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-29 16:27:51 -04:00
Anas Nashif
f3729445e3 intel_adsp: cavs: push all common kconfigs into series
Consolidate common kconfigs of the CAVS series into the series level and
remove duplication among all supported SoCs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-29 16:27:51 -04:00
Stephanos Ioannidis
5e45769c94 soc: openisa_rv32m1: Update target architecture for GCC 12
This commit updates the custom target architecture type specified for
the `SOC_OPENISA_RV32M1_RI5CY` and `SOC_OPENISA_RV32M1_ZERO_RISCY` SoC
types to be compatible with the GCC 12, which now uses the ISA spec
20191213 by default.

Note that the hack overriding the build system-default `-march` flag
for these SoCs needs to be removed and they should be properly
specified using the ISA extension Kconfigs.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-08-29 16:57:18 +02:00
Carlo Caione
5fece03d7d riscv: Introduce Zicsr and Zifencei extensions
And enable the new extensions on all the SoCs.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-08-29 16:57:18 +02:00
Kai Vehmanen
8195ea7ea0 logging: Intel ADSP mtrace logging backend
Implements a logging backend implementing the mtrace protocol
to relay log messages over SRAM. This protocol is implemented
by the SOF Linux driver ("mtrace" debugfs interface).

This implementation follows example of the ADSP HDA logger implemented
in commit 6913da9ddd ("logging: cAVS HDA based logger").

Cc: Tom Burdick <thomas.burdick@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-08-29 10:43:42 +02:00
Kai Vehmanen
45c82c9090 arch/xtensa: adsp: add SRAM window 2 initialization
Define SRAM window 2 details to the headers and open access to host to
the window in bootloader.

Also clarify Kconfig documentation that the semantics of the windows can
vary depending on which host<->DSP communication scheme is in use.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-08-29 10:43:42 +02:00
Gerard Marull-Paretas
014d831d80 soc: arm/riscv: gigadevice: enable reset controller by default
Similar to pinctrl, almost all device drivers will depend on the reset
controller being available, so default the driver class to y at SoC
level.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-29 10:30:49 +02:00
TOKITA Hiroshi
702d079007 soc: arm: gigadevice: Add support for GD32F407 soc
Add initial support for GD32F407 soc

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-08-29 10:27:15 +02:00
Tom Burdick
3a4864bdd2 logging: adsp hda backend improvements
* Adds a default hook and init function for cavstool.
* Adds an optional padding on flush feature to ensure all data is written.
* Fixes an error in cavstool.py for correctly wrapping the ring buffer.
* The test case now ensures wraps and flushes occur numerous times.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-08-26 21:33:10 -04:00
Anas Nashif
6c7bf09222 intel_adsp: fix leakage of Kconfigs in soc family defconfig
Add missing conditionals and move CAVS related configs into own series
defconfig.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-26 13:17:02 -04:00
Kumar Gala
8d9f9d50f4 dma: remove Kconfig.defconfig* setting of DMA drivers
Now that DMA drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-26 14:27:23 +00:00
Kumar Gala
04adb949d1 soc: xilinx: zynq7000: move to using DT_STRING_UPPER_TOKEN_BY_IDX macro
Replaced hand coded use with DT_STRING_UPPER_TOKEN_BY_IDX.  We should have
introduced the APIs when this was needed since the token values in
devicetree_generated.h should only be accessed via an API macro.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-25 15:00:24 -07:00
Kumar Gala
1314d73104 I2S: remove Kconfig.defconfig* setting of I2S drivers
Now that I2S drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-25 15:03:11 -05:00
Yves Vandervennet
6b66d7f266 flash: nxp: enabling lpc55s36's FMC
This commit enables the SoC's flash memory controller.

 - added lpc55s36 specific code in the NXP MCUX driver
   to take advantage of the SoC's check-before-read
   capability
 - enabled the FMC node in the SoC's dtsi (iap)
 - added the flash controller chosen node to the board's dts

Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
2022-08-25 10:24:41 -05:00
Gerard Marull-Paretas
056734bea8 soc: riscv: ite: remove pinmux/pinctrl dead code
Remove unused definitions coming from the pre-pinctrl era.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-25 13:55:47 +00:00
Kumar Gala
3f8ba07b90 usb_device: remove Kconfig.defconfig* setting of usb device drivers
Now that usb device drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-25 08:05:54 -05:00
Gerard Marull-Paretas
c50316ecde soc: gigadevice: gd32f403: use DT for SYS_CLOCK_HW_CYCLES_PER_SEC
Set the default value for SYS_CLOCK_HW_CYCLES_PER_SEC based on DT cpu0
clock-frequency property.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-25 09:09:51 +00:00
Gerard Marull-Paretas
b9f1a0cfe6 soc: gigadevice: gd32f4xx: use DT for SYS_CLOCK_HW_CYCLES_PER_SEC
Set the default value for SYS_CLOCK_HW_CYCLES_PER_SEC based on DT cpu0
clock-frequency property.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-25 09:09:51 +00:00
Mahesh Mahadevan
32e2e1cb79 dts: lpc55S6x: Add back the USB SRAM region
USB SRAM region was accidentally deleted by an earlier
commit. Rename the memory region used by USB to USB_SRAM instead
of SRAM4. SRAM4 was the wrong name for this region.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-08-24 10:08:40 +02:00
Francois Ramu
3fafe7fdee drivers: dma: new dma peripheral driver for stm32u5
It includes the definition for the DMA peripheral of this type,
present on stm32U5 devices.
A particular DMA_STM32U5 config is selected for that purpose.
The driver is derived from the existing dma_stm32.c
The GPDMA is counting channels (0-15) ; stream offset is 0.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-08-24 10:05:32 +02:00
Anas Nashif
a04d06514a Revert "intel_adsp: cavs: irq: simplify code"
This reverts commit 2241fb0592.

Fixes #49200

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-23 20:46:10 -04:00
Pieter De Gendt
afc784c2ea soc: mimxrt1064: Add HAL clock header include
The low power mode logic for i.MX RT1064 indirectly includes the HAL
definitions, but this is fragile and depends on specific Kconfig options.

This fixes build issues if for example CONFIG_ARM_MPU is not set.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2022-08-23 11:39:27 -05:00
Richard Osterloh
258737b2ef soc: arm: stm32f4: Add STM32F423 support
Add support for STM32F423xx devices in dts and soc

Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
2022-08-23 16:23:55 +02:00
Tim Lin
822c37745e soc: it8xxx2: pull more function into ram code section
Pull more function into ram code section to effectively improve
access speed and performance.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-08-23 10:16:36 +02:00
Tim Lin
cb041d062f ITE: drivers/i2c: Add I2C FIFO mode
Adding I2C FIFO mode can reduce the time between each byte to
improve the I2C bus clock stretching during I2C transaction.
The I2C master supports two 32-bytes FIFOs, channel A and C
are supported now.

I2C FIFO mode of it8xxx2 can support I2C APIs including:
i2c_write(), i2c_read(), i2c_burst_read.

Test:
1. tests\drivers\i2c\i2c_api --> pass
2. Reading 16 bytes of data through i2c_burst_read() can reduce
   0.52ms(2.4ms->1.88ms) compared to the original pio mode when the
   frequency is 100KHz.
3. It is normal to read sensor data through I2C on Nereid's platform.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-08-23 10:16:36 +02:00
Wei-Tai Lee
534d61b48c soc: riscv: andes_v5: use syscon driver instead of accessing dts directly
Access syscon area by driver instead of parsing dts node.

Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-08-23 10:15:50 +02:00
Emilio Benavente
76e8909658 soc: arm: nxp: rt595: Attached clock freq to pmic
Attached the correct clock frequency for
FlexComm15 which connects to the PMIC_I2C peripheral

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2022-08-23 10:13:51 +02:00
Flavio Ceolin
96e988c53a intel_adsp: Do not use xtensa hal with xcc-clang
Do not usu XTENSA_HAL when building with xt-clang, instead uses
the HAL provided together with the toolchain. Just like it is
done with "xcc" toolchain variant.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-08-23 10:13:43 +02:00
Gerard Marull-Paretas
a202341958 devices: constify device pointers initialized at compile time
Many device pointers are initialized at compile and never changed. This
means that the device pointer can be constified (immutable).

Automated using:

```
perl -i -pe 's/const struct device \*(?!const)(.*)= DEVICE/const struct
device *const $1= DEVICE/g' **/*.c
```

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-22 17:08:26 +02:00
Evgeniy Paltsev
ee5b158e3a ARC: boards: QEMU: hs6x: minor description polish
Non-functional polish of Kconfig symbol description and
QEMU_CPU_TYPE_${ARCH} variable (used only for verbose cmake comments)
for HS6x QEMU.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
2022-08-22 10:23:14 +00:00
Evgeniy Paltsev
2adfe5ce65 ARC: boards: ARCv3: add qemu_arc_hs5x board
Add qemu_arc_hs5x - single core ARCv3 32bit HS5x CPU.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
2022-08-22 10:23:14 +00:00
Immo Birnbaum
4a8e766526 soc: xilinx_zynq7000: remove static MMU entries for PS UARTs
Remove the static MMU entries for each available Xilinx PS UART
instance. Those are no longer required now that the PS UART
driver uses the DEVICE_MMIO API for register space mapping.

Signed-off-by: Immo Birnbaum <immo.birnbaum@weidmueller.com>
2022-08-19 20:41:26 +00:00