This re-implements the CONFIG_XTENSA_RPO_CACHE and its cached
and uncached region support in the SoC layer. This is in
preparation for removing RPO cache in the architecture layer
as this is a SoC feature and not an architecture feature.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This allows SoC to define their custom cache related functions
and are used by sys_cache_*() functions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
arch_mem_coherent() is cache related so it is better to move it
under cache subsys. It is renamed to sys_cache_is_mem_coherent()
to reflect this change.
The only user of arch_mem_coherent() is Xtensa. However, it is
not an architecture feature. That's why it is moved to the cache
subsys.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The macro ARCH_XTENSA_SET_RPO_TLB is only used for Intel Audio
DSP. The specific memory mapping requiring this is SoC specific
feature and not a feature on Xtensa in general. It should not be
declared in the architecture layer. So move it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a kconfig to indicate a memory mapping where physical
memory regions are both mirrored and mapped in different
addresses. Accessing one set of addresses is via CPU cache
while the other is directed to memory.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves the ace-link.ld into include/linker to indicate it is
to be included by the main linker script. Also rename it to
ace-link-mirrored.ld to indicate that it is for the mirrored
cache configuration.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The Zephyr linker script usually puts something before
z_mapped_start (where .text is), for example, vecbase vectors.
So we need to reserve those space or else k_mem_map() would be
mapping those which may result in faults.
To avoid mapping there, CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES
needs to be used. Since it is common when MMU is enabled, we
should enable it by default using imply. All current Xtensa
MMU SoCs all have this selected anyway. Using 'imply' instead
of 'select' is to allow it to be disabled if so desired.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Rework the SoC MMU mappings in preparation for removal of
double mapping code in Xtensa architecture code. This will let
the SoC layer and application to fine tune memory mappings
instead of having double mapping forcibly applied everywhere.
The modified mapping array mimics what the double mapping
would have done simply to have the same behavior. Future
optimizations can be done to remove unnecessary mappings.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the arch default MMU mappings into the SoC mapping
array. This is in preparation of not forcibly doing double
mapping in architecture code as this type of double mapping
should be specified for individual regions. This allows
the SoC layer to fine tune the mappings as not anything
needs to be double-mapped.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Moves the HiFi related kconfigs to their respective SoC
kconfigs as it is specific to the SoC... and this requires
creating new kconfigs for each SoC series.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SCMI CPU protocol is in fact a vendor extension from NXP. The current
naming used for the CPU protocol definitions (i.e. functions, structures,
macros) follows that of the SCMI standard protocols, which might be
misleading.
Include "nxp" in the name of all of the CPU protocol definitions.
This change was performed mechanically using "git grep" and "sed -i"
with some manual intervention.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
When the firmware wrote data to KBC/AUX output buffer, the hardware
automatically generated IRQ1/12 to notify the host. After the host read
the data, the EC received an output buffer empty (OBE) interrupt to
indicate that the next byte could be written. However, on the NPCX9M7FB,
this mechanism may cause IRQ1/12 to be missed if the firmware write new
data immediately after detecting that the output buffer is empty,
resulting in incorrect behavior.
To avoid missing IRQ1/12, the flow is changed so that it first checks
VWIRE_AVAIL to ensure no pending VW events. If no VW event is pending,
the firmware writes data to the output buffer and explicitly asserts
IRQ1/12 to notify the host. After the host reads the data and the OBE
interrupt triggers, the firmware clears IRQ1/12.
This updated sequence prevents IRQ1/12 from being lost and ensure
correct notification behavior.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Add DT helper file for PIC32CX-SG family devices to support
SoC-specific device tree definitions and utilities.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
If CONFIG_WDT_DISABLE_AT_BOOT is not defined (i.e. WDT should be enabled
at boot), DISABLE_WDOG should be 0 (disabled).
Signed-off-by: Alexandre Rey <alx.rey@icloud.com>
If the event timer or free-run timer is close to expiration when
system enters idle with I2C target DMA mode enabled, the memory
and CPU clocks may become unsynchronized after wakeup. This
causes CPU to fetch incorrect data and eventually trigger SoC
watchdog timeout.
Due to this hardware limitation, SoC should skip entering idle
mode if the remaining timer value is less than 150µs(safe margin).
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
The accuracy field of lfocs lfxo is incorrectly parsed from the SVD
file. Instead of stripping the "ppm" from the value before converting
it to an int, we are taking only the first three digits. This works
for 500ppm, but not for 20ppm.
Patch to strip last three digits instead.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Complement #99761 that added register includes to too few files.
Fix build error for some boards using these SoCs.
Signed-off-by: Josuah Demangeon <josuah.demangeon@nordicsemi.no>
Microchip MEC parts have a similar GPIO peripheral block. We
create a unified driver for all parts. NOTE: MEC GPIO interrupt
detection sets active status when changed from interrupt detect
disabled to any enabled mode. Driver ISR and interrupt configuration
implementation includes work-arounds for this issue.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
LPFLL (soc: scg: "lpfll_clk") clock source can be now selected
in KE1xz Device tree (nxp_ke1xz.dtsi., board.dts or overlay)
Tested on boards: frdm_ke15z, frdm_ke17z, frdm_ke17z512
Signed-off-by: Michael Galda <michael.galda@nxp.com>
Signed-off-by: Hake Huang <hake.huang@nxp.com>
If the stack is in ITCM, DTCM, or FlexRAM OCRAM, flexram_dt_partition()
may change its contents. The comment on flexram_dt_partition()
acknowledges that, stating that it's inlined because it "cannot use
[the] stack". But we currently call SystemInit(), which is not inlined
and does use the stack, prior to flexram_dt_partition()! Fix that issue
by reordering the calls.
It seems to me that flexram_dt_partition() would be safer as a
soc_early_reset_hook implemented in assembly, but this fix does work for
the moment. Tested on an i.MX RT1061, with the stack in FlexRAM OCRAM
and entering Zephyr with all FlexRAM allocated to ITCM and DTCM.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
If the stack is in ITCM, DTCM, or FlexRAM OCRAM, flexram_dt_partition()
may change its contents. The comment on flexram_dt_partition()
acknowledges that, stating that it's inlined because it "cannot use
[the] stack". But we currently call SystemInit(), which is not inlined
and does use the stack, prior to flexram_dt_partition()! Fix that issue
by reordering the calls.
It seems to me that flexram_dt_partition() would be safer as a
soc_early_reset_hook implemented in assembly, but this fix does work for
the moment. Tested on an i.MX RT1061, with the stack in FlexRAM OCRAM
and entering Zephyr with all FlexRAM allocated to ITCM and DTCM.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Generate PERIPHCONF SPU/CTRLSEL entries based on pinctrl properties
on the local domain peripherals as well as the global ones.
This fixes an issue where the required pin configuration was not
generated for the pinctrls on the radio local domain GPIOTE0 on
nrf54h20.
The secure attribute of nodes without an address and without a bus node
are now interpreted as being secure by default, instead of failing with
an error. This prevents the parsing of certain nodes from triggering
failing the build (in particular the 'ieee802154' node in
cpurad_peripherals).
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Since caching is enabled before z_data_copy(), RAM
functions may still be cached in the d-cache instead
of being written to SRAM. In this case, the i-cache
will fetch the wrong content from SRAM. Thus, using
"fence.i" to fix it.
Signed-off-by: Jacky Lee <jacky.lee@egistec.com>
Add eim, erm and edac instance for frdm_mcxa153, frdm_mcxn236,
frdm_mcxn947, frdm_mcxe247 and frdm_mcxe31b.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
nrfx_power_constlat API returns negative value if
the requested action has no effect, which is expected
in cases of multiple requests/releases. Align nrf_sys_event
to not treat it as an error.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
Please note that when performing conversions,
the selected channels must all be of the same type
(either ADC raw or V2T.)
Mixing ADC and V2T channels in a single conversion sequence is
not supported.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Enable instruction cache support for LPC55S36 SoC:
- Select CPU_HAS_ICACHE and HAS_MCUX_SYSCON_LPCAC
- Enable CACHE_MANAGEMENT and EXTERNAL_CACHE by default
- Set ICACHE_LINE_SIZE to 256 bytes
This enables the SYSCON LPCAC cache driver for improved
performance on the LPC55S36 SoC.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
This patch put in the same place the default value for
SYS_CLOCK_TICKS_PER_SEC. It also apply the sleeptimer clock frequency
when sleeptimer is used for sys clock.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
This patch introduce configuration of the symbol
'SYS_CLOCK_HW_CYCLES_PER_SEC' with dts entry rather than a hardcoded
value.
Clock control on siwx91x needs to use the clock frequency of the cpu
to init rather than the 'SYS_CLOCK_HW_CYCLES_PER_SEC' symbol,
otherwise we initialize the m4 clock with the ULP ref clock.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
To enhance throughput performance on the SiWx91x series, Added
some Siwx91x configurations by deafult.
Signed-off-by: Rahul Gurram <rahul.gurram@silabs.com>
GPPI initialization shall be executed as early as possible.
Add _ prefix to the initialization function to reduce chances that
other function calls uninitialized GPPI.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
When SHA is activated in the DT, configure it's register region with
strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
Select CPU_HAS_ICACHE and HAS_MCUX_LMEM_CACHE.
Default CACHE_MANAGEMENT=y and select EXTERNAL_CACHE.
Prepares MCXE24x to use the LMEM cache driver.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Enable clock control by default for siwx91x SoCs. Moreover, most
drivers for siwx91x soc depend on clock control, but didn't declare
it.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Split STM32 family-wide common Kconfig in two separate files: a new Kconfig
file `soc/st/stm32/common/Kconfig` to hold options that affect the common
code found in the same directory, and the existing top-level Kconfig file
`soc/st/stm32/Kconfig` which now only holds options used by multiple series
but not consumed by the common code - for example, options that are used by
SoC-specific code or consumed by the STM32Cube HAL module go in this file.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Instead of defining our own, use the DT_COMPAT_<> macro variables generated
by the build system inside the STM32 SoC Kconfig file.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add initial board support for the Space Cubics SC-OBC Module V1. The
hardware is based on an AMD Versal AI Edge VE2302 and a Microchip
IGLOO2. This Zephyr port runs on the Versal device’s Real-Time Processing
Unit (dual Arm Cortex-R5F).
This commit is the first in the series and only supports the basic devices
needed to run samples/hello_world and samples/philosophers. Specifically,
it adds the Cortex-R5F, UARTs, and the GIC interrupt controller.
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Emit the IVT section and IVT header only when XIP and the image is either
a standalone XIP app or MCUboot itself. Do not emit the IVT when the
Zephyr image is chain-loaded by MCUboot (BOOTLOADER_MCUBOOT=y).
- linker.ld/sections.ld: place .ivt_header at IVT_HEADER only under
XIP && (!BOOTLOADER_MCUBOOT || MCUBOOT).
Provide __ivt_region_start/end symbols.
- soc.c: guard IVT struct under the same condition and mark it 'used'
so the linker keeps it when needed.
- Kconfig.defconfig - Make the bootloader and the sign tool compatible
with the vector table.
This avoids populating 0x400000 IVT from the app image while retaining it
for MCUboot or standalone XIP use-cases.
Files:
- soc/nxp/s32/s32k3/linker.ld
- soc/nxp/s32/s32k3/sections.ld
- soc/nxp/s32/s32k3/soc.c
- soc/nxp/s32/s32k3/Kconfig.defconfig
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Use devicetree to provide the system clock frequency for S32K3
instead of hardcoding it in board defconfigs.
- Add clock-frequency to /cpus/cpu@0 in nxp_s32k344_m7.dtsi using
DT_FREQ_M(160).
- Define DT_SYSCLK_PATH and derive SYS_CLOCK_HW_CYCLES_PER_SEC from
the sysclk node via dt_node_int_prop_int() when CORTEX_M_SYSTICK.
- Remove CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC from mr_canhubk3
This keeps the clock configuration in a single SoC-level place,
aligns S32K3 with other NXP Cortex-M SoCs, and ensures both the
MCUboot and application builds share the same
SYS_CLOCK_HW_CYCLES_PER_SEC.
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
The 'common' folder is under 'soc/microchip/sam' which contains both MCU
and MPU devices. Currently all the files in 'common' is for MPU. Adding
if(foo) in 'CMakeLists.txt' to make more obvious of where the files are
used.
Update soc/microchip/sam/common/CMakeLists.txt with combining the .c
files with the same usage into one 'zephyr_source' call.
Signed-off-by: Tony Han <tony.han@microchip.com>
