Commit graph

6,613 commits

Author SHA1 Message Date
Aksel Skauge Mellbye
fff250c21d soc: silabs: Introduce family specific defconfig
Defconfig was only available at the vendor and series level,
make it possible to have family specific definitions too.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2024-10-22 20:41:23 +02:00
Aksel Skauge Mellbye
3d0909ed18 soc: silabs: Initialize DCDC from device tree
The DC-DC converter was unconditionally initialized with default
settings on Series 2. Add device tree binding and nodes, and guard
call to init function. Map DT options to config header from HAL.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2024-10-22 20:41:23 +02:00
Yves Vandervennet
adeeb10f4f board: mimxrt1170_evk: fix linkserver support to debug RAM images
- add ITCM definitions (for LinkServer) in board.cmake
- update of soc.c to support RAM images (stack pointer)
- doc update

Change applies to both versions of the MIMXRT1170 EVK

Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
2024-10-22 20:40:39 +02:00
Maureen Helm
2f03561399 soc: adi: Extract max32 flashprog section to a dedicated linker script
Extracts the max32 flashprog linker section to a dedicated linker script
that is conditionally included only when the flash driver is enabled.
This prepares max32 soc family to set SOC_LINKER_SCRIPT directly to the
common arm cortex-m linker script.

Signed-off-by: Maureen Helm <maureen.helm@analog.com>
2024-10-22 20:39:41 +02:00
Declan Snyder
f28725e6d5 soc: mcxw71: Enable LPSPI
Add DTS nodes and SOC clocking for LPSPI

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-10-21 18:39:49 -05:00
Filip Kokosinski
0a5b0abfcc soc/sifive/sifive-freedom: enable PMP by default on 64-bit SoCs
This commit enables PMP on 64-bit SoCs from the SiFive Freedom SoC series
by default.

This change is needed to e.g. run the Userspace Hello World demo.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-10-21 15:55:52 +02:00
Teresa Zepeda Ventura
6773f33445 drivers: spi: gecko: add new driver for SPI communication via EUSART
Added a new driver to support SPI communication via EUSART. Since the
Silabs EFR32MG24 family SoCs have only one USART, EUSART support is
necessary for implementing SPI functionality.

Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
2024-10-21 12:46:21 +02:00
Tu Nguyen Van
81f889d297 soc: dts: pinctrl: support the configurations which apply for LVDS pads
support the configurations which apply for LVDS pads
+ termination resistor
+ current reference control
+ rx current boost

Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
2024-10-21 12:39:04 +02:00
Alvis Sun
578fbca78d soc: nuvoton: reg: add i3c target registers and soc functions
As title.

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
2024-10-21 12:36:21 +02:00
Robin Kastberg
2ce0fd6172 soc: nxp: imxrt: MIMXRT1062 IVT needs to be FIRST
IMXRT1062 bootrom reads boothdr initial vector table
from 0x60001000. In the CMAKE scatter linker scripts we put multiple
sections at offset 0x1000 in the rom. In linkers other than LD, we are
not guaranteed a particular order when placing these.
If we specify FIRST we can count on the .ivt coming first. The other
positions aren't as crucial.

From IMXRT1060RM.pdf 9.7.1

> The location of the IVT is the only fixed requirement by the ROM.
> The remainder or the image memory map is flexible and
> is determined by the contents of the IVT.

Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
2024-10-21 12:36:02 +02:00
Carles Cufi
51c1e45301 soc: nordic: Remove the nRF54L15 EngA
The production version of the nRF54L15 SoC is now available, so remove
the initial Engineering A (EngA) preview version.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2024-10-21 01:46:39 +01:00
Yassine El Aissaoui
906a5ec37b soc: nxp: rw: Introduce HAS_NXP_MONOLITHIC_BT config
This config will be used to indicate if a platform
has the support for monolithic BT feature.

Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
2024-10-18 17:45:07 +01:00
Michał Stasiak
c092964dd2 modules: hal_nordic: Add new PDM instances
New PDM, some present on nRF54L15 FP1, instances have
been added. Modified condfiguration file for nRF5340,
which now requires PDM0 instance.

Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
2024-10-18 08:19:01 -04:00
Ha Duong Quang
12bb3fb9b1 soc: nxp: s32ze: add support eDMA3 for S32Z270
Enable support EDMA for S32Z270.
Add eDMA3 instance 0, 1, 4 and 5 for S32Z270 devices.

Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
2024-10-18 14:16:05 +02:00
Lucien Zhao
ef4ff8eb2c dts: arm: nxp: rt118x: add flexcan instances
Enable flexcan clocks
add 3 flexcan instances

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2024-10-18 09:18:07 +02:00
Jamie McCrae
85710f1727 soc: nordic: nrf53: Make GPIO pin forwarding automatic
Allows forwarding GPIO pins to network core automatically if the
devicetree node exists.

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2024-10-17 15:38:22 -04:00
Andrej Butok
36707c1bd4 soc: nxp: k6x: disable on reset NMI and EzPort
- Disables on reset NMI and EzPort.
- Fixes frdm-k64 SW3 user button on reset issue.
  So it can be assigned to the mcuboot-button0 alias.

Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
2024-10-17 10:49:26 -04:00
Krzysztof Chruściński
6253c0678e soc: nordic: nrf54h: cpuapp: Don't use serial shell when ETR is used
ETR handler (for Coresight STM logging) is using console UART and
can act as the shell backend. When that happens default serial shell
backend shall be disabled (and it is by default enabled if there is
a zephyr,console chosen set.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2024-10-17 10:48:25 -04:00
Yassine El Aissaoui
ad8b62413d soc: MCXW71: Add BLE support
- Add IMU regions
- Add HCI definition
- Add config when BT is enabled

Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
2024-10-17 09:45:42 +02:00
Sylvio Alves
59f0418d2e soc: esp32: unify runtime heap usage
This commit applies several changes in the way "heap_runtime"
feature is used. It can't be split due to bisectability issues.

Whenever the feature is enabled, a new heap is created and
custom malloc/calloc/free functions are added into the build
system. Those functions are currently used for internal Wi-Fi and BLE
drivers only.

Such changes are described below:

1) Rename heap.c to esp_heap_runtime.c for better readability.
2) Rename RUNTIME_HEAP to HEAP_RUNTIME to make it similar to what is
available in Zephyr.
3) Add runtime heap to BT as such as Wi-Fi.

Fixes #79490
Fixes #79470

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-10-17 09:45:02 +02:00
Tom Chang
cbb322937f drivers: espi: npcx: support espi taf rpmc request
This commit adds support for handling espi taf rpmc requests.

Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
2024-10-17 09:44:39 +02:00
Andrzej Głąbek
edc4f75b61 soc: nordic: Fix the way of enabling clock control for nRF54H Series
This is a follow-up to commit 7a2ce2882a.

Do not enable clock control by default on nRF54H Series SoCs when
the system timer is present, because clock control is not needed
for this purpose there.

Add missing `default y` in the CLOCK_CONTROL_NRF2 Kconfig option that
enables compilation of clock control drivers for nRF54H Series.
This way modules that actually require clock control (like drivers
that use radio) will be able to enable it using the generic option
(CLOCK_CONTROL), not the above one that is specific for nRF54H.

Update accordingly applications that referenced the CLOCK_CONTROL_NRF2
option.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2024-10-16 16:36:51 +01:00
Marcio Ribeiro
7e7672cb4b bugfix: esp32: allows QIO and QOUT flash modes
Allows QIO and QOUT flash mode to work on:
- esp32s2
- esp32s3
- esp32c2
- esp32c3
- esp32c6

Fixes #73677

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-10-16 12:26:52 +02:00
Yangbo Lu
7f4c074114 soc: nxp: imxrt118x: enable and configure M33 MPU
Enabled and configured M33 MPU.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2024-10-16 10:00:32 +02:00
Yangbo Lu
4d248fda87 soc: nxp: imxrt118x: add NonCacheable section for M33 linker
The NonCacheable section is required by HAL driver.
Added it with using DTCM.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2024-10-16 10:00:32 +02:00
Yangbo Lu
f83a695f25 soc: nxp: imxrt118x: add NETC clock init support
Added NETC clock init support.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2024-10-16 10:00:32 +02:00
Yangbo Lu
8f99767dd3 soc: nxp: imxrt: increase system workqueue stack for NETC
Increased system workqueue stack for NETC to use.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2024-10-16 10:00:32 +02:00
Kai Vehmanen
52efa3bb9b soc: intel_adsp: tools: fix ace15 ROM status check in cavstool.py
Fix definition for ROM status register for ACE1.5. The value should be
same as ACE2.0 and only different for ACE3.0.

Fixes: 6ad9b6ccab ("soc: intel_adsp: tools: add intel_adsp_ace30
support to cavstool.py")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2024-10-15 19:01:35 +01:00
Tim Lin
7fa962589f ITE: it8xxx2: Remove CONFIG_PINCTRL from soc defconfig file
The driver Kconfig determines whether pinctrl is enabled
instead of soc defconfig.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2024-10-15 13:52:55 +02:00
Nikodem Kastelik
6300e1bc25 soc: nordic: nrf54l: remove normal voltage mode
Normal voltage mode is no longer supported by MDK 8.67.0.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2024-10-15 04:27:42 -04:00
Declan Snyder
8a104729c4 soc: nxp: mcxw71: Add LPI2C node and clocking
Add LPI2C node and default clocking in soc.c

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-10-15 04:09:34 -04:00
Daniel DeGrasse
feb0241536 soc: nxp: lpc55xxx: fix dependencies for SOC_FLASH_MCUX
SOC_FLASH_MCUX has additional dependencies for LPC55xxx CPUs, due to the
fact that the flash should be disabled when executing in nonsecure mode.

Since the merge of HWMv2, this dependency has been set incorrectly at
the SOC level, resulting in the IAP flash driver being enabled when
targeting CPU1, which is incorrect. Fix the Kconfig dependency to
resolve this issue.

Fixes #79576

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-10-15 04:08:15 -04:00
Francois Ramu
48a2aedb78 soc: st: stm32h7rs serie requires specific power rails
Enables the XSPIM2 rail when using GPIO bank N
Enables the XSPIM1 rail when using GPIO bank O or P
Enables the USBvoltage detector when using the GPIO M

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-10-11 13:16:43 -04:00
Sylvio Alves
e48639e460 soc: esp32c6: add LLEXT linker entry
Make sure LLEXT sections are properly placed to avoid
orphan declaration.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-10-10 10:06:53 +02:00
Rafal Dyla
ec77fc399c modules: hal_nordic: Add global domain power request service
Service for powering peripherals that use GPIO pins
in the global power domains:
- Active Fast
- Active Slow
- Main Slow

Signed-off-by: Rafal Dyla <rafal.dyla@nordicsemi.no>
2024-10-09 18:36:47 +01:00
Ioannis Damigos
6c6a1e550c da1469x: Remove CONFIG_PINCTRL from all defconfig files
Remove CONFIG_PINCTRL from all defconfig files.

Fixes #78619

Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
2024-10-08 16:57:41 +02:00
Vaishnav Achath
1b8158b212 soc: ti: k3: am6x: Fix AM62X M4 RAT initialisation
Commit b73c5578e3 ("soc: ti: move init code from SYS_INIT to hooks")
changed SYS_INIT to init hooks. For AM6x M4 target soc_prep_hook()
was added by mistake instead of soc_early_init_hook(), the platform needs
RAT translation initialized before any other operation and the platform
failed to boot with this change, fix this by replacing with
soc_early_init_hook()

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
2024-10-07 20:15:41 -04:00
Peter Fecher
6560128418 dts: arm: nxp: nxp_imx8m_m4: Add ECSPI devices
Add device tree instances for ECSPI devices,
update SoC code to enable clocks.

Signed-off-by: Peter Fecher <p.fecher@phytec.de>
2024-10-07 18:43:35 +02:00
Laurentiu Mihalcea
8a1785b8aa soc: nxp: soc.yml: remove unsupported cpu clusters for imx8 socs
Some imx8 socs have cpu cluster entries for cores that
are not currently supported. Remove them.

Fixes #79027.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-10-07 18:43:26 +02:00
Hou Zhiqiang
fd103f2ccc soc: nxp: imx95: fix indent of MMU entry
Fix the indent of LPUARTs MMU setup entry.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2024-10-07 18:43:20 +02:00
Gerard Marull-Paretas
a9d0eacae2 soc: nordic: nrf54h20: add support for nRF54H20 EngB
nRF54H20 EngB is a re-label to the existing hardware revision for the
nRF54H20. nRF54H20 (whithout EngX) is becoming the final revision of the
SoC.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-10-07 18:42:14 +02:00
Adam Kondraciuk
bc7a5b6781 drivers: timer: nrf_grtc_timer: Align Zephyr to new AUTOEN read manner
The new GRTC reading manner of the SYSCOUNTER uses hardware mechanism which
allows to keep it alive when any of CPUs is not sleeping. Otherwise
the SYSCOUNTER goes into sleep mode. Thus there is no
longer need to maintain the `CONFIG_NRF_GRTC_SLEEP_ALLOWED` symbol, however
if the user wants to have the SYSCOUNTER enabled all the time the
`CONFIG_NRF_GRTC_ALWAYS_ON` can be used instead.
The nrfx_grtc  driver no longer provides the `wakeup-read-sleep` reading
manner.
Also setting the GRTC clock source is performed by the nrfx_grtc driver so
it has been removed from the `sys_clock_driver_init()` function.

Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
2024-10-07 18:42:14 +02:00
Gerard Marull-Paretas
97dff5bccb modules: hal_nordic: align PDM configuration
Introduce instance 0, PDM0, following nrfx 3.7.0 update.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-10-07 18:42:14 +02:00
Maureen Helm
82a00c9cb8 soc: adi: max32: Indicate Segger RTT support
Sets CONFIG_HAS_SEGGER_RTT on the max32 soc family to allow using RTT
backends in the logging, shell, and tracing subsystems.

Signed-off-by: Maureen Helm <maureen.helm@analog.com>
2024-10-06 20:51:27 +01:00
Yassine El Aissaoui
ad673d18b7 soc: rw: Fix stack over flow during BLE init
RW requires more stack size now,
value changed from 1024 to 1280.

Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
2024-10-04 10:50:00 +01:00
Krzysztof Chruściński
3786b617bd soc: nordic: Disable asserts on ppr and flpr
Asserts are by default enabled for tests but flpr and ppr are
small cores (<64k) and many tests does not fit in memory with
asserts enabled.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2024-10-04 10:45:57 +01:00
Jyri Sarha
32f9ecacc4 soc: intel_adsp: tools: cavstool.py: Add debug_slot_offset_by_type()
Add debug_slot_offset_by_type() for getting debug window slot offset
by type identifier. How to find the correct slot and what types there
are is documented here:

soc/intel/intel_adsp/common/include/adsp_debug_window.h

In a normal situation a client program would try to find a specific
slot right after DSP boot. Because of that the we can not expect it to
be there immediately. Instead we need to try multiple times and give
firmware some time to update the debug slot descriptor table.

Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
2024-10-03 22:00:33 +01:00
Yong Cong Sin
52a202309b zephyr: bulk update to DT_NODE_HAS_STATUS_OKAY
Change instances of:

DT_NODE_HAS_STATUS(<node_id>, okay)

to

DT_NODE_HAS_STATUS_OKAY(<node_id>)

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-10-03 17:06:52 +01:00
Jyri Sarha
80e629cd97 soc: intel_adsp: tools: cavstool.py: Add debug_slot_offset()
Add debug_slot_offset() function for getting a debug slot offset by
the slot number.

Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
2024-10-03 11:39:15 +01:00
Jyri Sarha
9563960bde soc: intel_adsp: tools: cavstool: Fix fw_is_alive() and wait_fw_entered()
The fw_is_alive() depends on 'dsp' global variable which is assigned
from map_regs() return value. To make fw_is_alive() and
wait_fw_entered(), that calls fw_is_alive(), callable from another
module, the 'dsp' variable needs to be passed as an argument.

Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
2024-10-03 11:39:15 +01:00