The boot container was using a non-standard symbol name
`__rom_start_address` for the ROM start address. This symbol
is not defined when build with `-DCONFIG_CMAKE_LINKER_GENERATOR=y`.
This commit use the symbol `__rom_region_start` which is
available for both cases.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
The arbitrary ordering of ILINK may cause the .last_section
to be placed between the gaps of consecutive sections in the ROMABLE
region.
This commit adds a workaround for Renesas RA devices, which have OFS
registers placed in FLASH. Adding a small .rom_padding section at
the beginning of the ROM_REGION stabilizes the placement order and
ensures that all ROM sections remain within the expected region.
Signed-off-by: Thinh Le Cong <thinh.le.xr@bp.renesas.com>
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Switch OFS-related linker sections from GROUP FLASH to GROUP ROM_REGION
to avoid overlapiping placement with .text when build with GNU and
CONFIG_CMAKE_LINKER_GENERATOR=y of RA boards that have OFS in FLASH
Signed-off-by: Thinh Le Cong <thinh.le.xr@bp.renesas.com>
Add parameter to the link_layer_register_isr() to force
or not the link layer isr registration in case of multiple
function calls.
This change fixes the interrupt service when resuming
from a PM standby state.
Update Bluetooth hci_stm32wba.c driver and
IEEE 802.15.4 ieee802154_stm32wba.c driver accordingly.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Add initial support for the FocalTech FT9001 ARM Cortex-M SoC including:
- SoC Kconfig and dtsi integration points
- Early init and core setup
- Pinctrl base definitions
This prepares the tree for the FT9001 board and drivers.
Signed-off-by: Robert Cheng <robert.cheng@focaltech-electronics.com>
Configure the GAU (General Analog Unit) clock from T3 PLL 256M with
a divider of 4 to achieve 64MHz, replacing the previous configuration
that used the main clock at 260MHz main clock with a divider of 1.
The GAU ADC has a maximum clock frequency limit of 64MHz. The previous
260MHz clock configuration caused incorrect conversion results when
operating at 12-bit and 14-bit resolutions. Using the T3 PLL 256M
source divided by 4 provides the correct 64MHz clock frequency.
This change also corrects a typo in the comment from "Attack clock"
to "Set 64M GAU clock from T3 PLL 256M and reset".
Signed-off-by: William Tang <william.tang@nxp.com>
Program I2S link for DSP offload, allowing to run DSP tests using
the I2S/SSP interface. On ACE1.5 and older, no additional programming
is required, I2S link is available by default.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
When os_timer is enabled in dts, then os_timer will be used as
OS tick timer.
To make systick as the default OS tick timer, currently os_timer
is not enabled in dts. When users want to use os_timer as
OS tick timer, they need to override the dts.
Improve the method, enable the os_timer is dts, but not enable
in Kconfig by default. If need to use os_timer as OS tick, just pass
CONFIG_MCUX_OS_TIMER=y
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
It is better to let the FLEXSPI2 memory region in the final
linker file be generated from dts, in this way user/developer
can place the data in the region in code more easily.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Remove duplicated #include directives within the same
preprocessor scope across the Zephyr tree.
Duplicates inside different #ifdef branches are preserved
as they may be intentional.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The GDB is not compiled by default and a recent change in the slot manager
series contained a typo in ifdef and missed by not compiling the GDB
support.
Fixes: ebb5625bee ("intel_adsp: Add debug slot manager")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Fix build issue from the below commit:
c520b3da1a
soc: nxp: imx943: m33: add and reuse api to initialize clocks
error: soc_clock_enable defined but not used.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
If a warm reboot is issued (e.g., via mcumgr reset), the sam
controller just hangs because of loop in reboot.c. This can
be devastating if no watchdog is present to reboot the controller.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Move most of the code that is used to interface with IronSide SE on the
nRF54H20/nRF9280 from the soc/nordic directory to the hal_nordic
repository. The interface code is now provided by the new IronSide
support package. Build system code and glue code that makes use of
Zephyr APIs is now located in the modules/hal_nordic directory.
Update the directory path for IronSide SE interface code in
MAINTAINERS.yml to match the move from soc/nordic/ironside to
modules/hal_nordic/ironside.
Also included are some refactoring changes and cleanup to match the new
supporting code.
C code and Kconfigs have been renamed to *ironside_se* / *IRONSIDE_SE*
to match the supporting code changes. Users of these APIs in zephyr
have been updated to match.
Individual configurations for different "IronSide services" have been
removed as the API serialization for all of these is now provided in
a single C file / header file (ironside/se/api.h).
The ironside_boot_report_get() API has been removed. The boot report
structure can be accessed through the IRONSIDE_SE_BOOT_REPORT macro.
Most configs relating to UICR / PERIPHCONF have been moved under the
"IronSide SE" menu to make it clear that these are part of the
IronSide SE interface.
The macros that in uicr.h that were used to add entries to the
PERIPHCONF section have been removed. The supporting code now provides
PERIPHCONF_XYZ() macros that can be used to initialize structures that
go into this section, and the zephyr part now only contains a macro
UICR_PERIPHCONF_ENTRY() that is used to place an arbitrary structure
into the section. The gen_periphconf_entries.py script used to generate
PERIPHCONF entries based on devicetree has been updated to use the new
macro system.
IronSide SE integration code/configs is now guarded by HAS_IRONSIDE_SE.
Note that the UICR build system integration that relies on Sysbuild
remains under the soc/nordic directory for now, but will be moved to
the modules/hal_nordic directory once it is clear how the integration
will look there.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
This patch is a workaround to a know issue when Bluetooth and pm
is activated.
We actually need to set the tx power to the Bluetooth controller
(network coprocessor) before sending power saving request to the
coprocessor.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Power profile property doesn't need to be defined in device three.
It is a configuration value that is defined if we want pm with
Bluetooth and/or Wifi .
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The default MCXW7x platform's clock uncertainty in microseconds for
Coordinated Sampled Listening (CSL) timing synchronization in
OpenThread shall be set to 20.
Signed-off-by: Xavier Razavet <xavier.razavet@nxp.com>
Use the last configured region in the boot config for the next boot,
as opposed to a default region.
Signed-off-by: Muzaffar Ahmed <muzaffar.ahmed@silabs.com>
Currently all drivers which uses a slot from the debug window have fragile
hardwired slot 'mapping', they are locked to use specific slots even if
there are free slots available for them to take.
The new API hides the management of the slots and descriptors and users
can ask, release or even seize slots that they want to use.
Add a new debug slot manager API and a new default no config option to
allow selection between the hardwired or dynamic debug slot management.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Resize the reserved part of the debug window to cover the first 1K and
define the partial_page0 which will cover the partial slot in page 0.
Add comment to describe the debug window layout.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
The current default of 8192 will provide only 2 pages in debug window:
page0: descriptors
page1: slot0
However, the coredump is hardwired to use slot1, which by default is not
valid.
Increase the default window size to 12288 to allow three pages.
This change affects CAVS25 only as it is using default window sizes and the
window 3 is not used in this configuration at all (it was used with IPC3
only), so we do have enough space for the three page - we could even
increase the default to cover 4 pages (8192+8192), but let's be
conservative on this.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
The z_gdb_backend_init() is defined to return with success/error code
with return type of int.
Fixes: a9c47a47a4 ("intel_adsp: cavs: add gdb support")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Add required CMake directives to enable working CONFIG_SRAM_VECTOR_TABLE=y
on STM32F0 series when CONFIG_CMAKE_LINKER_GENERATOR=y.
Builds OK with both ZEPHYR_TOOLCHAIN_VARIANT undefined (uses GNU toolchain
from Zephyr SDK) and set to "iar" (uses IAR toochain from EWARM v9.70.1).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Don't quote the section names provided to Z_GENERIC_SECTION: the macro
already performs stringification on our behalf.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Remove selecting `CONFIG_HAS_HW_NRF_RADIO_IEEE802154` that should be
generated from DTS based on the SoC selection.
Signed-off-by: Michał Grochala <michal.grochala@nordicsemi.no>
RIF configuration is now done at soc init time in a centralized
way so it is no more necessary for drivers to perform this
configuration.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Perform all the IPs RIF configuration at init time in case of this
isn't yet performed by an earlier entity during the boot sequence.
This configuration depends on TRUSTED_EXECUTION_SECURE which is
currently always enabled on STM32N6x but will be configurable in
future.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Set dma tcd queue size to 4 defaultly to fix build issues,
- error: static assertion failed: NUM_DMA_BLOCKS_RX_PREP must be
< CONFIG_DMA_TCD_QUEUE_SIZE
#define BUILD_ASSERT(EXPR, MSG...) _Static_assert((EXPR),...
drivers/i2s/i2s_mcux_sai.c:45: note: in expansion of
macro BUILD_ASSERT
BUILD_ASSERT(MAX_TX_DMA_BLOCKS > NUM_DMA_BLOCKS_RX_PREP,
Signed-off-by: Biwen Li <biwen.li@nxp.com>
All power.c files in Espressif SoCs depends on un-registered
soc log module. When CONFIG_LOG=y and CONFIG_LOG_DEFAULT_LEVEL=4,
build fails as LOG_DBG used in those files won't have its proper
declaration.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The `st,stm32-ccm` is now used though the generic DTCM mechanism: remove
all SoC-specific code which was used to implement support for it.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Selecting the correct CTRLSEL value for VPR IO pins relies on
mapping any pinctrl psel value with the correct port/pin set on the
VPR nodes in devicetree to the same CTRLSEL value, to avoid enumerating
all permutations of (pin function, port, pin).
However, the mechanism did not work as intended and ended up mapping all
these pins to GPIO instead, which meant that the pins did not behave
as expected.
Update the handling so that it works as intended.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
- Enable the DTCM region in soc.c
- Apply MPU configuration for the new memory region (itcm, dtcm,
sram,...)
- Turn on the Kconfig to relocate the vector table to 0x0.
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Use CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS instead.
The new kconfig reflects more correctly on what is going on
in hardware. Also, this is not enabled by default if CPU
cache is not coherent. CPU cache can be incoherent and yet
there are no mirrored memory regions. Those relying on this
deprecated default behavior has their config adding
CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS separately.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
