Add code to clock and release reset signal for USBOTG controller on
RW6xx SOC when USB is enabled, and add KConfig selection to indicate to
build system which USB controller this SOC uses.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
IPC has inverted the usage of the state lock API.
In this API semantics, the get method disallow the policy of
using the given state, while the put() release this constraint.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Fix the inline documentation to match implementation. As IPFL is used,
the correct matching function is xthal_icache_region_lock().
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Fix the inline documentation to match implementation. As IPFL is used,
the correct matching function is xthal_icache_region_lock().
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Nordic SoCs use this hook to execute `SystemInit` as early as possible
after ARM core reset. Previously, `z_arm_platform_init` was defined as
assembly code, which would simply jump to the other function.
However, this extra code can be avoided by using `SystemInit` directly
in place of the `z_arm_platform_init` symbol (whenever it's undefined).
This is now done with a linker script containing a `PROVIDE` directive.
This saves 4 bytes of ROM (0-16 depending on alignment) and also makes
it possible to override `z_arm_platform_init` out of tree, if needed.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
We need to use correct SOC name when naming the Kconfig.defconfig*
files.
So we need the following changes:
- mimx8mp -> mimx8ml8
- mimx8mm -> imx8mm6
- mimx8mn -> mimx8mn6
- mimx8mq -> mimx8mq6
Then we also need to take care of qualifiers name. Standard notation
uses "_" instead of "."
e.g : Kconfig.defconfig.mimx8mp.a53 -> Kconfig.defconfig.mimx8ml8_a53
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Checking if the device state is locked is not correct, device runtime
put / get is no longer checking for it and the only place that was
locking device's state was the pm action callback and if the idea
was to protect some concurrent call, using it is not enough.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
There is no needed to lock/unlock a device state in its pm action
callback. The power management subsystem should take care of
serialize these calls.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Prevent the system from entering runtime idle state during IPC
transactions until the HOST acknowledgment is received.
This patch modifies the IPC mechanism to:
- Lock the runtime idle state immediately after sending an IPC message
to the HOST, preventing the system from entering a low-power state.
- Unlock the runtime idle state once the IPC transaction is acknowledged
by the HOST, allowing the system to enter low-power states if
conditions permit.
The changes ensure that the DSP does not enter a power state that could
interrupt the IPC communication process, maintaining the integrity of
the IPC state machine.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit enables pinctrl on i.MX8ULP. This includes:
1) Adding `pinctrl_soc.h` header file.
2) Adding DTS node for IOMUXC1, which is one of the
IPs responsible for managing the 8ULP pads.
3) Adding .dtsi with pin definitions. For now, only
the LPUART7 pads are added to this file because this
is going to be the only consummer for now.
4) Modifying the `pinctrl_imx.c` driver to work for 8ULP.
5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a
dependency of `CONFIG_PINCTRL_IMX`.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.
- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.
- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.
- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add simplistic booting method which allows to run
applications without the 2nd stage bootloader.
- introduce memory layout header file
- update and optimize default and mcuboot linker scripts
- remove building multiple binaries during the application build
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add simplistic booting method which allows to load without 2nd stage
bootloader.
Update common architecture loader to support all build scenarios.
- simple boot: using single binary application without bootloader
- mcuboot: zephyr port of MCUboot
- application: loaded by the MCUboot
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit removes the `Kconfig.core` file. It's been largely unused, and
the only symbol it provides (`RISCV_CORE_E31`) overlaps with the SoC-layer
provided `SOC_SERIES_SIFIVE_FREEDOM_FE300`.
As of date, the only SoC that uses the E31 core in Zephyr is the FE310 SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
DMASEC is set to non-secure by default, which prevents CCM from
accessing secure memory. Change DMASEC to secure.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The soc_secure_* function are used by the non-secure application
to access hardware resources which are mapped as secure.
Using these functions for hardware resources mapped as non-secure
is missleading.
We have some soc_secure_* functions which read FICR values.
In nRF91 and nRF53 platforms this made sense since FICR
has hardware fixed mapping as secure.
For nRF54 though the FICR has hardware fixed mapping as non-secure.
This change refactors the soc_secure.h to exclude the functions
which read FICR values from being included when FICR is mapped as
non-secure.
Also updates the hwinfo and ieee802154 drivers to adjust to this change.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
In preparation for adding AMP support for i.MX RT6xx family we need
to rename existing cm33 support files to more specific names.
e.g mimxrt685_evk.dts -> mimxrt685_evk_mimxrt685s_cm33.dts
This will allow us to later add support for Cadence DSP found on i.MX
RT6xx series.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
imxrt6xx are dual core devices featuring an ARM Cortex-M33
core and an Cadence Xtensa HIFI4 Audio DSP.
Currently only m33 core is supported. In order to support
the Cadence DSP we need first to do some code-reorganization
for m33.
We start by moving all cm33 related code to its own directory
and introduce the cpuclusters property in soc.yml file.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Clarify usage of __rom_region_end/size in XIP system.
When PMP is enabled, __rom_region_end should be padded to meet the
requirement of PMP entry, and the actual ROM region usage ends at
.last_section instead of __rom_region_end.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Updated ROM region padding to utilize LMA instead of location counter,
because the location counter has been assigned to 'RAM_BASE'.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
LPFlexcomm is a MFD device hence select this Kconfig whenever
it is enabled.
Remove the selection from the individual driver Kconfig files.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Change, for audio DSP and M7 cores, SOC_<name> to match
the exact soc name.
Update the board files accordingly.
These configs are used in SOF and NXP_HAL, so change
sha for these modules.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Enable sleep mode on LPC55S69 (corresponding to zephyr's runtime idle
mode). Add DT description and power api implementations.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Timing function need Cycle Count Register CYCCNT of DWT,
but Arm-Cortex-M23 only support DWT_CTRL, DWT_PCSR and DWT_COMP
& DWT_FUNCTION registers. It can't meet the requirement of timing
function, so to remove CPU_CORTEX_M_HAS_DWT.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
During the migration to Hw model V2 the PR #63495
was not fully reported.
This change is adding the support Serial Wire / JTAG port pins
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes the following errors when sparse (SCA) is enabled:
soc/intel/intel_adsp/ace/power.c:46:12: warning:
cast removes address space '__cache' of expression
/soc/intel/intel_adsp/ace/power.c:48:9: warning:
incorrect type in argument 1 (different address spaces)
Fixes#70725
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Select the LPTIM clock source STM32_LPTIM_CLOCK to be
LSE or LSI depending on the DTS clocks property
of the stm32_lp_tick_source node.
This will also affect the SYS_CLOCK_TICKS_PER_SEC
depending on the lptim prescaler
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add SoC initialization to set the UART RDC permission in the early
phase, so that the it can be used by Zephyr on Cortex-A cores.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
To minimize time the CPU spends when preparing for sleep, make sure
the pending transactions are finished before calling `wfi`.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
The SOC name `imx8ulp` has been just a placeholder until
support for the SOC's ADSP (since this is the only core
that's supported in Zephyr) could be added to the NXP HAL.
Now that the support has been added, to make use of it, the
SOC name `imx8ulp` has to be changed to `mimx8ud7`. As such,
this commit does the following:
1) Introduces SOC part number configuration - needed
by some HAL headers.
2) Replaces all occurrences of `imx8ulp` (as the SOC
name) with `mimx8ud7`.
3) Enables `CONFIG_HAS_MCUX`.
4) Aligns all `CONFIG_SOC_` configurations with the
new SOC name.
5) Updates SOF hash. This is needed to fix build issues
caused by this name change. This is not done in a separate
commit to preserve bisectability.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
