There is a typo in the part number list for LPC55S69. The
LPC55S69JET98 should be LPC55S69JEV98.
Fixes#80541
Signed-off-by: David Leach <david.leach@nxp.com>
Larger image partitions require more space in DRAM due to
the increase in .bss.sector_buffers.
Each sector in .bss.sector_buffers consumes 16 bytes.
In the worst case scenario, such as with the ESP32S3 N32R8V,
which has 32 MB of flash and most likely 12 MB image partition,
an addition of 0xc000 should be sufficient to accommodate this.
Signed-off-by: Nik Schewtschuk <nikita.schewtschuk@smartmechatronics.de>
- Update GDMA and ADC drivers and remove deprecated entries.
- Rebased hal_espressif to latest bump sync.
- Added ESP Timer and Radio common config values
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Make sure all kconfig related to Wi-Fi is
in its driver area.
This commit also removes esp_timer_init() call
from Wi-Fi driver.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Files renaming done to better isolate zephyr related
functions from stm32 hal related functions
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
Make the SMPS_MODE define visible from drivers by moving it to soc.h
This define is for example used by the ADC driver to determine if sampling
should be synchronized with the SMPS clock.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
What is changed?
- Added a new mps3 board an555 for the soc corstone310.
The qualifier to build/run application with board mps3/an555 is
`mps3/corstone310/an555` for secure and
`mps3/corstone310/an555/ns` for non-secure.
- Added FVP variant to enable FVP testing with corstone310
and it uses the ARM FVP `FVP_Corstone_SSE-310`.
The qualifier to build/run application with FVP is
`mps3/corstone310/an555fvp` for secure and
`mps3/corstone310/an555fvp/ns` for non-secure.
Why do we need this change?
- This enables FVP support and testing for corstone310.
- A separate FVP variant was added for AN555 because, the TFM board
used for non-secure variant differs for FPGA and FVP.
TFM board `arm/mps3/corstone310/an555` should be used when testing
AN555 with FVP and `arm/mps3/corstone310/fvp` should be used when
testing with AN555 FPGA.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
What is changed?
- Added a new mps3 board an552 for the soc corstone300.
The qualifier to build/run application with board mps3/an552 is
`mps3/corstone300/an552` for secure and
`mps3/corstone300/an552/ns` for non-secure.
- Added FVP variant to enable FVP testing with corstone300
and it uses the ARM FVP `FVP_Corstone_SSE-300_Ethos-U55`.
The qualifier to build/run application with FVP is
`mps3/corstone300/fvp` for secure and
`mps3/corstone300/fvp/ns` for non-secure.
- Note: the qualifier to build/run application with board mps3/an547
is now changed to
`mps3/corstone300/an547` for secure and
`mps3/corstone300/an547/ns` for non-secure.
How is it changed?
- Moved common code from mps3/an547 to corstone300.
- Renamed soc for an547 to corstone300 and added
a new soc corstone300/an552.
Why do we need this change?
- This enables FVP support and testing for corstone300.
- SOC/qualifier for mps3/an547 was renamed to reduce code redundancy
- A separate FVP variant was added for AN552 because, the TFM board
used for non-secure variant differs for FPGA and FVP.
TFM board `arm/mps3/corstone300/fvp` should be used when testing
AN552 with FVP and `arm/mps3/corstone300/an552` should be used when
testing with AN552 FPGA.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The current selected start-up time takes 8 seconds to initialize.
When xosc32 is used as main clock reference it blocks the whole
initializarion of the system by that amount of time. This patch
relax that condition setting the initialization time to 62ms.
Fixes#79949
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Only initialize the HFXO Manager HAL driver if the HFXO is enabled in
DeviceTree, the device uses SYSRTC for timekeeping, and Power Manager
is enabled. HFXO Manager integrates with the Sleeptimer HAL driver for
SYSRTC to autonomously wake the HFXO prior to Sleeptimer wakeup from
deep sleep. It is not needed on devices that don't have HFXO-SYSRTC
integration, and it is not needed if the application doesn't use deep
sleep.
Add missing call to init_hardware() prior to init().
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Rework Nordic specific S2RAM marking procedures.
The S2RAM marking procedures must not disrupt the stack due to
the TLS pointer not yet being initialized during their execution.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Instead of fixing csi2rx clock frequencies, set them according to the
pixel rate got from the camera sensor.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
HAS_SEGGER_RTT Kconfix symbol is missing in NXP MCXC series Kconfig.
Add the symbol to fix and enable Segger RTT samples.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Power Manager no longer requires the Counter driver. This seems to have
been a hack to get the Sleeptimer HAL included in the build, as the
Sleeptimer is the real dependency of the Silabs Power Manager HAL.
Since Sleeptimer is now used for the OS timer, this hack is not needed.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add OS timer implementation making use of the Sleeptimer HAL.
Sleeptimer integrates tightly with the Silabs Power Manager HAL,
and must be used as the OS timer to achieve optimal power consumption
when using the radio.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add a pinctrl driver for Microchip MEC5 HAL based chips.
The driver removes the YAML enum "no change" property
value from the driver strength and slew rate properties.
Update the shared header file in mec soc common folder to
use a different Z_PINCTRL_STATE_PINCFG_INIT for MEC5.
Modifications to legacy MEC172x XEC PINCTRL will be in
a future PR.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
CMSIS SystemInit is not used in Zephyr. Implement the functionality
that isn't already done by Zephyr startup using soc_prep_hook().
The reason the lack of TrustZone init did not create immediately obvious
issues previously is that SMU faults can only happen if the SMU clock is
enabled.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Bandgap voltage is used for on die temperature measurement. Bandgap
buffer has to be enabled explicitly to get correct tempearature.
Enable the buffer if TEMP_KINETIS is selected.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
The previous changes in
https://github.com/zephyrproject-rtos/zephyr/pull/74304
assumed that because this is also handled in
`bt_hci_transport_setup` that it shouldn't be done on
initialisation too.
However, if someone wants to develop their own app which
uses BT and also wants to enable the CPUNET by default this
KConfig should be available to them.
Signed-off-by: Sean Madigan <sean.madigan@nordicsemi.no>
Andes AE350 integrates 2 PLICs in the platfrom, one for external interrupt
and another for IPI. Adusted Kconfig for total IRQ numbers and support 2
aggregators in the 2nd level interrupt controller.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The rom_mpu_padding section is incorrect NAPOT padding for the address of
__rodata_region_end when ROM_BASE is not 0x0, because __rom_region_start
is set to the offset of rom_start section.
Fixed this by use "__rom_region_start = ABSOLUTE(.);" to keep both
__rodata_region_end and __rom_region_start are absolute address.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Add PCI device IDs for common Intel Raptor Lake variants and Alder Lake N.
These all have cAVS2.5 audio DSP.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Numerically sort the PCI DIDs for cAVS2.5 hardware. This follows
the convention in e.g. Linux and coreboot and eases maintainance. No
functional change.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The "Detected cAVS 1.8+ hardware" message is misleading as it implies
some version of Intel cAVS hardware has been found, while in fact this
script supports also other types of hardware, including Intel ACE.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Clean up code documentation to drop references to platforms no longer
supported in the code. Continues the cleanup started in commit
086e4f84ed ("intel_adsp: cavstool: Remove
legacy code").
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The default configuration for PINCTRL should not be set with
the other default configurations in .defconfig, instead select
a default value as part of defining the UART driver.
Signed-off-by: Andrew Davis <afd@ti.com>
Add initial SoC support for the TI J721E SoC series Cortex-R5 core.
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Signed-off-by: Andrew Davis <afd@ti.com>
The commit introduced regression for hsdk4xd platform.
The hsdk4xd SoC setup from soc_early_asm_init_percpu need to be done
in early code before any C code execution.
The current approach has multiple issues
- we call function (which can be easily implemented in C for
this or other SoC) from the place where we haven't setup stack
pointer (so we can't use stack) - which is very error-prone
- we never return back from soc_reset_hook on hsdk4xd platform
So let's just revert it for now. If any other ARC SoC need to use
soc_reset_hook - than it can be implemented properly.
This reverts commit 8c32a82e47.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Series 2 always uses the device init HAL, while Series 0/1 never do.
Create a separate soc.c for Series 2 to make both versions easier to read.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Swap from the deprecated device_init_* functions to clock manager
for clock tree configuration. Populate config headers using
device tree representation of clock tree and oscillator config.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Switch EFR32MG21 to use the device init HAL. This makes the init sequence
the same as the rest of Series 2.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
On Series 2, set the SYS_CLOCK_HW_CYCLES_PER_SEC Kconfig option from
DeviceTree, rather than separately configuring it in board-level
defconfig.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
