Rework the Intel Audio DSP host IPC service backend to use the generic
ipc_service data/len conventions and the new critical send and buffer
management APIs.
Replace the backend-specific intel_adsp_ipc_msg and related enums with a
simple two-word payload passed through the standard ipc_service_send()
and ipc_service_send_critical() interfaces, and adapt the ISR and
receive callback to operate on this representation.
Use ipc_service_get_tx_buffer_size() as a readiness check for the host
channel and provide hold_rx_buffer() / release_rx_buffer()
implementations so ipc_service_release_rx_buffer() can be used to signal
when the channel becomes available again.
Wire the emergency send path through send_critical() to route urgent
messages via the backend's emergency fast path while keeping the normal
IPC flow unchanged.
Move the synchronous IPC wait logic out of the Intel Audio DSP host IPC
backend and into the common intel_adsp_ipc helper used by tests.
Update intel_adsp_ipc_send_message_sync() to both send the IPC message
through ipc_service_send() and wait on the backend semaphore, and remove
the now redundant ipc_send_message_sync() helper from the host IPC
backend.
Document that intel_adsp_ipc_send_message_sync() is a test-only helper,
not used by SOF firmware, and that it is a candidate for future removal
or for replacement by an explicit synchronous send primitive in the
generic IPC service API or in application code.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
5 years ago LiteX switched to 32 bit csr data width,
while the option is still available in litex, it doesn't really
work there, even if it can be build, the bios f.e. won't boot.
already described in https://github.com/enjoy-digital/litex/issues/1062
So it is currently only here for designs, that are older than
5 years and for fpgas, where also the fpga bitstream can be updated
it is time to remove the support and require the users, when they wan't
to update zephyr, that they also have to update their fpga bitstream.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
RTT need to use RAM which is not cacheable as RTT does not support
data cache. Using cpuapp TCM RAM memory section for RTT.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add MCUX_OS_TIMER configuration with CPU_FREQ-based default selection.
Update CORTEX_M_SYSTICK to be disabled when either LPTMR or OSTIMER
is selected as the system timer, ensuring only one timer is active.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add initial support for the Allwinner H3 SoC, commonly
found in development boards like the Orange Pi series.
This commit introduces the intial SoC support files:
- Basic Kconfig configuration and SoC definition
- MMU region setup for memory management
- SoC-specific headers and device tree source include
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
This disables the kconfigs to build the reset vector and crt1
startup code from the architecture layer as ACE has its own
rom_entry() as entry point.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The idle enter was being traced but idle exit was not.
This change adds the missing call to sys_trace_idle_exit()
to the idle exit path for the it51xxx and it8xxx2 SoCs.
Signed-off-by: Rob Barnes <robbarnes@google.com>
Add the memory-regions property to mac in stm32h7rs.dtsi,
same as in stm32h7.dtsi, and set sram2 as default. Also add
the #memory-region-cells to sram2 and sram1 nodes.
Override the sram2 as default with sram1 in stm32h7s3.dtsi and
stm32h7s3.dtsi since sram2 is disabled per default.
Add the same checks as for h7 series to mpu_regions.c and sections.c.
Signed-off-by: Benjamin Klaric <benjamin.klaric01@gmail.com>
Use the memory-regions property in stm32h7.dtsi to explicitly locate
ethernet buffer and descriptor to an sram region. Set sram2 as default
and override with sram3 when available, in soc level .dtsi files.
Add #memory-region-cells to sram2 and sram3 nodes in specific .dtsi
files in dts/arm/st/h7, since it is needed by the memory-regions
property.
Add a check for memory-regions before the check and definition of the
sram_eth_node in mpu_regions.c and sections.ld.
Signed-off-by: Benjamin Klaric <benjamin.klaric01@gmail.com>
The binary-info feature that introduced in #54290 causing trouble
with some rp2xxx variant boards.
Turning off this feature defaultly to solve these problems.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The LCD_CAM peripheral is a parallel I/O controller integrated in the ESP32
series. It consists of an LCD output module and a DVP camera input module.
The camera side is already supported in Zephyr as a video driver.
This commit adds support for the LCD module by implementing it as a
MIPI-DBI backend. The LCD_CAM supports multiple output formats, and the
initial implementation provides I8080 mode.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Move the shared pinctrl and clock initialization for the LCD_CAM peripheral
from the ESP32 DVP driver into a new SoC-level implementation.
Update the ESP32-S3 DTS to reflect the new structure by introducing an
`lcd_cam_dvp` child node under the common `lcd_cam` parent node.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
The goal is to slowly convert all Microchip MEC to in-tree drivers
and support code (no HAL). We had partial HAL support for MEC172x
as the mech172x folder. We are removing HAL based mech172x since HAL
will be deprecated in the future and it has no board support.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
GPIO hardware in Microchip MEC parts is the same except for the MUX
field (number of alternate functions). We modify the old XEC PINCTRL
driver to work on all MEC parts and also be independent of HAL and
CMSIS register structures. During development we found a DT issue
with DT_ENUM_IDX_OR always inserting the default value. Worked around
by converting slew rate and drive strength to YAML integer type and
created defines for the values in the dt-bindings header.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Updated the MMU region entries for the GIC device to use
MT_DEFAULT_SECURE_STATE instead of MT_NS,
aligning the security attribute with the default secure sate macro.
Signed-off-by: Niu Zhihong <zhihong@nzhnb.com>
Binary Info embeds program meta information in flash,
which can be viewed with RaspberryPi Pico's `picotool`.
Metadata is automatically collected from pinctrl.
It can be override by the Kconfig configurations, such as
```
CONFIG_RPI_PICO_BINARY_INFO_OVERRIDE_PROGRAM_NAME="my program name"
```
When this feature is enabled, pinctrl groups are restricted to
consisting of pins with a single rpi_pico function.
In other words, SPI's MISO and MOSI can be in the same group,
but I2C's SDA cannot be included in this group.
This is rarely an issue in normal use,
and can be resolved by dividing them into separate groups.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Since e150ffb92c, Zephyr only really
supports native_simulator based targets when building native/posix
arch based targets.
So this comment is not relevant anymore. Let's remove it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Fix the Kconfig dependency for CYW20829 so that enabling the
low-power system timer automatically disables the Cortext-M SysTick
Signed-off-by: Merin George <merin.george@infineon.com>
Add initial support for the Elan em32f967 SoC based on ARM Cortex-M4.
Minimal SoC definition for upstream:
- soc.h, Kconfig, and CMakeLists.txt provided for completeness
- This PR does not implement drivers or UART functionality
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
NO_POSIX_CHEATS was a macro used to avoid including the content of a
header (`posix_cheats.h`) which allowed building applications in the
POSIX architecture without the native simulator, avoiding collisions
between some embedded symbols and those from the host C library.
Support for this way of building, and this header and macro were
removed in e150ffb92c, but these users
were forgotten. This was harmless, but let's just clean it up now.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add macro definitions to map generic ADC instance names to hardware
specific SARADC base addresses, enabling driver portability.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
Add API for indicating that a deterministic interrupt will occur at
certain point in time in the future. Implementation is ensuring that
there will be no latency due to NVM memory waking up. There are 2
ways of ensuring that:
- setting low latency power mode in RRAMC (higher power consumption
in idle (not available in non-secure build)
- using PPI and GRTC to trigger the RRAMC wake up task right before
an expected interrupt
Module has a pool of GRTC channels and dynamically allocates and
frees those channels when events are registered and unregistered.
If GRTC channel is not available then algorithm falls back to power
mode setting (in secure build).
API offers registering an event using relative and absolute timing.
API can be used from Zero Latency interrupts.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Adjust the pin function bitfield to 4 bits to fit all RZ/V SoCs
(RZ/V2L, V2H, V2N). PFC bitfield of RZ/VH, V2N have 4 bits, so
the current 3-bit width does not fit them.
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Add the SOC_IT8XXX2_RAM_CODE_NOINLINE Kconfig option to prevent
functions marked with __soc_ram_code from being inlined when LTO
is enabled.
This ensures RAM code functions remain in the RAM section instead of
being merged into callers by the compiler.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit enables multi level interrupts:
- Enable multi level interrupts
imx943 is a two level interrupts system and
some interrupts(eg. edma interrupts) depend on irqsteer.
- Increase irq number from 405 to 790
Actually there are 407(IRQ 0 ~ IRQ 406) interrupts
from nvic(first level interrupts),
The second level interrupts are extended by irqsteer,
it extends 32 x 12 = 384 interrupts,
So first level interrupts + second level interrupts
= 407 + 384 = 791(IRQ 0 ~ IRQ 790) interrupts
Signed-off-by: Biwen Li <biwen.li@nxp.com>
S32K566 is a member of the S32K5 family which expands
s32k3 series to higher performance and larger memory.
Zephyr port for S32K5 will support cortex-M7 and cortex-R52
After reset, swt_startup is enabled and starts running,
disable it using the watchdog hook.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Perform call to LL_DBGMCU_{Dis,En}ableDBGStandbyMode() for STM32WBA series
in the common code, as done with other series. While at it, also add
missing call to LL_DBGMCU_{Dis,En}ableDBGStopMode().
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Update system clock related variables
otherwise Cy_SysLib_Delay or Cy_SysLib_DelayUs are incorrect
Signed-off-by: Kevin Chan <kevin.chan3@infineon.com>
Enabled modes:
idle: SLEEP
suspend: DEEP-SLEEP
standby: POWER-DOWN with CPU retention
OS Time Base: OSTIMER with 32K clock source
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
