Commit graph zephyr/soc
Author SHA1 Message Date
Tony Han
9810eecad9 soc: microchip: sam: sama7: some optimize in Kconfig and CMakeLists.txt
Select MMU and CACHE_MANAGEMENT in 'config SOC_FAMILY_MICROCHIP_SAMA7'.
Replace 'config' with 'configdefault' for items in defconfig file.
Remove duplicated linker script in CMakeLists.txt in sama7d6 and sama7g5
directories, use the one in sama7 directory.

Signed-off-by: Tony Han <tony.han@microchip.com>
2025-12-02 11:24:28 +01:00
Tony Han
f703c2ee09 soc: microchip: sam: sama7: add sama7g54 (System-in-Package) SIP SoCs
Add SAMA7G5 series System-in-Package (SiP) MPUs to Kconfig.soc and
soc.yml, update the header files for them too.

Signed-off-by: Tony Han <tony.han@microchip.com>
2025-12-02 11:24:28 +01:00
Tony Han
0a9d1493a8 soc: microchip: sam: reorganize directory structure for sama7g5 series
Update directory structure to the following hierarchy for MPU devices:
  Product Architecture
    |__ SOC Series
          |__ Product Group
Move directory 'soc/microchip/sama7g5/' into 'soc/microchip/sama7/'.
Add sama7g5 to 'soc/microchip/sam/sama7/soc.yml'.
Remove the files under soc/microchip/sam due to they became useless
with the reorganization.

Signed-off-by: Tony Han <tony.han@microchip.com>
2025-12-02 11:24:28 +01:00
Arnaud Pouliquen
cfe2d71e24 soc: st: stm32mp13: fix KERNEL_DIRECT_MAP config usage
Fix config dependency between MMU KERNEL_VM_SUPPORT and KERNEL_DIRECT_MAP

This fix following build issue:

warning: KERNEL_DIRECT_MAP (defined at kernel/Kconfig.vm:83) has direct
dependencies MMU && KERNEL_VM_SUPPORT with value n, but is currently
being y-selected by the following symbols:
 - SOC_SERIES_STM32MP13X (defined at soc/st/stm32/stm32mp13x/Kconfig.soc:6,
   soc/st/stm32/stm32mp13x/Kconfig:6), with value y, direct dependencies y
   (value: y), and select condition SOC_FAMILY_STM32 (value: y)

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
2025-12-01 12:25:16 -05:00
Ville Kujala
8883febbcf boards: nrf9280pdk: Merge cpuapp iron variant into the base variant
Replaces the legacy SDFW compatible board configuration with the
IronSide SE compatible one, thus removing support for running samples
and tests on nRF9280 devices with the old firmware.

Signed-off-by: Ville Kujala <ville.kujala@nordicsemi.no>
2025-12-01 12:24:42 -05:00
Jacky Lee
a29797d264 soc: egis_et171: add customize config value of fw size info
Allows applications to customize the firmware size information
for binary header optionally.

Signed-off-by: Jacky Lee <jacky.lee@egistec.com>
2025-12-01 12:22:44 -05:00
Ivan Pankratov
0aa208d51e dts: bluetooth: add base binding for BLE radio hardware capabilities
Create a shared base binding (ble-radio.yaml) for common Bluetooth LE
radio hardware capabilities to avoid duplication between vendors and
ensure consistent property naming across the ecosystem.

Properties are prefixed with 'ble-' and ordered chronologically by
Bluetooth Core Specification version (5.0, 5.1, 6.0). Each property
indicates a hardware capability, not current enablement state.

Signed-off-by: Ivan Pankratov <ivan.pankratov@silabs.com>
2025-12-01 12:22:33 -05:00
Martin Hoff
b78fe9f1aa drivers: power_domain: siwx91x: fix the link between pd and cpu state
This patch is needed to block the pm_state "PM_STATE_SUSPEND_TO_IDLE"
when a device on the power domain (actually all the peripherals) is
active. Without this patch, cpu can decide to go to deep sleep while
a peripheral is active.

Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
2025-12-01 11:11:23 +01:00
Aksel Skauge Mellbye
a83b19b3f9 soc: silabs: Fix clock control dependency declarations
Most drivers for Series 2 depend on clock control, but didn't
declare it. Enable clock control by default for Series 2 SoCs.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2025-12-01 11:11:14 +01:00
Martin Hoff
29fb893bab soc: silabs: siwx91x: removed sscanf for nwp firmware version check
This patch removes the use of sscanf to maintain compatibility with
tests that use the minimal cpp library. The expected version is now
defined using multiple individual values rather than a single
formatted string.

Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
2025-12-01 11:08:51 +01:00
Dmitrii Sharshakov
e3ef835ffe soc: raspberrypi: rp2350: imply XIP
Imply XIP from the SoC config to make XIP the default to match the
behaviour between Cortex-M33 and Hazard3 variants.

This fixes cbe6a716d3, which stopped
selecting XIP at the SoC level.

Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
2025-11-28 20:58:32 -05:00
Haoran Jiang
40accad696 soc: sifli: sf32: Add SF32LB52 platform ftab generation
Using the `gen_ftab.py` script, we can retrieve the current image
distribution information from the device tree and generate the
corresponding `ftab.bin` file. This eliminates the need to burn an
additional `ftab.bin` externally before running the device

Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
2025-11-28 17:25:27 +00:00
Thomas Decker
2fbefdbc53 soc: st: stm32: h7rsxx: Fix MPU region for read-only id flash region
Set correct MPU memory type and size for the uniqe device id, package code
and ADC VREF/TS calibration read-only flash region.

REGION_IO_ATTR configures the MPU region to device-memory with RW access,
which is also used for the PERIPH region. To avoid complicating things
unnecessarily, we use this type instead of defining a new device-RO.

The size is reduced to 512 bytes, because RM0477 table 28 and chapter
5.3.12 state that this read-only flash area has a size of 512 bytes.

Signed-off-by: Thomas Decker <decker@jb-lighting.de>
2025-11-28 10:11:57 +00:00
Guillaume Gautier
3206d73994 soc: st: stm32: add timer shared interrupts
For some STM32 series, some interrupts are shared between different timer
instances. Use the SHARED_INTERRUPTS for these series so that all timers
can be used at the same time.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-11-27 21:54:24 +01:00
Mathieu Choplain
7defeda8bd soc: st: stm32: wkup_pins: break after configuring I/O retention on pin
After we found the target GPIO port and configured I/O retention on target
wake-up pin, break from the search loop.

Applies only to STM32WBA series.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-11-27 16:02:47 +01:00
Arunmani Alagarsamy
1814b902a9 soc: silabs: siwg917: Add configurable boot features via DTS and Kconfig
Add support for configuring hardware-specific boot feature bitmaps
through Devicetree and software-specific boot configurations through
Kconfig options.

Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
2025-11-27 14:48:35 +01:00
Sebastian Bøe
a053b97144 soc: ironside: counter_service: 2 compilation errors fixed
2 compilation errors fixed in counter service.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2025-11-27 13:47:58 +00:00
Aksel Skauge Mellbye
eabde5b278 soc: silabs: Add xg24 variants
Add support for more SoC variants for xG24.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2025-11-27 14:45:47 +01:00
Nikodem Kastelik
ad1e5ac253 nordic: update and align to nrfx 4.0.1
New nrfx release contains major rework of nrfx drivers
instantiation making it easier to integrate with dts nodes.
Now, nrfx driver instances can no longer be `const`
because they contain driver runtime state.
Additionally, all nrfx drivers return `errno` error codes
instead of deprecated `nrfx_err_t`.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2025-11-27 14:45:17 +01:00
Francois Ramu
b4cdb239c8 soc: st: stm32u5 set backup sram retention if regulator is LDO
On the stm32u5 series, this commit will enable backup sram regulator
when the regulator is LDO, during SOC init. Then stm32_backup_sram_init
does not change the backup SRAM retention anymore.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-11-27 11:33:40 +01:00
Khoa Tran
8a86e9bbf9 soc: renesas: ra: Add support for Renesas RA4T1 SoC series
Add support for Renesas RA4T1 SoC series

Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
2025-11-27 11:30:12 +01:00
Sebastian Bøe
e0ad51e375 soc: nordic: gen_uicr: Enable IS_GEN_UICR_IMAGE by default
Enable IS_GEN_UICR_IMAGE by default for the gen_uicr image.

A recent change accidentally made this default n, and broke a bunch of
users.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2025-11-26 11:08:09 +00:00
Mihira Madhava Bollapragada
adf1c8c693 drivers: intc: change the VIM kconfig to TI_VIM
VIM is a vector interrupt manager that TI devices have and is used a
interrupt controller. the driver's Kconfig selection is created as "VIM"
and is resulting in the confusion with a Text Editor name.

Make the VIM Kconfig option to indicate the vendor TI name in it.

Signed-off-by: Mihira Madhava Bollapragada <madhava@ti.com>
2025-11-26 07:10:13 +00:00
Bill Waters
e787380ec8 soc: infineon: edge: pse84: slot size
Increase the slot size for secure applications to
support testing applications that require more than
the default size of 0x20000

Signed-off-by: Bill Waters <bill.waters@infineon.com>
2025-11-25 20:22:45 -05:00
Chris Wilson
5220936bbc soc: st: stm32: add '-align' flag for signing tool v2.21.0+
Starting in v2.21.0, the STM32 signing tool ('STM32_SigningTool_CLI')
stopped automatically adding padding bytes at the beginning of the
payload to align it to the 0x400 offset. To restore this behavior, the
'-align' flag must be passed to the signing tool post-build command.

This commit checks for signing tool version v2.21.0 or higher and
appends the '-align' flag to the post-build signing command. It also
changes local CMake variable names to lower case and corrects some
indentation issues.

Fixes zephyrproject-rtos/zephyr#99456

Signed-off-by: Chris Wilson <chris@binho.io>
2025-11-25 21:13:29 +00:00
Marek Matej
b4ee630506 soc: espressif: esp32c6: set early init stack
Early init stack pointer can interfere with bss segments if grown
enought, therefore stack pointer is set to safe area before starting
init.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-11-25 19:24:57 +00:00
Martin Hoff
87ab3e337a soc: silabs: siwx91x: introduce zero latency irq
The HAL used by the SiWx91x SoC implements a mechanism to protect
atomic sections. Since this HAL also supports a zero-latency
interrupt (ZLI) mechanism, we need to ensure the same number of
bits are used for ZLI interrupts.
The interrupt priority level (2) depends on a hardcoded value in the
Simplicity SDK (CORE_ATOMIC_BASE_PRIORITY_LEVEL).
Without this fix, arch_irq_lock (which sets the BASEPRI register to
0x4 when zero-latency interrupts are not enabled) is overridden by
CORE_EnterAtomic in the HAL, which sets BASEPRI to 0xC since the HAL
does not use the BASEPRI_MAX function. IRQ might then fires since it's
register with a lowest priority in Zephyr.

Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
2025-11-25 17:39:13 +00:00
Bjarki Arge Andreasen
034d3d3325 nordic: nrf54h: bicr: allow for custom bicr.json in application
Allow placing a custom bicr.json file in the application source
folder which will be used instead of the default one in the
boards folder. Also allows setting a custom name to use for the
file so multiple files can be placed in either boards or app dirs
and selected with Kconfig (prj.conf or <board>.conf)

The following will take precedence over the bicr.json file in the
board folder:

- <app>/bicr.json
- <app>/bicr_foo.json + CONFIG_SOC_NRF54H20_BICR_NAME="bicr_foo.json"

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2025-11-25 17:35:23 +00:00
Sebastian Bøe
f324a1540f soc: nordic: ironside: Add counter service
Add counter service.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2025-11-25 16:06:00 +00:00
Gang He
6437340bf3 soc: sifli: sf32: Add configuration for Bluetooth HCI driver support
Add configuration support for Bluetooth HCI driver.

Signed-off-by: Gang He <ganghe@sifli.com>
2025-11-25 16:05:02 +00:00
Albort Xue
8885c708bf soc: nxp: mcx: mcxw7xx: Update power management in case of NBU is used.
Added conditional compilication for 'power_state_set' function. The
changes ensure that mode of NBU domain is manually set only when
the NBU is not used. If NBU is enabled, the mode of NBU domain is
auto updated by software run on NBU.

Change include:
- Conditional checks around the NBU mode in sleep and deep sleep mode.

Signed-off-by: Albort Xue <yao.xue@nxp.com>
2025-11-25 13:03:49 +01:00
S Swetha
bf093f939e soc: intel: wildcat_lake: Add soc support for WCL
This commit introduces SOC support for
Wildcat Lake.

Signed-off-by: S Swetha <s.swetha@intel.com>
2025-11-24 21:15:21 +01:00
Adrian Bonislawski
af974c3074 soc: intel_adsp: ace: add IMR info registers
Adds devicetree nodes for IMR (Isolated Memory Regions)
information registers across all ACE platforms.
These registers provide information about the IMR memory region,
such as whether it is in use and its size.

Implements structures and utility functions to access
these registers and retrieve IMR information programmatically.
This allows dynamic detection of IMR availability and its size at runtime,
instead of relying on hardcoded values.

Removes the hardcoded IMR_L3_HEAP_SIZE definition since the size can now be
determined dynamically using the newly added ace_imr_get_mem_size() func.

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2025-11-24 14:58:27 -05:00
Adrian Bonislawski
35a1e62035 soc: intel_adsp: ace40: extend hwreg1 MMU mapping
This patch will extend MMU mapping range for hwreg1 entry
because it is required to access lower register addresses

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2025-11-24 14:58:27 -05:00
Mathieu Choplain
0ee6ec0617 soc: st: stm32: wkup_pins: enable retention for STM32WBA wake-up pins
In order for wake-up pins to behave properly in Standby mode on STM32WBA,
the I/O Standby Retention must be enabled. (It only comes in effect when
the SoC does enter Standby mode, and has no effect otherwise).

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-11-24 17:30:03 +01:00
Ayush Singh
0b173063fe soc: ti: simplelink: cc13x2x7_cc26x2x7: Add poweroff support
- Tested on BeagleConnect Freedom with
  samples/boards/ti/cc13x2_cc26x2/system_off

Signed-off-by: Ayush Singh <ayush@beagleboard.org>
2025-11-24 17:22:06 +01:00
McAtee Maxwell
f587c056a7 drivers: clock_control: fix clock pathing for infineon clocks
- fix fixed_factor clock_control driver
- update pse84 dts with fixes
- update psc3 dts with fixes
- update pse84_ai dts with fixes

Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
2025-11-24 08:47:15 +01:00
John Batch
8275b4fb2f drivers: i2c: infineon: Fixing build errors in i2c_ifx_cat1_pdl.c
Fixing build errors related to reference to an incorrect define.
Adds missing headers to pinctrl_soc.h for Edge platform.

Signed-off-by: John Batch <john.batch@infineon.com>
2025-11-22 05:12:02 -05:00
Peter van der Perk
9f20e79f66 soc: nxp: s32: S32K3 use early reset to init ECC ram before using it.
SOC_RESET_HOOK is already too late because the code touches ram already
instead use the newer SOC_EARLY_RESET_HOOK so we can do ECC
initialization before using the memory

Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
2025-11-21 11:40:56 -05:00
Guillaume Legoupil
2baee8af6d drivers: add config NXP_IEEE802154_MAC to pull up MCUX_COMPONENTs for NBU
west: update hal_nxp to integrate mcux: middleware: ieee_802_15_4 MAC: Add
      CONFIG_NXP_IEEE802154_MAC
      zephyr: blobs: add MCXW71 & MCXW72 BLE controller and Host libraries
                     (ieee-802.15.4-mac) to MCUXSDK 25.09.00 release
      This new version of the BLE controller is for ZigBee support and
      implements ieee-802.15.4 MAC interface.

Update connectivity framework for MCXW71 & MCXW72 BLE controller
(ieee-802.15.4 MAC) from MCUXSDK 25.09 release.

Signed-off-by: Guillaume Legoupil <guillaume.legoupil@nxp.com>
2025-11-21 12:02:00 +01:00
Yongxu Wang
1266be59d6 soc: nxp: imx9: use SCMI generic power domain ON/OFF
Switch to SCMI_POWER_STATE_GENERIC_ON/OFF from the power protocol
header instead of local defines

Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
2025-11-21 10:10:24 +02:00
Yongxu Wang
2c72fe58e8 soc: nxp: imx943: configure GPT as system timer for power management
Configure GPT timers as system tick source when PM is enabled to resolve
low power mode issues:
- Cortex-M SysTick loses state during mix power-off
- SysTick cannot maintain time during system suspend

Configuration changes:
- Disable Cortex-M SysTick when GPT timer is enabled
- Set GPT clock frequency to 32768 Hz for low power operation, 32k is
  reserved in soc level system sleep mode
- Configure system tick rate to 1024 Hz

Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
2025-11-21 10:09:40 +02:00
Mathieu Choplain
df71f6c730 soc: st: stm32: wba: replace Kconfig power supply configuration with DT
Replace the existing infrastructure to specify power supply configuration
through Kconfig with Devicetree, and update all boards according to new
mechanism.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-11-20 16:00:39 +00:00
Mathieu Choplain
3b55e9a219 soc: st: stm32: u5: replace Kconfig power supply configuration with DT
Replace the existing infrastructure to specify power supply configuration
through Kconfig with Devicetree.
Set the LDO as default to reduce out-of-tree breakage - most users were
relying on LDO being the default and it is harmless to use LDO if board
is designed for SMPS. (Existing SMPS users should break anyways since the
Kconfig symbol no longer exists, but this ensures they actively set the
power supply to SMPS in DT)

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-11-20 16:00:39 +00:00
Mathieu Choplain
7477212372 soc: st: stm32: h7rs: replace Kconfig power supply configuration with DT
Replace the existing infrastructure to specify power supply configuration
through Kconfig with Devicetree. Also update all boards that were defining
the Kconfig to no longer do so.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-11-20 16:00:39 +00:00
Mathieu Choplain
800fefa82b soc: st: stm32: h7: replace Kconfig power supply configuration with DT
Replace the existing infrastructure to specify power supply configuration
through Kconfig with Devicetree. Also update all boards that were defining
the Kconfig to no longer do so.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-11-20 16:00:39 +00:00
Vit Stanicek
ea55b27c38 samples: i2s_codec: Enable on rd_rw612_bga
Instantiate the wm8904 driver in rd_rw612_bga's DT. Add MCLK clock
configuration to rw612's soc.c. Modify pinmux definitions to route
those. Add DT and Kconfig fragments to the sample. Document output jack
utilised.

Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
2025-11-20 06:03:44 -05:00
Vit Stanicek
7341b8ad89 samples: i2s_codec: Enable on lpcxpresso55s69/cpu0
Modify board's pinctrl nodes to include the MCLK signal. Instantiate the
wm8904 driver. Add board specific Kconfig fragment and DT overlay. Set
up the MCLK signal.

Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
2025-11-20 06:03:44 -05:00
John Batch
36ecb5a39c SOC: Infineon: CYW20829: Adding B1 devices to CYW20829 Family.
Adding B1 revision devices to CYW20829 family.
Clean up unsupported devices from SOC files.

Signed-off-by: John Batch <john.batch@infineon.com>
2025-11-20 06:02:48 -05:00
Carles Cufi
b2d65fbc46 soc: nxp: imxrt: Select missing ATOMIC_OPERATIONS_*
Follow-up to
689ba58b10.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2025-11-19 15:54:32 -05:00