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drivers: timer: ambiq: add clock source selection for stimer

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Add clock source selection for stimer and make it configurable

Signed-off-by: Hao Luo <hluo@ambiq.com>
This commit is contained in:
Hao Luo 2024-11-25 16:37:45 +08:00 • committed by Benjamin Cabé
commit 5d4353dc9a
13 changed files with 73 additions and 5 deletions
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3
boards/ambiq/apollo3_evb/Kconfig.defconfig
View file

@ -4,6 +4,9 @@
if BOARD_APOLLO3_EVB
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768 if AMBIQ_STIMER_TIMER
config LOG_BACKEND_SWO_FREQ_HZ
default 1000000
depends on LOG_BACKEND_SWO

4
boards/ambiq/apollo3_evb/apollo3_evb.dts
View file

@ -85,6 +85,10 @@
};
};
&stimer0 {
clk-source = <3>;
};
&bleif {
pinctrl-0 = <&bleif_default>;
pinctrl-names = "default";

3
boards/ambiq/apollo3p_evb/Kconfig.defconfig
View file

@ -4,6 +4,9 @@
if BOARD_APOLLO3P_EVB
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768 if AMBIQ_STIMER_TIMER
config LOG_BACKEND_SWO_FREQ_HZ
default 1000000
depends on LOG_BACKEND_SWO

4
boards/ambiq/apollo3p_evb/apollo3p_evb.dts
View file

@ -85,6 +85,10 @@
};
};
&stimer0 {
clk-source = <3>;
};
&bleif {
pinctrl-0 = <&bleif_default>;
pinctrl-names = "default";

3
boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig
View file

@ -4,6 +4,9 @@
if BOARD_APOLLO4P_BLUE_KXR_EVB
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768 if AMBIQ_STIMER_TIMER
config LOG_BACKEND_SWO_FREQ_HZ
default 1000000
depends on LOG_BACKEND_SWO

4
boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts
View file

@ -131,6 +131,10 @@
};
};
&stimer0 {
clk-source = <3>;
};
&xo32m {
pinctrl-0 = <&xo32m_default>;
pinctrl-names = "default";

3
boards/ambiq/apollo4p_evb/Kconfig.defconfig
View file

@ -4,6 +4,9 @@
if BOARD_APOLLO4P_EVB
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768 if AMBIQ_STIMER_TIMER
config LOG_BACKEND_SWO_FREQ_HZ
default 1000000
depends on LOG_BACKEND_SWO

4
boards/ambiq/apollo4p_evb/apollo4p_evb.dts
View file

@ -149,6 +149,10 @@ compatible = "ambiq,adc";
};
};
&stimer0 {
clk-source = <3>;
};
zephyr_udc0: &usb {
vddusb33-gpios = <&gpio96_127 7 (GPIO_PULL_UP)>;
vddusb0p9-gpios = <&gpio96_127 5 (GPIO_PULL_UP)>;

11
boards/rakwireless/rak11720/Kconfig.defconfig Normal file
View file

@ -0,0 +1,11 @@
# RAKWIRELESS RAK11720 Board configuration
# Copyright (c) 2024 RAKwireless Technology Co., Ltd. <www.rakwireless.com>
# Sercan Erat <sercanerat@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if BOARD_RAK11720
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768 if AMBIQ_STIMER_TIMER
endif # BOARD_RAK11720

4
boards/rakwireless/rak11720/rak11720.dts
View file

@ -61,6 +61,10 @@
};
};
&stimer0 {
clk-source = <3>;
};
&bleif {
pinctrl-0 = <&bleif_default>;
pinctrl-names = "default";

6
drivers/timer/ambiq_stimer.c
View file

@ -31,6 +31,8 @@
#define TIMER_IRQ (DT_INST_IRQN(0))
#define TIMER_CLKSRC (DT_INST_PROP(0, clk_source))
#if defined(CONFIG_TEST)
const int32_t z_sys_timer_irq_for_test = TIMER_IRQ;
#endif
@ -184,10 +186,10 @@ static int stimer_init(void)
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
am_hal_stimer_config((oldCfg & ~(AM_HAL_STIMER_CFG_FREEZE | CTIMER_STCFG_CLKSEL_Msk)) |
AM_HAL_STIMER_XTAL_32KHZ | AM_HAL_STIMER_CFG_COMPARE_A_ENABLE);
TIMER_CLKSRC | AM_HAL_STIMER_CFG_COMPARE_A_ENABLE);
#else
am_hal_stimer_config((oldCfg & ~(AM_HAL_STIMER_CFG_FREEZE | STIMER_STCFG_CLKSEL_Msk)) |
AM_HAL_STIMER_XTAL_32KHZ | AM_HAL_STIMER_CFG_COMPARE_A_ENABLE);
TIMER_CLKSRC | AM_HAL_STIMER_CFG_COMPARE_A_ENABLE);
#endif
g_last_time_stamp = am_hal_stimer_counter_get();

26
dts/bindings/timer/ambiq,stimer.yaml
View file

@ -13,3 +13,29 @@ properties:
interrupts:
required: true
clk-source:
type: int
required: true
description: |
clk-source specifies the clock source that used by the system timer.
For Apollo3:
0 - NOCLK : No clock enabled.
1 - HFRC_DIV16 : 3MHz from the HFRC clock divider.
2 - HFRC_DIV256 : 187.5KHz from the HFRC clock divider.
3 - XTAL_DIV1 : 32768Hz from the crystal oscillator.
4 - XTAL_DIV2 : 16384Hz from the crystal oscillator.
5 - XTAL_DIV32 : 1024Hz from the crystal oscillator.
6 - LFRC_DIV1 : Approximately 1KHz from the LFRC oscillator (uncalibrated).
7 - CTIMER0A : Use CTIMER 0 section A as a prescaler.
8 - CTIMER0B : Use CTIMER 0 section B (or A and B linked together) as a prescaler.
For Apollo4:
0 - NOCLK : No clock enabled.
1 - HFRC_6MHZ : 6MHz from the HFRC clock divider.
2 - HFRC_375KHZ : 375KHz from the HFRC clock divider.
3 - XTAL_32KHZ : 32768Hz from the crystal oscillator.
4 - XTAL_16KHZ : 16384Hz from the crystal oscillator.
5 - XTAL_1KHZ : 1024Hz from the crystal oscillator.
6 - LFRC_1KHZ : Approximately 1KHz from the LFRC oscillator (uncalibrated).
7 - CTIMER0 : Use CTIMER 0 for the clock source (allows prescaling from other system clocks).
8 - CTIMER1 : Use CTIMER 1 for the clock source (allows prescaling from other system clocks).

3
soc/ambiq/Kconfig.defconfig
View file

@ -9,9 +9,6 @@ rsource "*/Kconfig.defconfig"
config CORTEX_M_SYSTICK
default n if AMBIQ_STIMER_TIMER
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768 if AMBIQ_STIMER_TIMER
config SYS_CLOCK_TICKS_PER_SEC
default 1024