Commit graph

145 commits

Author SHA1 Message Date
Carlo Caione
5d104f20ab riscv: Introduce API for CLIC and PLIC
Introduce a new interface for CLIC and PLIC to be used by the drivers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Carlo Caione
56466a14e1 riscv: Decouple CLIC and PLIC
Try to decouple CLIC and PLIC as much as possible.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Carlo Caione
31c5dc2230 Kconfig: Introduce RISCV_HAS_CLIC
Introduce a new RISCV_HAS_CLIC symbol for platforms using CLIC,
reorganize the Kconfigs and make the Nuclei ECLIC depending on the new
symbol.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Carlo Caione
0e788b89a6 riscv: Use IRQ vector table for vectored mode
For vectored interrupts use the generated IRQ vector table instead of
relying on a custom-generated table.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-07 10:00:20 +02:00
Alex Kolosov
4a52bc22b6 soc: riscv: telink_b91: add dfu related configurations for b91 platform
Modify Telink b91 config files and linker script with necessary config
settings required for DFU.

Signed-off-by: Alex Kolosov <rikorsev@gmail.com>
2022-06-24 20:25:33 +02:00
Carlo Caione
741b9dc65d riscv: Rename __irq_wrapper to _isr_wrapper
For some reasons RISCV is the only arch where the vector table entry is
called __irq_wrapper instead of _isr_wrapper. This is not only a
cosmetic change but Zephyr expects the common ISR handler to be called
_isr_wrapper (for example when generating the IRQ vector table).

Change it.

find ./ -type f -exec sed -i 's/__irq_wrapper/_isr_wrapper/g' {} \;

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-21 20:27:20 -04:00
Yuriy Vynnychek
49d873603c soc: riscv: telink_b91: B91 BLE controller support (linker aes_data)
Introduced new aes_data linker section used by B91 BLE controller.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2022-06-05 14:45:10 +02:00
Carlo Caione
10061efdc4 riscv: Rework and cleanup Kconfig
This patch is doing several things:

- Core ISA and extension Kconfig symbols have now a formalized name
  (CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*)

- a new Kconfig.isa file was introduced with the full set of extensions
  currently supported by the v2.2 spec

- a new Kconfig.core file was introduced to host all the RISCV cores
  (currently only E31)

- ISA and extensions settings are moved to SoC configuration files

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-05 14:28:42 +02:00
Filip Kokosinski
70c978bb97 soc/riscv/sifive-freedom/fe310: use correct SYS_CLOCK_HW_CYCLES_PER_SEC
This commit introduces changes in three places in order to fix the
problem with timer-related tests on FE310-based boards:
* tests/kernel/sleep/kernel.common.timing
* tests/kernel/tickless/tickless_concept/kernel.tickless.concept
* tests/kernel/workq/work_queue/kernel.workqueue

The first change is the modification of the SYS_CLOCK_HW_CYCLES_PER_SEC
value back to 32768 Hz to match FE310's datasheet description.

The second change is CLINT frequency reduction in Renode simulation
model to 16 MHz to correspond with the oscillator frequency given by the
FE310's datasheet and the HiFive1 board schematic. This fixes the first
two tests.

The last change is reducing the MIN_DELAY define to 100. This causes the
RISC-V machine timer driver to update the mtimecmp register more often,
which in turn addresses the `work_queue/kernel.workqueue` problem with
work items finishing prematurely, causing the above-mentioned test to
fail.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-05-24 08:58:43 -07:00
Nicolas Pitre
1cb557dccf riscv: rationalize PMP related Kconfig options
ARCH_HAS_USERSPACE and ARCH_HAS_STACK_PROTECTION are direct functions
of RISCV_PMP regardless of the SoC.

PMP_STACK_GUARD is a function of HW_STACK_PROTECTION (from
ARCH_HAS_STACK_PROTECTION) and not the other way around.

This allows for tests/kernel/fatal/exception to test protection against
various stack overflows based on the PMP stack guard functionality.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-05-18 10:54:53 +02:00
Henrik Brix Andersen
957000c9d8 soc: riscv: privilege: gd32vf103: undefine CAN_MODE_NORMAL
The GigaDevice HAL defines CAN_MODE_NORMAL, which conflicts with the
zephyr/drivers/can.h header definition. Undefine it in soc.h.

Fixes: #45611

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-05-16 12:56:50 +02:00
Gerard Marull-Paretas
26a924a44e soc: riscv: mpfs: update include paths
Use the <zephyr/...> prefix.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:45:29 -04:00
Gerard Marull-Paretas
4b91c2d79f asm: update files with <zephyr/...> include prefix
Assembler files were not migrated with the new <zephyr/...> prefix.
Note that the conversion has been scripted, refer to #45388 for more
details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:45:29 -04:00
Gerard Marull-Paretas
d342e4c4c1 linker: update files with <zephyr/...> include prefix
Linker files were not migrated with the new <zephyr/...> prefix.  Note
that the conversion has been scripted, refer to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:45:29 -04:00
Gerard Marull-Paretas
0e69129fb3 soc: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:57:59 +02:00
Peter McShane
635f7ec536 soc: riscv: Add Microchip mpfs soc
Adding soc support for Microchip PolarFire SoC soc

Signed-off-by: Peter McShane <peter.mcshane@microchip.com>
2022-05-06 11:32:54 +02:00
Nicolas Pitre
ec9c2ec2d8 riscv: pmp: rename CONFIG_PMP_SLOT
The plural form is clearer.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-04-29 15:30:00 +02:00
Nicolas Pitre
2fece49a14 riscv: pmp: switch over to the new implementation
Add the appropriate hooks effectively replacing the old implementation
with the new one.

Also the stackguard wasn't properly enforced especially with the
usermode combination. This is now fixed.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-04-29 15:30:00 +02:00
Shawn Nematbakhsh
2a9b2dd7b9 soc: riscv: sifive-freedom: Revert whitespace mistake.
Revert the deleted spaces from PR#42280 / c74526919.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2022-04-05 17:09:40 -04:00
Shawn Nematbakhsh
a8ffd19281 soc: riscv: sifive-freedom: fe310: Support custom coreclk rate in DTS.
Allow coreclk to be configured up to 320 MHz from DTS.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2022-04-05 12:00:03 +02:00
Shawn Nematbakhsh
c74526919d soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS.
Rather than specify input clock for each peripheral individually, instead
specify the relevant clocks in DTS.

This will enable easier support for non-default coreclk on fe310 in a
follow-up CL.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2022-04-05 12:00:03 +02:00
Gerard Marull-Paretas
c925b5991a include: remove unnecessary autoconf.h includes
The autoconf.h header is not required because the definitions present in
the file are exposed using the compiler `-imacros` flag.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-04-05 11:18:20 +02:00
Filip Kokosinski
8388bb7c24 soc: riscv: sifive-freedom: fix SYS_CLOCK_HW_CYCLES_PER_SEC value
This commit fixes the default value of SYS_CLOCK_HW_CYCLES_PER_SEC
option. The previous value of 32768 is not consistent with the
documentation of FE310 SoC. Only FE310-based boards rely on the default
value of this option; other boards from the Freedom series define it
themselves.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-03-24 10:46:34 +01:00
Filip Kokosinski
38f38e0be8 boards: FE310-based boards: transition to pinctrl driver
This commit makes the transition from the pinmux driver to the pinctrl
driver. It also modifies UART, SPI and I2C drivers used in FE310-based
boards to use the new pinctrl API.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-03-24 10:46:34 +01:00
Filip Kokosinski
a5cc185b9b drivers: pinctrl: add SiFive pinctrl driver
Add a pinctrl driver used in FE310-based boards.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-03-24 10:46:34 +01:00
Nazar Kazakov
f483b1bc4c everywhere: fix typos
Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
2022-03-18 13:24:08 -04:00
William Patty
01ebcda726 soc: riscv: riscv-privilege: add support for mtvec vectored mode
Enable support for mtvec vectored mode for privilege SOCs. This
is an optional feature and takes up addtional code space. It is
necessary to support this feature for privilege SOCs that only
support mtvec vectored mode.

Change was tested on qemu_riscv32 and qemu_riscv64 boards with
CONFIG_RISCV_MTVEC_VECTORED_MODE enabled.

Signed-off-by: William Patty <wpatty24@gmail.com>
2022-03-17 11:12:32 +01:00
Gerard Marull-Paretas
95fb0ded6b kconfig: remove Enable from boolean prompts
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:

sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-09 15:35:54 +01:00
Ederson de Souza
2aab236c12 arch/riscv: Add IPI support
Use CLINT to send interrupts to another CPU. SMP support is kinda
incomplete without it.

This patch only enables it for riscv-privilege platforms - specifically,
"virt" one.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-02-25 19:13:50 -05:00
Ederson de Souza
d9ab35577b arch/riscv: Boot secondary CPUs for SMP support
Secondary CPUs are now initialised and made available to the system. If
the system has more CPUs than configured via CONFIG_MP_NUM_CPUS, those
are still left looping as before.

Some implementations of `soc_interrupt_init` also changed to use
`arch_irq_lock` instead of `irq_lock`.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-02-25 19:13:50 -05:00
Carles Cufi
e83a13aabf kconfig: Rename the TEST_EXTRA stack size option to align with the rest
All stack sizes should end with STACK_SIZE.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2022-02-22 08:23:05 -05:00
Carlo Caione
18ffcdcf74 linker: Introduce zephyr,memory-region compatible
Introduce a new "zephyr,memory-region" compatible to be used when a new
memory region must be created in the linker script from the devicetree
nodes using the compatible.

Remove also the LINKER_DT_REGION_FROM_NODE macro and add a new
LINKER_DT_REGIONS macro to cycle through all the compatible regions.

In the same PR modify the DTS files and the linker scripts.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-02-21 22:02:04 -05:00
Katsuhiro Suzuki
feaf0070fc boards: riscv: hifive_unleashed: add GPIO support
This patch adds GPIO and 96board LS (Low Speed)iexpansion  connector
support for SiFive HiFive Unleashed and also enables GPIO basic test.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2022-02-21 20:46:47 -05:00
Yuriy Vynnychek
45744e7b35 soc: riscv: telink_b91: new pinctrl driver support
Added basic support for new pinctrl driver.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2022-02-21 19:41:44 -05:00
Henry Hsieh
58d50a0e97 riscv: fix non-standard assembly of RISC-V
Non-standard `jalr rd, rs` pseudo-instructions are used.
This commit changes them to `ret` for standard return pseudo-instruction
or `jalr rd, rs, 0` for no offset jump register and link.

Fixes #41100.

Signed-off-by: Henry Hsieh <r901042004@yahoo.com.tw>
2022-02-04 11:23:39 +01:00
Daniel Leung
61d0c3cfe7 riscv: remove @return doc for void functions
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-12 16:02:16 -05:00
Gerard Marull-Paretas
e5e73a70e9 soc: remove unnecessary inclusions of devicetree.h
Many ARM SoCs included <devicetree.h> likely due to:

1. nvic.h not being self-contained
2. As a result of copy-paste

Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:

sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h

soc.h files that make a legitimate usage of the API have not been
changed.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
31ad52336b soc: riscv: telink_b91: fix required headers
The linker script is using the DT API, which was previously included via
<soc.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Gerard Marull-Paretas
130b06a0fd soc: riscv: riscv-privilege: andes_v5: make smu.h self contained
The header was not self-contained: it uses DT and utility macros but
<devicetree.h> and <sys/util_macro.h> were not included.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Jim Shu
74faa18902 soc: riscv: virt: enable RISC-V PMP support
Enable CONFIG_RISCV_PMP in qemu virt soc. Use this SoC as CI testing
platform of RISC-V PMP and Userspace.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2022-01-11 11:47:03 +01:00
TOKITA Hiroshi
5c7a0ef888 drivers: interrupt-controller: add Nuclei ECLIC driver
Add support for the ECLIC interrupt controller
which is used with the Nuclei processor core.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
TOKITA Hiroshi
949d4b91d9 drivers: pinctrl: Support pinctrl with GD32VF103
Change the settings to support pinctrl on the GD32VF103.

- Split soc/arm/gigadevice/common/pinctrl_soc.h
  and put it into include/dt-bindings.
- Leave some definitions that can't handle with device tree compiler
  in pinctrl_soc.h.
- Remove dependency to SOC_FAMILY_GD32 because always enabled it
  if GD32_HAS_AF(IO)_PINMAX was selected.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
TOKITA Hiroshi
c9c04e491e soc: riscv: Add initial support for GigaDevice GD32V SoC
Add GigaDevice GD32V SoC.
GD32V has non-standard CSR. It doesn't use common startup code.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
TOKITA Hiroshi
d53e49c532 soc: nuclei: Add Nuclei specialized CSR definitions
Nuclei core has non-RISCV standard CSRs.
Add a header file to suppor these CSRs.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
TOKITA Hiroshi
2de3133a05 riscv: Add an option for configuring mcause exception mask
GD32V processor core is used non-standard bitmask
for mcause register. Add option to configure the bitmask
to support GD32V.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
Jordan Yates
7b2a388d1d linker: remove manual name specification
As memory region names are now derived purely from devicetree, remove
the `name` parameter from `DT_REGION_FROM_NODE_STATUS_OKAY`. Name is
`zephyr,linker-region` if it exists, otherwise the node path.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2021-12-09 16:23:03 +01:00
Henrik Brix Andersen
91233dba70 drivers: entropy: add driver for the neorv32 trng
Add entropy driver for the NEORV32 True Random Number Generator (TRNG).

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-10-26 17:53:15 -04:00
Henrik Brix Andersen
d711d224c2 drivers: serial: neorv32: use shared serial driver init priority
Use the shared CONFIG_SERIAL_INIT_PRIORITY for driver initialization
priority.

Override the default value for the NEORV32 SoC to ensure the serial
driver is initialized after the syscon driver by default.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-10-19 06:44:46 -04:00
Henrik Brix Andersen
a281dbfb6d soc: riscv: privilege: add neorv32 processor suppport
Add support for the open-source NEORV32 RISC-V compatible processor
system (SoC).

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-10-15 09:46:53 -04:00
Henrik Brix Andersen
91a0372b5c soc: riscv: priv: call __reset during boot
Call __reset instead of directly calling __initialize from the common
RISC-V privileged SoC vectors __start. This allows injection of SoC
specific reset code just after setting up the machine trap vector.

RISC-V privilege SoCs without the need for custom reset code can set
CONFIG_INCLUDE_RESET_VECTOR=y to include a __reset stub which simply
calls __initialize.

Fixes: #38396

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-09-14 09:48:03 -04:00