As a result of the 11a2107d991b("riscv: timer: driver revamp") commit,
gd32vf103 no longer works properly.
In the
c9c04e491e0f("soc: riscv: Add initial support for GigaDevice GD32V SoC")
that is the first commit of implementation of this SoC,
set the CPU frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
and riscv_machine_timer divide the clock with the value of
CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER.
The CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC should set the timer's clock,
so I fixed to set the config as 27MHz in this PR. Also, remove the
unnecessary CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER setting.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Adds watchdog reset as a reset source at SoC init. This is achieved by:
1. Writing 0x2 to the RESET_EN bitfield register to indicate watchdog
reset is enabled.
2. Writing 0x1 to the CFG_CDC_SYNC register to commit the change.
3. Polling the CFG_CDC_SYNC register until reading 0 to confirm the
change has been processed.
This patch is part of the OpenTitan watchdog (AON Timer) support patch
series. It is needed to ensure that the watchdog reset functionality
is enabled. Note that the timer itself is not enabled here, only the
reset function.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
1. Fixes the number of interrupts in OpenTitan by default. This should
be 32 + 185 = 217 IRQs, as there are 185 configurable registers,
including interrupt 0.
2. Adds 2ND_LVL_INTR_00_OFFSET Kconfig, which is needed to generate a
PLIC interrupt on IRQ 11.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
The Mi-V implements the A extension therefore it shouldn't use the C
version. The built-in version generates code with proper machine
opcodes.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
use helper macros from csr.h instead of inline assembly which results
in cleaner and more maintainable code
Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
The init infrastructure, found in `init.h`, is currently used by:
- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices
They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:
```c
struct init_entry {
int (*init)(const struct device *dev);
/* only set by DEVICE_*, otherwise NULL */
const struct device *dev;
}
```
As a result, we end up with such weird/ugly pattern:
```c
static int my_init(const struct device *dev)
{
/* always NULL! add ARG_UNUSED to avoid compiler warning */
ARG_UNUSED(dev);
...
}
```
This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:
```c
static int my_init(void)
{
...
}
```
This is achieved using a union:
```c
union init_function {
/* for SYS_INIT, used when init_entry.dev == NULL */
int (*sys)(void);
/* for DEVICE*, used when init_entry.dev != NULL */
int (*dev)(const struct device *dev);
};
struct init_entry {
/* stores init function (either for SYS_INIT or DEVICE*)
union init_function init_fn;
/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
* to know which union entry to call.
*/
const struct device *dev;
}
```
This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.
**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
init: convert SYS_INIT functions to the new signature
Conversion scripted using scripts/utils/migrate_sys_init.py.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
manifest: update projects for SYS_INIT changes
Update modules with updated SYS_INIT calls:
- hal_ti
- lvgl
- sof
- TraceRecorderSource
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: devicetree: devices: adjust test
Adjust test according to the recently introduced SYS_INIT
infrastructure.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: kernel: threads: adjust SYS_INIT call
Adjust to the new signature: int (*init_fn)(void);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
For RISCV arch, enable FLASH_SIZE and FLASH_BASE_ADDRESS config.
To avoid duplicated work, remove flash config from RISCV soc.
Signed-off-by: Jonas Otto <jonas@jonasotto.com>
- Put L2C init level in pre_kernel_2 to wait for syscon driver
- Check if SMU exists when preprocessing
Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
Executing code out of RAM on IT8xxx2 requires that the relevant
addresses be mapped onto the CPU's instruction memory bus, referred to
by ITE documentation as Instruction Local Memory (ILM). ILM mappings
configure blocks of RAM to be used for accesses to chosen addresses when
performing instruction fetch, instead of the memory that would normally
be accessed at that address.
ILM must be used for some chip features (particularly Flash
self-programming, to execute from RAM while writing to Flash), and has
historically been configured in the Flash driver. The RAM for that was
hard-coded as a single 4k block in the linker script. Configuring ILM
in the flash driver is confusing because it is used by other SoC code as
well, currently in code that cannot depend on the Flash being functional
or in hand-selected functions that seem performance-critical.
This change moves ILM configuration to a new driver and dynamically
allocates RAM to ILM in the linker script, allowing software use of the
entire 64k RAM depending on configuration. This makes ILM configuration
more discoverable and makes it much easier to correctly support the
CODE_DATA_RELOCATION feature on this SoC.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Continue to phase out MP_NUM_CPUS, change Kconfig to be
MP_MAX_NUM_CPUS and make MP_MAX_NUM_CPUS the main Kconfig symbol.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Some files were using macros defined in sys/util.h without including it,
e.g. for MHZ().
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some SoCs define stuff in soc.h, used in drivers or SoC code. Note that
soc.h is not introduced here as a catch-all header. soc.h optimizations
or removal is out of the scope of this patch.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add options about Internal RC(IRC) oscillator.
- GD32_HAS_IRC_32K/40K indicates IRC types.
- GD32_LOW_SPEED_IRC_FREQUENCY is the numeric value of frequency
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Linker scripts contains a `.last_section` section that is placed in rom
region as NOLOAD for the purpose of retrieve the actual number of bytes
contained in the image. See d85efe0b10
However, a previous section may cause the location counter to be
incremented for alignment purposes. This can result in the size of the
image to be 0x10FA but location counter to be 0x1100 because it has been
aligned for next section placement.
Therefore, two new Kconfig settings are introduced.
Those settings request the linker to will write a pattern in
`.last_section`. Together with removing NOLOAD and writing a patten to
the section then we ensure that data is written after alignment of
location counter, and thereby forces the image size to be in sync with
the location counter.
The default pattern used will be 0xE015 (end of last section).
Some systems may fill up the flash completely, or simply write data at
the end of the flash, which in both cases can result in overflow.
Therefore, the new settings can be disabled.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This patch adds a clock control driver for GD32 platforms. It is
important to note that the driver is only able to handle peripheral
clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On
some similar platforms (STM32) this task is embedded in the same clock
driver, performed at init time but with no options to do any
manipulation at runtime via the API calls. The clock control API as-is
is really orthogonal to "system clocks", and it is arguably a bad idea
to embed system clock init code in a clock control driver. It can be
done at SoC level still using Devicetree as a source of hardware
description/initial configuration.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Place vector sections after ROM_START sections.
Also add init.ld script that will prevent overlapping .init sections
in telink_b91 SoC.
Fixes#49036.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Similar to pinctrl, almost all device drivers will depend on the reset
controller being available, so default the driver class to y at SoC
level.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
machine-timer node name changed in #48429.
but Kcondif.defconfig.gd32vf103 not followed it.
It makes misconfigures the RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER.
So the machine-timer did not count the actual time.
Correcting node name to fix this problem.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
All SOC_ERET definitions expand to the mret instruction (used to return
from a trap: exception or interruption). The 'eret' instruction existed
in previous RISC-V privileged specs, but it doesn't seem to be used in
Zephyr (ref. RISC-V Privileged Architectures 3.2.2).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Andes fpga base AE350(60M Hz) may fail in XIP because it causes hundreds
of cycles to fetch instructions, decreased tick rate to 100 if CONFIG_XIP.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
After some analysis I found out that there's no machine timer provided
by the "riscv" vendor. There are some specs for the mtime/mtimecmp
registers (this is why we can have a single driver), but the actual
register layout or implementations differ amongst vendors. GD32 uses the
Nuclei implementation, named "system timer" in their documentation. This
patch aligns with vendor specs.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Base address for PRCI is not used anywhere in the tree for this
platform. Again, if ever used, this needs to come from DT.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
There is no GPIO driver for such platform, and if it existed, all this
information should be provided in Devicetree (as other platform drivers
like UART do).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
- zephyr/toolchain.h is not needed
- gd32vf103.h is not needed (no CMSIS here)
- undefinition not needed, HAL is now patched with a prefix for this
definition.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
SystemInit is declared in gd32vf103.h. Include it instead of relying on
indirect soc.h includes.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
We already have riscv_clic.h and riscv_plic.h, no need to have the same
declarations in soc_common.h as well.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
