drivers: syscon: Introduce BFLB Efuse driver
This introduces a driver used to access bouffalolab efuses via syscon API Signed-off-by: Camille BAUD <mail@massdriver.space>
This commit is contained in:
Camille BAUD
Benjamin Cabé
parent
22fa13083a
commit
88387b44dc
5 changed files with 277 additions and 0 deletions
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@ -2,3 +2,4 @@
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_SYSCON_GENERIC syscon.c)
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zephyr_library_sources_ifdef(CONFIG_SYSCON_BFLB_EFUSE syscon_bflb_efuse.c)
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@ -38,4 +38,6 @@ config SYSCON_INIT_PRIORITY
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initialized earlier in the startup cycle. If unsure, leave at default
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value
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source "drivers/syscon/Kconfig.bflb_efuse"
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endif # SYSCON
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9
drivers/syscon/Kconfig.bflb_efuse
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9
drivers/syscon/Kconfig.bflb_efuse
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@ -0,0 +1,9 @@
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# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space)
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# SPDX-License-Identifier: Apache-2.0
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config SYSCON_BFLB_EFUSE
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bool "Bouffalolab EFUSEs driver"
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default y
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depends on DT_HAS_BFLB_EFUSE_ENABLED
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help
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E-Fuse access via SYSCON API for Bouffalolab platforms.
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248
drivers/syscon/syscon_bflb_efuse.c
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248
drivers/syscon/syscon_bflb_efuse.c
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@ -0,0 +1,248 @@
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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT bflb_efuse
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#include <zephyr/drivers/syscon.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(efuse_bflb, CONFIG_SYSCON_LOG_LEVEL);
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#include <bouffalolab/bl60x/bflb_soc.h>
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#include <bouffalolab/bl60x/hbn_reg.h>
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#include <bouffalolab/bl60x/ef_ctrl_reg.h>
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#include <bouffalolab/bl60x/extra_defines.h>
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struct efuse_bflb_data {
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uint8_t cache[DT_INST_PROP(0, size)];
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bool cached;
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};
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struct efuse_bflb_config {
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uintptr_t addr;
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size_t size;
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};
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static inline void efuse_bflb_clock_settle(void)
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{
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__asm__ volatile (".rept 15 ; nop ; .endr");
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}
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/* 32 Mhz Oscillator: 0
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* crystal: 1
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* PLL and 32M: 2
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* PLL and crystal: 3
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*/
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static void efuse_bflb_set_root_clock(uint32_t clock)
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{
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uint32_t tmp;
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/* invalid value, fallback to internal 32M */
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if (clock > 3) {
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clock = 0;
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}
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tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
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tmp = (tmp & HBN_ROOT_CLK_SEL_UMSK) | (clock << HBN_ROOT_CLK_SEL_POS);
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sys_write32(tmp, HBN_BASE + HBN_GLB_OFFSET);
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efuse_bflb_clock_settle();
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}
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static void efuse_bflb_clock_delay_32M_ms(uint32_t ms)
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{
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uint32_t count = 0;
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do {
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__asm__ volatile (".rept 32 ; nop ; .endr");
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count++;
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} while (count < ms);
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}
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static uint32_t efuse_bflb_is_pds_busy(const struct device *dev)
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{
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uint32_t tmp;
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const struct efuse_bflb_config *config = dev->config;
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tmp = sys_read32(config->addr + EF_CTRL_EF_IF_CTRL_0_OFFSET);
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if (tmp & EF_CTRL_EF_IF_0_BUSY_MSK) {
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return 1;
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}
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return 0;
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}
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/* /!\ only use when running on 32Mhz Oscillator Clock
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* (system_set_root_clock(0);
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* system_set_root_clock_dividers(0, 0);
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* sys_write32(32 * 1000 * 1000, CORECLOCKREGISTER);)
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* Only Use with IRQs off
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* returns 0 when error
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*/
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static void efuse_bflb_efuse_read(const struct device *dev)
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{
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const struct efuse_bflb_config *config = dev->config;
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uint32_t tmp;
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uint32_t *pefuse_start = (uint32_t *)(config->addr);
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uint32_t timeout = 0;
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do {
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efuse_bflb_clock_delay_32M_ms(1);
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timeout++;
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} while (timeout < EF_CTRL_DFT_TIMEOUT_VAL && efuse_bflb_is_pds_busy(dev) > 0);
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/* do a 'ahb clock' setup */
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tmp = EF_CTRL_EFUSE_CTRL_PROTECT
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| (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS)
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| (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
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#if defined(CONFIG_SOC_SERIES_BL60X)
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| (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)
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#endif
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| (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS)
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| (0 << EF_CTRL_EF_IF_POR_DIG_POS)
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| (1 << EF_CTRL_EF_IF_0_INT_CLR_POS)
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| (0 << EF_CTRL_EF_IF_0_RW_POS)
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| (0 << EF_CTRL_EF_IF_0_TRIG_POS);
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sys_write32(tmp, config->addr + EF_CTRL_EF_IF_CTRL_0_OFFSET);
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efuse_bflb_clock_settle();
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/* clear PDS cache registry */
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for (uint32_t i = 0; i < config->size / 4; i++) {
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pefuse_start[i] = 0;
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}
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/* Load efuse region0 */
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/* not ahb clock setup */
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tmp = EF_CTRL_EFUSE_CTRL_PROTECT
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| (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS)
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| (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
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#if defined(CONFIG_SOC_SERIES_BL60X)
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| (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)
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#endif
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| (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS)
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| (0 << EF_CTRL_EF_IF_POR_DIG_POS)
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| (1 << EF_CTRL_EF_IF_0_INT_CLR_POS)
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| (0 << EF_CTRL_EF_IF_0_RW_POS)
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| (0 << EF_CTRL_EF_IF_0_TRIG_POS);
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sys_write32(tmp, config->addr + EF_CTRL_EF_IF_CTRL_0_OFFSET);
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/* trigger read */
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tmp = EF_CTRL_EFUSE_CTRL_PROTECT
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| (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS)
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| (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
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#if defined(CONFIG_SOC_SERIES_BL60X)
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| (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)
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#endif
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| (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS)
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| (0 << EF_CTRL_EF_IF_POR_DIG_POS)
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| (1 << EF_CTRL_EF_IF_0_INT_CLR_POS)
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| (0 << EF_CTRL_EF_IF_0_RW_POS)
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| (1 << EF_CTRL_EF_IF_0_TRIG_POS);
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sys_write32(tmp, config->addr + EF_CTRL_EF_IF_CTRL_0_OFFSET);
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efuse_bflb_clock_delay_32M_ms(5);
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/* wait for read to complete */
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do {
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efuse_bflb_clock_delay_32M_ms(1);
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tmp = sys_read32(config->addr + EF_CTRL_EF_IF_CTRL_0_OFFSET);
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} while ((tmp & EF_CTRL_EF_IF_0_BUSY_MSK) ||
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!(tmp & EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MSK));
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/* do a 'ahb clock' setup */
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tmp = EF_CTRL_EFUSE_CTRL_PROTECT
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| (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS)
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| (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
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#if defined(CONFIG_SOC_SERIES_BL60X)
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| (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)
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#endif
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| (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS)
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| (0 << EF_CTRL_EF_IF_POR_DIG_POS)
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| (1 << EF_CTRL_EF_IF_0_INT_CLR_POS)
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| (0 << EF_CTRL_EF_IF_0_RW_POS)
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| (0 << EF_CTRL_EF_IF_0_TRIG_POS);
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sys_write32(tmp, config->addr + EF_CTRL_EF_IF_CTRL_0_OFFSET);
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}
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static void efuse_bflb_cache(const struct device *dev)
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{
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struct efuse_bflb_data *data = dev->data;
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const struct efuse_bflb_config *config = dev->config;
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uint32_t tmp;
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uint8_t old_clock_root;
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tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
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old_clock_root = (tmp & HBN_ROOT_CLK_SEL_MSK) >> HBN_ROOT_CLK_SEL_POS;
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efuse_bflb_set_root_clock(0);
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efuse_bflb_clock_settle();
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efuse_bflb_efuse_read(dev);
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/* reads *must* be 32-bits aligned AND does not work with the method memcpy uses */
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for (int i = 0; i < config->size / sizeof(uint32_t); i++) {
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tmp = sys_read32(config->addr + i * 4);
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data->cache[i * sizeof(uint32_t) + 3] = (tmp & 0xFF000000U) >> 24;
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data->cache[i * sizeof(uint32_t) + 2] = (tmp & 0x00FF0000U) >> 16;
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data->cache[i * sizeof(uint32_t) + 1] = (tmp & 0x0000FF00U) >> 8;
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data->cache[i * sizeof(uint32_t) + 0] = (tmp & 0x000000FFU);
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}
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efuse_bflb_set_root_clock(old_clock_root);
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efuse_bflb_clock_settle();
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data->cached = true;
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}
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static int efuse_bflb_read(const struct device *dev, uint16_t reg, uint32_t *val)
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{
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struct efuse_bflb_data *data = dev->data;
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if (!val) {
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return -EINVAL;
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}
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if (!data->cached) {
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efuse_bflb_cache(dev);
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}
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*val = *((uint32_t *)&data->cache[reg]);
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return 0;
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}
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static int efuse_bflb_size(const struct device *dev, size_t *size)
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{
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const struct efuse_bflb_config *config = dev->config;
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*size = config->size;
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return 0;
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}
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static int efuse_bflb_get_base(const struct device *dev, uintptr_t *addr)
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{
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struct efuse_bflb_data *data = dev->data;
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*addr = (uintptr_t)data->cache;
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return 0;
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}
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static DEVICE_API(syscon, efuse_bflb_api) = {
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.read = efuse_bflb_read,
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.get_size = efuse_bflb_size,
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.get_base = efuse_bflb_get_base,
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};
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static const struct efuse_bflb_config efuse_config = {
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.addr = DT_INST_REG_ADDR(0),
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.size = DT_INST_PROP(0, size),
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};
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static struct efuse_bflb_data efuse_data = {
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.cached = false,
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.cache = {0},
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};
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DEVICE_DT_INST_DEFINE(0, NULL, NULL, &efuse_data, &efuse_config, POST_KERNEL,
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CONFIG_SYSCON_INIT_PRIORITY, &efuse_bflb_api);
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17
dts/bindings/syscon/bflb,efuse.yaml
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17
dts/bindings/syscon/bflb,efuse.yaml
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@ -0,0 +1,17 @@
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# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space)
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# SPDX-License-Identifier: Apache-2.0
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description: BouffaloLab Efuse
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compatible: "bflb,efuse"
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include: base.yaml
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properties:
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reg:
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required: true
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size:
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required: true
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type: int
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description: Size of efuse storage (bytes)
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