The current driver has a few limitations:
1. The `ngpios` DT property is fixed at eight.
Since the SN74HC595 and kin are designed to be
easily daisychain-able, the upper bound on `ngpios`
should be limited only by the maximum number of pins
that Zephyr supports per GPIO port, which is 32.
2. In the case of having no control over the shift register's
reset input, the device tree node should accept a default
value to shift into the register(s) during init.
3. There seems to be an assumption that the serial clock
and load clock are tied together. While this is often the
case, the device tree node should be more flexible in
allowing the specification of a separate load clock GPIO pin.
4. The device tree node should also be able to accept a GPIO pin
to drive the enable input pin of the shift register(s).
This commit addresses all of these issues.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
1. Renamed MCXA276 to MCXA266
2. NXP frdm_mcxa276 is renamed to frdm_mcxa266,
add this information to migration-guide-4.3.rst.
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
1. Renamed MCXA166 to MCXA346.
2. NXP frdm_mcxa166 is renamed to frdm_mcxa346,
add this information to migration-guide-4.3.rst.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The stm32n6 features an RNG block. The RNG is a true NIST SP800-90B
compliant entropy source according to the stm32n657x0 reference manual[1].
Per Table 3 in the reference manual, the RNG peripheral register boundary
address (secure) is 0x54020000 to 0x540203FF. That is, base address
0x54020000 and size 0x400.
Per Table 73 in the reference manual, the RNG peripheral has only a single
rng_clk option (hsis_osc_ck).
Per section 14.10.66 (and more) the RNG peripheral control is performed
through AHB3 using bit 0.
As such, the `clocks` property contains a single phandle to the RCC AHB3
bit 0 entries.
Per Table 135 in the reference manual, the RNG peripheral interrupt is
located at position 40 in the NVIC.
[1] RM0486 Rev 2: https://www.st.com/resource/en/reference_manual/rm0486-stm32n647657xx-armbased-32bit-mcus-stmicroelectronics.pdf
Signed-off-by: Emil Dahl Juhl <emil@s16s.ai>
Add support for the SDMMC clock bypass feature for those SoCs that have
it. This provides a SDMMC bus speed double that of `clk-div = <0>`.
Updated the `clk-div` documentation at the same time to be clearer on
how the bus clock speed is determined.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Define SAI1 node for STM32H7xx series.
Add STM32H7xx related DMA configs.
Enable samples/drivers/i2s/output for nucleo_h745zi_q/m7
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Add external interrupt support for Renesas RZ/A3UL, V2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Change the adc node's compatible of RZ/G3S to renesas,rz-adc-c
Fix ADC node register size for Renesas RZ/G3S
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
This patch introduces a new board definition for embedsky’s
TQ‑H503A development board, based on the STM32H503CBT6 SoC.
Tested: successfully built, ran and debug
`hello_world` and `blinky` samples.
Signed-off-by: MA Junyi <mjysci@live.com>
The Egis ET171 SPI controller was based on Andes ATCSPI200,
but has since been modified. In particular, the WrTranCnt and RdTranCnt
fields from the SPI Transfer Control Register have been moved to dedicated
Wr_Tran_Cnt and Rd_Tran_Cnt registers.
Signed-off-by: jacob kung <jacob.kung@egistec.com>
Enable optional storage of sensor attribute values in EEPROM. On reset, the
device goes through a POR sequence that loads the values programmed in the
EEPROM into the respective register map locations.
The driver stores sample frequency, offset, oversampling, lower threshold,
upper threshold, alert pin polarity, alert mode and conversion mode if the
value is continuous or shutdown.
The functionality has been tested with sensor shell and power cycling
sensor:
Test (undocumented) temperature offset is stored:
```shell
uart:~$ sensor attr_set ti_tmp11x@48 ambient_temp offset 0
ti_tmp11x@48 channel=ambient_temp, attr=offset set to value=0
uart:~$ sensor get ti_tmp11x@48 ambient_temp
[...] (25.523436)
uart:~$ sensor attr_set ti_tmp11x@48 ambient_temp offset 50
ti_tmp11x@48 channel=ambient_temp, attr=offset set to value=50
uart:~$ sensor get ti_tmp11x@48 ambient_temp
[...] (75.617186)
uart:~$
[15:12:20.088] Disconnected
[15:12:36.106] Connected
uart:~$ sensor get ti_tmp11x@48 ambient_temp
[...] (75.554686)
uart:~$ sensor attr_get ti_tmp11x@48 ambient_temp offset
ti_tmp11x@48(channel=ambient_temp, attr=offset) value=50.000000
```
Test one-shot mode is not stored:
```shell
uart:~$ sensor attr_set ti_tmp11x@48 ambient_temp 18 1
ti_tmp11x@48 channel=ambient_temp, attr=accel_x set to value=1
uart:~$ sensor get ti_tmp11x@48 ambient_temp
[...] (75.562499)
uart:~$ sensor get ti_tmp11x@48 ambient_temp
Read failed
[00:00:21.332,000] <wrn> sensor_compat: Failed to fetch samples
uart:~$
[15:16:24.529] Disconnected
[15:16:33.540] Connected
uart:~$ sensor get ti_tmp11x@48 ambient_temp
[...] (75.406249)
uart:~$ sensor get ti_tmp11x@48 ambient_temp
[...] (75.351561)
```
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add PWM driver support for Renesas RZ/A3UL
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
This commit introduces a new devicetree property, bits-per-symbol, to
allow the symbol width to be configured from 3 to 8 bits. This change
is particularly beneficial for MCUs that lack DMA for their SPI
peripheral and have a limited hardware FIFO.
This property provides flexibility by allowing developers to select a
slower SPI clock frequency and use the symbol width to scale the
timings to meet strict LED strip requirements, minimizing the risk of
FIFO underruns.
Additionally, using higher-density patterns (e.g., 3-bit or 4-bit
symbols) makes more efficient use of the pixel buffer, which reduces
the RAM footprint required for the LED strip data.
The implementation is optimized with a fast path for the common 8-bit
symbol case, while a generic bit-packing loop handles all other
widths.
Signed-off-by: Wai-Hong Tam <waihong@google.com>
In order for samples/boards/nxp/mimxrt1060_evk/system_off to work, a
soft-off power state is needed.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Added tag protocol definition and binding. Also introduced
zephyr,dsa-port compatible for future tag protocol driver Kconfig
dependency checking.
Updated existed dts.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The SNVS RTC can act as a wakeup source, re-use pm.yaml properties and
remove the Kconfig symbol.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Remove INPUTMUX interrupt assignments for PINT and GPIO peripherals.
Remove gpio0 DT node.
As the GPIO peripherals can be secured on the mimxrt798s, accesses from
the cm33_cpu0 and hifi4 are mutually exclusive, so the GPIO0 will stay
enabled in the cm33_cpu0 domain.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
This property allows a user to specify the operation of a
pin in sleep mode.
By default, pins are configured to be output low in sleep mode.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The nPM1300 datasheet featured wrong soft start current values which
were also used in the DTS bindings for its regulator driver. This fixes
the values aligning them with the next release of the document.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Introduce the ACE 4.0 architecture, along with support for the NVL and
NVL-S platforms within the Intel ADSP framework in the Zephyr project.
This update includes:
- Addition of ACE 4.0 architecture configurations in Kconfig and
Kconfig.intel_adsp.
- Inclusion of device tree source files for NVL and NVL-S platforms,
defining CPU, memory, and peripheral configurations.
- Updates to driver files to support ACE 4.0 specific features,
including DMIC and SSP configurations.
- Introduction of new header files for ACE 4.0, detailing boot,
interrupt, IPC, power, and shim functionalities.
- Modifications to the CMakeLists.txt to include ACE 4.0 MMU support.
- Addition of default configurations for NVL and NVL-S platforms in
Kconfig.defconfig.ace40.
The NVL and NVL-S platforms are part of the Nova Lake series, targeting
advanced audio processing capabilities. ACE 4.0 introduces enhanced DSP
capabilities and advanced power management features, improving audio
stream handling and synchronization compared to ACE 3.0.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit to initial support dts SoC layer on RX261
Signed-off-by: Hau Ho <hau.ho.xc@bp.renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Use HAL functions, which also wait for reset to complete.
Remove unused register size and active-low DT props.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
