Even though the USB driver does not support multi-instance yet, out-of-tree
or custom boards may want to use the USB2 instance instead of USB1, which
is not currently possible because its node is not declared.
Add missing USBOTGHS2 and corresponding USBPHYC2 nodes to STM32N6 series
root DTSI file.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Adds the pinctrl node and encapsulates the port nodes within
the pinctrl node for pic32cz ca series of socs, and updates
the binding file
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
Use ring indicator to wake up the CMUX device
from sleep.
Only used for runtime power management, but same event
could be used for initiating idle -> connected as well.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
CMUX driver can enable the support for idle-timer in
devicetree and can be requested to shut down the pipe
during sleep.
Then UART backend put the actual device into sleep when
pipe is closed.
Waking up is requested by sending data to DLC pipe
or by manually opening the uart_pipe.
Modem may request similar wake-up by a RING interrupt which
would open the same pipe.
When UART is powered and pipe is not closed, CMUX wake-up
procedure is automatic. Either end may initiate the wake-up.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
Add eim, erm and edac instance for frdm_mcxa153, frdm_mcxn236,
frdm_mcxn947, frdm_mcxe247 and frdm_mcxe31b.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
Add edac driver for NXP's ERM and EIM peripherals. It can inject ECC
error to specific channel within EIM and then report the error address,
syndrome and count within ERM.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
Add the "st,stm32u5-pwr" compatible to the Power Controller node in the
DTSI for STM32U5 series.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Please note that when performing conversions,
the selected channels must all be of the same type
(either ADC raw or V2T.)
Mixing ADC and V2T channels in a single conversion sequence is
not supported.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Fixes the max3421e devicetree compatible to follow the convention of
using a hyphen rather than an underscore as the word separator.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Many dts/dtsi files where its dt-bindings are in-tree
do not include zephyr prefix in the #include path.
Add it to make it consistent globally.
Some dt-bindings that resides in hal can not be changed.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
To enhance throughput performance on the SiWx91x series, Added
some Siwx91x configurations by deafult.
Signed-off-by: Rahul Gurram <rahul.gurram@silabs.com>
Properties in bclk nodes were defined after the bclkout subnode,
disk subnode was defined before properties in a few boards DTS files
which violates the Devicetree Specification v0.4, section 6.3:
"Nodes may contain property definitions and/or child node definitions.
If both are present, properties shall come before child nodes."
This caused the Device Tree Compiler error:
"Properties must precede subnodes. Unable to parse input tree"
This commit moves nested nodes after properties,
fixing the syntax error and ensuring compliance with
the Devicetree Specification.
Signed-off-by: Stanislav Bobokalo <stanislav.b@embedd.it>
Added dts binding for Nordic Tamper Controller with
property to configure SWD pins as GPIOs.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
- Add sifli and analog definitions
- Modify the drive-strength definition to use the original register
definition instead of the physical current value, as different I/O
pins may have different definitions
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
We add MEC165xB chip device tree files. We are sharing the
same base mec5.dtsi which required modifications due to
peripherals not present in MEC165xB.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add ITCM and DTCM memory region definitions to the common STM32H7
devicetree.
ITCM: 64 KB @ 0x00000000
DTCM: 128 KB @ 0x20000000
Signed-off-by: Ibrahim Abdalkader <i.abdalkader@gmail.com>
Expose internal temperature sensor for rv-3032-c7. Driver is reporting
temperature from internal deice sensors and have HIGH an LOW temperature
treshhold which are triggering interrupts. I2C communication and IRQ are
handled from parent MFD driver.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Expose timer functionality from rv-3032-c7 via counter api.
I2C communication and IRQs are arbitrated via MFD parent driver
for rtc, sensor and counter at once.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Rework rv3032 implementaion to use MFD driver unstead of local
implementaion for I2C access and Interrupt managements. This way
could be utilized parts which are not implemented because did not fit
in to RTC api - counter and temperature sensor. To have propper
sincronization arbitration is need which is handled from mfd_rv3032.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Remove backup flag from RTC driver and move it to parent instead.
RTC driver still can access the values of the flags but MFD need
to know what is expected in term of initial behaviour.
Some assumptions done in RTC driver are causing inconsistant behaviour.
We cannot assume that the RTC alarms and notifications need to be
cleaned only if POR bit is triggered. We can have situation where
whole system go throigh soft restart and need to zero RV3032, so driver
need to have option to allow that kind of behaviour.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Remove gpio-int since interrupts will be managed from MFD driver
insted, acticting like dispatcher for interrupts.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Add MFD driver for managing rv3032 functionality which did not fit RTC
api. That way are implemented part which otherwise will not be used:
- RTC
- counter/timer
- temperature sensor
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Update all `vrefint-cal-addr` properties in STM32 DTSI to comply with DTS
Coding Style which says that "hex values in properties should use lowercase
hex".
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Update all `cal-addr` properties in STM32 DTSI to comply with DTS Coding
Style which says that "hex values in properties should use lowercase hex".
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Update all `reg` properties in STM32 DTSI to comply with DTS Coding Style
which says that "hex values in properties should use lowercase hex".
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add initial board support for the Space Cubics SC-OBC Module V1. The
hardware is based on an AMD Versal AI Edge VE2302 and a Microchip
IGLOO2. This Zephyr port runs on the Versal device’s Real-Time Processing
Unit (dual Arm Cortex-R5F).
This commit is the first in the series and only supports the basic devices
needed to run samples/hello_world and samples/philosophers. Specifically,
it adds the Cortex-R5F, UARTs, and the GIC interrupt controller.
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Use devicetree to provide the system clock frequency for S32K3
instead of hardcoding it in board defconfigs.
- Add clock-frequency to /cpus/cpu@0 in nxp_s32k344_m7.dtsi using
DT_FREQ_M(160).
- Define DT_SYSCLK_PATH and derive SYS_CLOCK_HW_CYCLES_PER_SEC from
the sysclk node via dt_node_int_prop_int() when CORTEX_M_SYSTICK.
- Remove CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC from mr_canhubk3
This keeps the clock configuration in a single SoC-level place,
aligns S32K3 with other NXP Cortex-M SoCs, and ensures both the
MCUboot and application builds share the same
SYS_CLOCK_HW_CYCLES_PER_SEC.
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Introduce DT bindings for on-chip C40 flash and its controller
and describe their corresponding nodes in nxp_s32k344_m7.dtsi.
- Binding: dts/bindings/mtd/nxp,c40-flash.yaml
Erase/write block sizes.
- Binding: dts/bindings/flash_controller/nxp,c40-flash-controller.yaml
Describe flash device (child) ranges
- SoC nodes: With the new compatible and geometry
properties. Keep status = "disabled" at the SoC level
so boards opt-in.
This prepares the platform for using Zephyr’s flash API / FLASH_MAP /
MCUboot with internal code flash.
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Add device tree node for MU instances that will be used by HSE and RTU
for s32z270.
Add support hash crypto for NXP S32 with Algo 2:
SHA224, SHA256, SHA384 and SHA512.
Add support cipher crypto with ECB, CBC and CTR mode by using ram key
catalog.
Add support 128/256 bits ram key length.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
The INA232 is another device in the INA2XX family and is very similar
to the already implemented INA230 and INA236. The main difference
between the INA232 and the INA236 is that the INA232 does not have a
Device ID register. Because of these similarities, it is implemented
in the ina230.x files in the same way as the IN236. Modifications to
the corresponding tests are included as well.
Signed-off-by: Johannes Meyer <johannes.meyer@intego.de>
Add the support of the mailbox IPCC1 for communication between
the Cortex-M33 and the Cortex-A35
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
On the STM32MP2 series, the IPCC clock is managed at the system
level by the CPU responsible for system configuration.
In topologies where the Cortex-M33 acts as a companion processor, it
cannot enable the IPCC clock.
This update makes the IPCC clock optional in both the device tree
and the driver.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
