Commit graph

8801 commits

Author SHA1 Message Date
Jose Alberto Meza
b5a39b896b dts: arm: microchip: mec1501: mec172xnsz: Remove pinctrl from SoC dts
Remove pinctrl from device tree since it is not required
when internal oscillator is used.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2024-02-06 18:56:27 +01:00
Jose Alberto Meza
c909915cda dts: bindings: clock: pinctrl is not required for all clock options
Pinctrl is not required when internal oscillator is used

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2024-02-06 18:56:27 +01:00
Jose Alberto Meza
a0c64636e1 dts: arm: mec152x: Allow to use VCI pins as GPIOs
Allow to VCI pins to be used as GPIOS using zephyr user device
tree node entry.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2024-02-05 14:51:44 -05:00
Juliane Schulze
1683f1913b drivers: Add support for TI TMAG5273 3D Hall sensor
Product Homepage:
https://www.ti.com/product/TMAG5273

Datasheet:
https://www.ti.com/lit/ds/symlink/tmag5273.pdf

Tested on a custom hardware with nRF52840.

Signed-off-by: Juliane Schulze <juliane.schulze@deveritec.com>
2024-02-05 13:23:24 -06:00
Joel Guittet
8f267065f2 dts: bindings: fix gc9x01x display documentation
The bindings documentation contains a deprecated pixel-format.

Signed-off-by: Joel Guittet <joelguittet@gmail.com>
2024-02-05 09:38:57 +00:00
Daniel DeGrasse
9001512e1f dts: arm: nxp: nxp_rt1010: provide flexspi clock source
Add FlexSPI clock source to RT1010 devicetree definition for FlexSPI
node, to match FlexSPI clock source defined on standard FlexSPI dt node
that is removed in the RT1010 devicetree.

Fixes #68488

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-02-02 13:49:48 -06:00
Abderrahmane Jarmouni
32fd2f57b1 drivers: display: stm32_ltdc: fix for stm32f429i_disc1
Display is not working on STM32F429i-DISC1 board because
display_blanking_off() needs to be sent to ILI9341 device, but it's sent
to LTDC instead which does not implement it.
This patch adds a LTDC DT property that provides the pHandle of the
display's own controller so that display_blanking_off/on are forwarded to
it when they are called by an application.

Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
2024-02-02 19:54:45 +01:00
Juliane Schulze
34cb22e919 sensors: Add driver for Vischay VCNL36825T Proximity Sensor
Driver for the Vishay VCNL36825T including power management support.

Signed-off-by: Juliane Schulze <juliane.schulze@deveritec.com>
2024-02-02 10:51:10 -06:00
Andrzej Głąbek
1606f65972 dts: nordic: Include input-event-codes.h from nrf_common.dtsi
... so that there is no need to include that header individually
for every added board based on an nRF SoC.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2024-02-02 16:40:11 +01:00
Andrzej Głąbek
50d56c9503 dts: Add initial support for nRF54H20 EngA SoC
Add definition of the nRF54H20 SoC revision EngA with its Application,
Radio, and Peripheral Processor (PPR) cores and basic peripherals:
GRTC, GPIOs, GPIOTE, and UARTs.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2024-02-02 16:40:11 +01:00
Andrzej Głąbek
6bce789829 dts: Add and extend Nordic bindings needed for nRF54H20
Add a set of bindings that will be used in the nRF54H20 SoC definition.
Extend the existing GPIOTE binding with properties needed for this SoC.
Also do a tiny clean-up in the bindings added recently for nRF54L15
(HFXO and LFXO).

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2024-02-02 16:40:11 +01:00
Grzegorz Swiderski
3cfa2296a6 dts: Move nrf_common.dtsi to the common directory
... so that it can be included by ARM and RISC-V cores. For the same
reason, SysTick can no longer be disabled in this common file.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2024-02-02 16:40:11 +01:00
Tomas Galbicka
069bcbcb7f drivers: mbox: Add NXP Mailbox driver for mbox
This adds new NXP mailbox driver for MBOX device.

NXP mailbox IP driver supports sending data between cores.
It uses 32 bit register to trigger irq to other core.
This driver implementation uses 4 bits for channel selection of
triggering mode, 4 bits for channel selection of data transfer and
rest 24 bits for data.

NXP mailbox IP Reference Manual UM11126, Chapter 52.
https://www.nxp.com/webapp/Download?colCode=UM11126

Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
2024-02-02 09:31:33 -06:00
Linus Isberg Martinsson
23d3114db3 dts: boards: stm32h562: Add missing UART7 and UART8
UART7 and UART8 instances were missing in the device tree for
STM32H562.

Signed-off-by: Linus Isberg Martinsson <isberg.linus@gmail.com>
2024-02-02 09:29:18 -06:00
Francois Ramu
cd239bf8f1 dts: bindings: flash controller stm32 qspi nor flash reg property
Address and size are given by the DTS register property
of the qspi nor. The size Property becomes useless.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-02-02 13:48:18 +01:00
Francois Ramu
078e32fa37 dts: bindings: flash controller stm32 ospi nor flash reg property
Address and size are given by the DTS register property
of the ospi nor. The size Property becomes useless

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-02-02 13:48:18 +01:00
Manuel Argüelles
1b302f51ea soc: arm: nxp_s32: s32k1: add support for RTC
Add support for the Real Time Clock (RTC) counter.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2024-02-02 12:43:00 +01:00
Chun-Chieh Li
bc1a988f9d drivers: usb: device: support Nuvoton NuMaker series USBD controller driver
1. Configure 'core-clock' to 192MHz to generate necessary 48MHz
2. Support workaround to disallowing ISO IN/OUT EPs to be assigned
   the same EP numbers

Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
2024-02-02 10:07:43 +01:00
Sumit Batra
286a3ce37f drivers: eth: phy: tja1103: Handle link change
drivers: eth: phy: tja1103: Handle link change
These changes enable -
TJA1103 driver to gracefully handle Link connect or disconnect events
between Ethernet PHY and its link partner and notify it to the
upper network layers

Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
2024-02-01 14:29:43 -06:00
Eve Redero
7f5b332b58 doc: fix index typo in sdl bindings
Label "key1" is used twice in the exemple, renaming to "key2".

Signed-off-by: Eve Redero <eve.redero@gmail.com>
2024-02-01 14:32:03 +00:00
Daniel Gaston Ochoa
cc9c90c767 devicetree: spi: stm32h7: Allow to enable SPI FIFO from DT
Allow to enable/disable the STM32 SPI FIFO usage from
devicetree.

Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
2024-02-01 14:31:12 +00:00
Martin Åberg
f033f31728 soc/gr716a: Enable SPIMCTRL support on LEON GR716A
GR716A has two SPIMCTRL SPI controllers.

This adds the SPIMCTRL description to the DTS and makes the SPI
option available in the kernel configuration.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2024-02-01 14:06:38 +01:00
Martin Åberg
e13d4a14df drivers/spi: Add support for GRLIB SPIMCTRL
This adds support for the GRLIB SPIMCTRL SPI controller used in LEON and
NOEL-V systems. SPIMCTRL can operate in two different modes: In the
default mode it allows memory-mapped read access to the flash data. When
set in the user mode, it can be used to generate SPI bus transactions.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2024-02-01 14:06:38 +01:00
Daniel DeGrasse
5957da5830 dts: arm: nxp: rt1064: setup rx-clock-source for XIP flash
Setup rx-clock-source for XIP flash. When running from RAM, the FLEXSPI2
attached SIP flash will be reconfigured, so we must ensure the
configuration used for it is valid.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-02-01 10:57:35 +01:00
Daniel DeGrasse
f81113e948 drivers: clock_control: add support for FlexSPI reclock on NXP iMX RT10XX
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.

Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-02-01 10:57:35 +01:00
Harshit Agarwal
f4a8ec3f93 dts: mbox: add PolarFire SoC mailbox interface
Add Microchip's PolarFire SoC mailbox node.

Signed-off-by: Harshit Agarwal <harshit.agarwal@microchip.com>
2024-02-01 04:33:16 -05:00
Harshit Agarwal
ccb2a0df04 dts: riscv: add PolarFire SoC system controller QSPI interface
Add support for Microchip's PolarFire SoC system controller QSPI
interface.

Signed-off-by: Harshit Agarwal <harshit.agarwal@microchip.com>
2024-02-01 04:33:16 -05:00
Daniel DeGrasse
3dbbb73319 drivers: display: ili9xxx: convert to MIPI DBI API
Convert ili9xxx display drivers to use MIPI DBI API. Due to the fact
this change requires a new devicetree structure for the display driver
to build, required devicetree changes are also included in this commit
for all boards and shields defining an instance of an ili9xxx display.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-01-31 16:01:45 +00:00
Daniel DeGrasse
571de47e16 drivers: mipi_dbi: add SPI based MIPI DBI mode C driver
SPI controllers can easily implement MIPI DBI mode C, with the help of
GPIO pins for the reset and command/data signals. Introduce a MIPI DBI
compliant SPI driver, which emulates MIPI DBI mode C (SPI 3 and 4 wire).

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-01-31 16:01:45 +00:00
Daniel DeGrasse
3ab6572856 drivers: mipi_dbi: introduce MIPI DBI driver class
Introduce MIPI DBI driver class. MIPI DBI devices encompass several
interface types. All interfaces have a data/command, reset, chip select,
and tearing effect signal

Beyond this, MIPI DBI operates in 3 modes:

Mode A- 16/8 data pins, one clock pin, one read/write pin. Similar to
Motorola type 6800 bus

Mode B- 16/8 data pins, one read/write pin. Similar to Intel 8080 bus

Mode C- 1 data output pin, 1 data input pin, one clock pin.
Implementable using SPI peripheral, or MIPI-DBI specific controller.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-01-31 16:01:45 +00:00
Armando Visconti
4828340b92 drivers/sensor: add support to LIS2DE12 accelerometer
The LIS2DE12 is an ultra-low-power high- performance three-axis
linear accelerometer belonging to the “femto” family with digital
I2C/SPI serial interface standard output.

This driver is based on stmemsc HAL i/f v2.3

https://www.st.com/en/datasheet/lis2de12.pdf

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2024-01-31 15:39:45 +01:00
Armando Visconti
6d65738126 dts/bindings/sensor: lis2du12: fix macros typos
Fix few macros typos.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2024-01-31 15:39:45 +01:00
Najumon B.A
8b3bd500cd dts: rtc: mc146818: add acpi hid support in yaml file
add acpi hid support for mc146818 yaml file. Currently this added
for acpi test case support.

Signed-off-by: Najumon B.A <najumon.ba@intel.com>
2024-01-31 15:03:06 +01:00
Najumon B.A
34a2fbfba1 drivers: pci: update prt retrieve based on pnp id
update prt retrieve based on acpi pnp id instead of acpi device
path/name

Signed-off-by: Najumon B.A <najumon.ba@intel.com>
2024-01-31 15:03:06 +01:00
Najumon B.A
940c66f82e boards: x86: add pci controller node with acpi pnp id
add acpi pnp/hw id for pcie node to enable support for retreive
interrupt routing information for pci legacy interrupt via acpi

Signed-off-by: Najumon B.A <najumon.ba@intel.com>
2024-01-31 15:03:06 +01:00
Najumon B.A
2f3fb49d76 lib: acpi: add device resource enum support
add device resource enumaration support such as irq and mmio.

Signed-off-by: Najumon B.A <najumon.ba@intel.com>
2024-01-31 15:03:06 +01:00
Gerard Marull-Paretas
e57ad265fb dts: bindings: misc: add nordic-nrf-ficr-client
So that FICR clients can include this file instead of redefining FICR
properties every time.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-31 13:40:59 +00:00
Gerard Marull-Paretas
ed0fc03f67 dts: bindings: arm: nordic,nrf-ficr: add #nordic,ficr-cells
Add a new #nordic,ficr-cells property, so that we can specify a FICR
offset in a phandle-array, e.g.

  nordic,ficrs = <&ficr 0xff>;

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-31 13:40:59 +00:00
Gerard Marull-Paretas
6ec2dbf8ee dts: bindings: nordic,nrf-ficr: move to misc folder
It's not related to ARM.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-31 13:40:59 +00:00
Naga Sureshkumar Relli
c5818d4b3f dts: riscv: introduce Polarfire SOC SPI interface
Add support for the Microchip Polarfire SOC SPI interface.

Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
2024-01-31 06:36:21 -05:00
Filip Kokosinski
e08a77c8fe dts/riscv/efinix: add the efinix,vexriscv-sapphire compatible string
This commit adds the `efinix,vexriscv-sapphire` compatible string. This
helps identify the core type from the final devicetree alone.

The VexRiscv core configuration is specific to the Efinix Sapphire SoC.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
Filip Kokosinski
0458ac064c dts/riscv/openisa: add compatible strings for the RI5CY cores
This commits adds two new compatible strings:
* `openisa,ri5cy`
* `openisa,zero-ri5cy`

Adding these two new compats help identify the specific core defined by the
cpu node from the devicetree alone.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
Filip Kokosinski
6297f3640f dts/riscv/andes: add andestech,andescore-v5 compatible string
This commit adds the `andestech,andescore-v5` compatible string. This helps
identify the core tpye form the final devicetree alone.

Andes doesn't define which core type from the v5 series the AE350 SoC uses,
so we're using the whole series name here.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
Filip Kokosinski
f80347ec95 dts/riscv/lowrisc: add lowrisc,ibex compatible string
The OpenTitan Earlgrey SoC has the lowRISC Ibex CPU core. This commits adds
the `lowrisc,ibex` compatible string to reflect that.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
Filip Kokosinski
b5859ece4d dts/riscv/microchip: add missing cpu nodes compats in mpfs.dtsi
The cores used in the `mpfs.dtsi` file are:
* 1x SiFive E51 (RV32)
* 4x SiFive U54 (RV64)

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
Filip Kokosinski
a3a4bf915b dts/riscv/litex: add litex,vexriscv-standard compatible string
This commit adds the `litex,vexriscv-standard` compatible string. This
helps identify the core type from the final devicetree alone.

The VexRiscv core version is defined in this repository:
https://github.com/litex-hub/zephyr-on-litex-vexriscv.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
Filip Kokosinski
28c7674c66 dts/riscv: add riscv compatible string where it's missing
This commit adds the `riscv` compatible string to cpu nodes where it is
currently missing. This is convention is already followed by some cpu
nodes.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
Filip Kokosinski
17670be2cc dts/riscv: remove the timebase-frequency property
The `timebase-frequency` is not defined by any of the YAML binding files.
There was a discussion in #37420 to add this property, but in the end it
was rejected. This resulted in the #37685 feature request being created.

As of now, this property is not documented anywhere so this commit removes
it from the RISC-V devicetrees, as RISC-V is the only architecture that is
currently defining it - and even in RISC-V not all platforms do that.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
Filip Kokosinski
c592690649 dts/bindings: move RISC-V cores bindings to dts/bindings/cpu/
This commit moves the bindings of RISC-V cores from `dts/bindings/riscv` to
`dts/bindings/cpu`. This change aligns the bindings of RISC-V cores with
other architectures.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
Mykola Kvach
739ec3072b drivers: serial: add missed binding for xen dom0 consoleio driver
Add missed binding and appropriate changes for Xen Dom0/Dom0less
UART driver.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
2024-01-30 18:52:13 -05:00