When compiling, the following warning occurs:
Warning (simple_bus_reg): /soc/sai1@452005804: simple-bus unit address
format error, expected "52005804"
Looking at table 3 in the reference manual[1] for the stm32n6 it seems that
the sai1_a address simply had a typo, where a "4" was added in front of the
correct address.
Fix the typo.
[1] RM0486 Rev 2: https://www.st.com/resource/en/reference_manual/rm0486-stm32n647657xx-armbased-32bit-mcus-stmicroelectronics.pdf
Signed-off-by: Emil Dahl Juhl <emil@s16s.ai>
Add tearing effect support for better display synchronization. If
tearing effect is configured in the mipi_dbi device, the display
controller configures its tearing effect register.
Display orientation configuration is updated to also rotated the
direction of the display pixel vertical scanline, such that scan order
matches the display orientation.
Signed-off-by: Christian Rask <christianrask2@gmail.com>
Add tearing effect support for better display synchronization. This
allows users to configure an external interrupt on falling/rising edges
of the gpio connected to the display controllers tearing effect pin.
See dt-bindings/mipi_dbi/mipi_dbi.h for details of how this works for
mipi_dbi display interfaces.
Signed-off-by: Christian Rask <christianrask2@gmail.com>
Change the compatible of CPU core for qemu_rx, rx130 and rx261
target accroding to the change of dt-binding for rx cpu core
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Adding bindings for rx cpu core version and remove the redundant
compatible in the qemu_rx and rsk_rx130 boards
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
The wdog0 unit address and reg entry pointed to the secure
alias, while the SMU was configured to expect the non-secure
alias.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Silicon Labs controller with integrated radio each rely on a specific
binary blob (RAIL library) for using the EFR32 radio subsystem.
This commit adds support for the Silicon Labs BGM240SA22VNA SoC.
Signed-off-by: Ephraim Westenberger <ephraim.westenberger@gmail.com>
Due to a mismatch in naming of debug jtrst pin name
(compared to hal_stm32) all boards based on stm32wba5x
are not compiling.
This temporary fix will solve this issue until a systematic
approach will be put in place.
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
1. Added new boolean type 'nxp,internal-voltage-regulator-en'
and 'nxp,chop-oscillator-en' properties for 'nxp,vref'.
The user can use these properties to improve the stability
and accuracy of the VREF output voltage.
2. Added properties 'nxp,current-compensation-en' and
'nxp,internal-voltage-regulator-en' and 'nxp,chop-oscillator-en'
for LPC55S3x, MCXN23x, MCXN94x, and MCXW7x VREF node.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
RP2350 adds four more PWM slices from the eight available on RP2040,
which are only broken out to package pins on RP2350B. This change fixes
the driver to support the correct number of slices on RP2350.
Tested by confirming that PWM can correctly be configured on GPIO 44 of
RP2350B.
Signed-off-by: Peter Marheine <peter@taricorp.net>
Which does not have HW support for it, as stated by ST here:
https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html
"
The STM32U575 portfolio offers from 1 to 2 Mbytes of flash memory
and from 48- to 169-pin packages.
The STM32U585 is available with 2 Mbytes of flash memory and provides
an additional encryption accelerator engine (AES, PKA, and OTFDEC).
"
All the U5 SoC have a hash HW accelerator (even the ones which don't
have crypto support: U535XX, U575XX, U59XXX and U5FXXX).
The hash node is therefore moved directly inside the stm32u5.dtsi.
Signed-off-by: Philémon Jaermann <p.jaermann@gmail.com>
1. Upgrade the ATCDMAC driver to make it compatible with multiple
ATCDMAC series drivers.
2. Rename the driver from ATCDMAC300 to ATCDMACX00.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
The STM32 QUADSPI peripheral allows to configure, in clock cycles, the
duration the chip select signal must stay high between each command sent
to the flash memory controller (QUADSPI_DCR_CSHT).
Currently, this value is set by the flash driver to 1 clock cycle in
single flash mode and 3 clock cycles in dual flash mode. However, the
minimal duration depends on the flash memory (typically 30-50 ns) and
the number of clock cycles on the QSPI's clock frequency. So, adding
this new property allows to select the value of CSHT to match the
requirement of the flash memory used. Also note that in single flash
mode, the current configuration is out-of-spec for most flash memories.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
Add support for timer kernel clock for STM32U0.
Contrary to other series, on U0, TIMPCLK is always equal to PCLK, so no
need to define it, we can use PCLK directly.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32H7RS.
Define a new property for the timer prescaler in the RCC binding of H7RS.
Also fix the clock bus of TIM16 and TIM17 (they are on APB2 instead of 1)
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32H7.
Define a new property for the timer prescaler in the RCC binding of H7.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32H5.
Define a new RCC binding for H5 with the timer prescaler property (timpre).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32F7.
The STM32F7 RCC clock driver complies with st,stm32f4-rcc
driver variant.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
