Add support for timer kernel clock for STM32F4.
Define a new RCC binding to add the timer prescaler property (timpre).
This new binding is used for all STM32F4 except F405/F407/F415/F417 who do
not support it.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32F3.
Also reorganizes the timer instances:
- TIM3 is not available on F301, F318, F302x6 or x8, but is available for
all others
- TIM4 is available on F302xB and higher, F303xB and higher, F358, F398,
F373 and F378
- TIM7 is not available on F301, F318, F302, but is available for all
others
- TIM8 is only available on F303xB and higher, F358 and F398
- TIM20 is only available on F303xD and xE,and on F398
Depending of the SoC version, some timers have access to one or two
distinct clock sources. Timers with NO_SEL selection only have access
to the base TIMPLCKx clock, those defined with TIMx_SEL(0) can use another
source clock: STM32_SRC_TIMPLLCLK. That's why some clocks are redefined.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit sets the interrupt mode to high-level
triggered, as fifo mode is enabled by default
(CONFIG_SPI_ITE_IT51XXX_FIFO_MODE=y) and the fifo
mode only supports high-level triggered.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Add initial device tree support for the Rockchip RK3588 SoC.
The DTS describes:
- Four Cortex-A55 cores with PSCI enable-method
- GICv3 interrupt controller
- ARMv8 timer
- UART2 and UART3 (disabled by default)
Signed-off-by: Guowei Li <15035660024@163.com>
The OTG_HS PHY from stm32u5a5xx device require the correct reference
clock frequency selction in SYSCFG_OTGHSPHYCR. The current default is
hard coded to 16Mhz (which matches the development board crystal).
However, a custom board my require a different crystal and then the
USB will not work. This add a required field in the
st,stm32u5-otghs-phy binding to force user to select the correct
clock reference. The current nucleo_u5a5zj_q baord was updated to
reflect the mandatory field.
Signed-off-by: BUDKE Gerson Fernando <gerson.budke@leica-geosystems.com>
Add include of the stm32l4+ specific clock bindings in
stm32l4p5.dtsi in order to let all stm32l4+ benefit from it.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The STM32G4 variants g473, g474, g483, g484, g491 and g4a1 do support QSPI
interface. All mentioned variants include the stm32g491.dtsi.
Signed-off-by: Andreas Schmidt <andreas.schmidt@dormakaba.com>
It is now possible to enable CONFIG_UART_INTERRUPT_DRIVEN for mspm0
uart driver.
Signed-off-by: Jackson Farley <j-farley@ti.com>
Co-authored-by: Hans Binderup <habi@bang-olufsen.dk>
The definition of the EM3 energy mode is that software switches
off the LFRCO and LFXO before entering deep sleep. On Series 2,
oscillators are clocked on-demand based on peripheral requests
from hardware. Requesting EM3 will result in EM2 if any active
peripheral uses one of the oscillators, and requesting EM2
will result in EM3 if no peripherals use the oscillators.
In version 2025.6 of the HAL, this was reflected in the API
of the power manager by making EM3 an alias of EM2. Reflect
this in Zephyr by removing the separate EM3 power state.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
