dts: xtensa: Add DT for SoC mimxrt685s/hifi4
Add DT for the mimxrt685s/hifi4 SoC (i.MX RT685's HiFi 4 DSP core). Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
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217
dts/xtensa/nxp/nxp_rt685_hifi4.dtsi
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217
dts/xtensa/nxp/nxp_rt685_hifi4.dtsi
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/*
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* Copyright 2025 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/xtensa.dtsi>
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#include <mem.h>
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#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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/ {
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chosen {
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zephyr,sram = &adsp_data;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <0>;
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};
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};
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soc {
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interrupt-parent = <&core_intc>;
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/*
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* Dummy interrupt controller node - IRQs are handled directly by platform code.
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* INPUTMUX (IRQ allocation) is set up in mimxrt685s/hifi4 soc.c.
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*/
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core_intc: core_intc@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0x00 0x400>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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itcm: memory@24020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x24020000 DT_SIZE_K(64)>;
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adsp_reset: memory@24020000 {
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reg = <0x24020000 DT_SIZE_K(1)>;
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};
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};
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dtcm: memory@24000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x24000000 DT_SIZE_K(64)>;
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};
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ram0_cached: memory@200000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x00200000 DT_SIZE_K(512)>;
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};
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ram0_noncached: memory@20400000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x20400000 DT_SIZE_K(512)>;
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adsp_text: memory@20400000 {
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reg = <0x20400000 DT_SIZE_K(256)>;
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};
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adsp_data: memory@20440000 {
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reg = <0x20440000 DT_SIZE_K(256)>;
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};
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};
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peripheral: peripheral@40000000 {
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ranges = <0x0 0x40000000 0x10000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clkctl0: clkctl@1000 {
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/* FIXME This chip does NOT have a syscon */
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compatible = "nxp,lpc-syscon";
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reg = <0x1000 0x1000>;
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#clock-cells = <1>;
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};
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gpio: gpio@100000 {
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reg = <0x100000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,lpc-gpio";
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gpio0: gpio@0 {
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reg = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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int-source = "pint";
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compatible = "nxp,lpc-gpio-port";
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};
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gpio1: gpio@1 {
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reg = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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int-source = "pint";
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compatible = "nxp,lpc-gpio-port";
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};
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};
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pint: pint@25000 {
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compatible = "nxp,pint";
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reg = <0x25000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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interrupts = <7 0 0>, <8 0 0>, <9 0 0>, <10 0 0>,
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<11 0 0>, <12 0 0>, <13 0 0>, <14 0 0>;
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num-lines = <8>;
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num-inputs = <64>;
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};
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iocon: iocon@4000 {
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compatible = "nxp,lpc-iocon";
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reg = <0x4000 0x1000>;
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pinctrl: pinctrl {
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compatible = "nxp,rt-iocon-pinctrl";
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};
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};
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clkctl1: clkctl@21000 {
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compatible = "nxp,lpc-syscon";
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reg = <0x21000 0x1000>;
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#clock-cells = <1>;
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};
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dma1: dma-controller@105000 {
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compatible = "nxp,lpc-dma";
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reg = <0x105000 0x1000>;
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interrupts = <29 0 0>;
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dma-channels = <33>;
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status = "disabled";
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#dma-cells = <1>;
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};
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i3c0: i3c@36000 {
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compatible = "nxp,mcux-i3c";
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reg = <0x36000 0x1000>;
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#address-cells = <3>;
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#size-cells = <0>;
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interrupts = <6 0 0>;
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clocks = <&clkctl1 MCUX_I3C_CLK>;
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clk-divider = <2>;
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clk-divider-slow = <1>;
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clk-divider-tc = <1>;
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status = "disabled";
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};
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flexcomm0: flexcomm@106000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x106000 0x1000>;
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clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>;
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interrupts = <5 0 0>;
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status = "disabled";
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};
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flexcomm1: flexcomm@107000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x107000 0x1000>;
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interrupts = <31 0 0>;
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clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>;
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status = "disabled";
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};
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flexcomm3: flexcomm@109000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x109000 0x1000>;
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interrupts = <30 0 0>;
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clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>;
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status = "disabled";
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};
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mbox: mbox@111000 {
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#mbox-cells = <1>;
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compatible = "nxp,mbox-imx-mu";
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reg = <0x111000 0x1000>;
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interrupts = <27 0 0>;
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rx-channels = <4>;
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status = "disabled";
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};
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};
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};
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};
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