Assigning power domain to the GP DMA.
NOTE: Only controllers 1 and 2 are under IO_0 domain, controller 0 is
under HUB-ULP domain.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Support for the measuring the CPU die temperature
for the ESP32 targets S2,C3. The ESP32 support
was ommited due to lack of offset calibration.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Serial speeds listed in device tree did not reflect
what driver supports.
2M and 500K were missing while
1200, 2400 and 460800 were present while not supported.
This change synchronized dts with driver code:
drivers/serial/uart_smartbond.c
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
PCA9420 PMIC offers of multiple operation states, or DVS (Dynamic
Voltage Scaling). Such states may be automatically changed by hardware
using MODESEL0/1 pins. Certain MCUs allow to automatically configure
certain output pins when entering low power modes so that PMIC state is
changed without software intervention. This means that application just
needs to configure the voltages for each state using
`nxp,modeN-microvolt`, set `nxp,enable-modesel-pins` in devicetree and
forget about configuring regulators.
This patch introduces a new _parent_ API to expose such functionality in
a vendor agnostic way. Consider this API as experimental for now, until
we have other usecases.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Most of devicetree properties for regulator, such as:
- regulator-min/max-microvolt
- regulator-min/max-microamp
- regulator-allowed-modes
- etc.
Are meant to specify limits on what consumers may set. They are **NOT**
meant to describe the hardware capabilities. For example, I could have a
BUCK converter that supports 0-5V output voltage, but my circuit may
only allow working on the 2.7-3.3V range.
This patch reworks the API so that the API class layer manages this
information. This is done by drivers collecting all such fields in a
common configuration structure that is later accessed by the class
layer. This simplifies drivers implementation. For example, if A
consumer calls regulator_set_voltage() with a voltage that is supported
but not allowed, driver code won't be called. Similarly, if a regulator
is configured to be `always-on`, enable/disable driver code will never
be called.
Drivers have been adjusted. PCA9420 mode settings have been removed from
devicetree in this commit as they are not actual modes but PMIC states.
This will be refactored in a follow-up commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The stm32G0 device has a one APB peripheral clock bus
but splitted on two RCC registers: RCC_ABPENR1 and RCC_ABPENR2
Peripherals are on one or the other.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The XY Memory is a feature commonly found in DSP processors to increase
the DSP performance. The XY component allows a ARC processor to
implicitly load source operands and store results into a closely coupled
memory using a single instruction.
Add XY memory for ARC EM9D/EM11D processors including em_starterkit,
em_starterkit_em11d. emsdp_em9d, nsim_em, iotdk.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.
This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.
The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
The interrupt-map property specifies both 32-bits values and a phandle;
update the type accordingly.
Update the definition of pcie-host-ecam-generic on qemu arm64 to match
the new type.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Add DTS information for qemu-virt-a53 and qemu-kvm-arm64 for PCIe
controller support. Three new bindings are required for the PCIe
controller in ECAM mode.
The DTS information was extracted from QEMU (dumpdtb) with a PCIe device
attached to the virtual machine (ivshmem)
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
We are about to add UART reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
We are about to add timer reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
To deassert reset in STM32MP1 RCC the driver needs to set the bit in
reset clear register.
This patch extends existing implementation to support this type of
register.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This driver exposes STM32 RCC reset functionality through reset API.
Information about RCC register offset and bit is encoded just like GD32.
The first 5 least significant bits contains register bit number.
Next 12 bits are used to keep RCC register offset. Remaining bits are
unused.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
STM32L4 devices, except STM32L412 STM32L422 STM32L4P5 STM32L4Q5, have
32 4-byte battery-backed RTC backup registers. Other STM32L4 devices
have backup registers in tamper module, not used in Zephyr.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
All STM32L1 devices have 4-byte battery-backed RTC registers, but
they have different number of registers:
STM32L151Xb-a has 5 registers.
STM32L151Xb has 20 registers.
STM32L151Xc, STM32L152Xc, STM32L152Xe have 32 registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Add BBRAM entry for all STM32H7 microcontrollers except STM32H7A3 and
STM32H7B3 which have backup registers in tamper module.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
All supported STM32F3 devices have 4-byte battery-backed RTC registers,
but they have different number of registers:
STM32F303x8 and STM32F334 have 5 registers.
STM32F303xc and STM32F303xe have 16 registers.
STM32F302x8 has 20 registers.
STM32F373 has 32 registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Among supported devices only STM32F031, STM32F051, STM32F072 and
STM32f09x have 5 4-byte battery-backed RTC registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
STM32 battery-backed RAM is organized in 4 byte registers. Number of
registers can vary between models from 5 to 32 registers.
Usually, the registers are part of RTC. On some variants they are part
of tamper module. On STM32F1 the registers are in separate module. For
now, only backup registers from RTC are supported.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Add definitions for DMAs, Digital Audio Interfaces (DAIs) and
the necessary clocks to enable full use of audio peripherals
in the intel_adsp_cavs25_tgph boards.
Link: https://github.com/thesofproject/sof/issues/6710
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
