NXP LPUART IP supports rs485 mode when transceiver driver enable
using RTS. Allow setting rs485 mode up via the "nxp,rs485-mode"
dts property. "nxp,rs485-de-active-low" dts property can be used
for set RTS polarity.
Signed-off-by: Grixa Yrev <GrixaYrev@yandex.ru>
Add the HSI48 clock to the stm32 devices that have this
clock signal.
Within a stm32 family, only few might have the
RCC_HSI48_SUPPORT.
STM32WB has a CLK48 mux.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add zephyr,memory-region compatible and attribute to SOC memory regions,
so that sections will be generated and MPU attributes can be applied.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT1170 and RT1160 CM7 and CM4 cores have the same set of differences.
Merge the DTS files for both CM4 and CM7 cores, to create generic
rt11xx_cm4 and rt11xx_cm7 files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
- Similar to what was done for other parts of the driver, remove any
register specification from Devicetree (modesel-reg/mask)
- Keep all the information in the driver, and define modes as "numbers",
e.g. PCA9420_MODE0: 0, PCA9420_MODE1: 1, etc.
- Bindings provide IC defaults now (all modes allowed 0/1/2/3 and
initial mode set to 0).
- When mode is controlled via the MODESEL0/1 pins (ie directly by an iMX
MCU using the dedicated PMIC_MODE0/1 pins), the driver will not allow
to select a mode (it is not possible). This mode is now enabled by
setting `nxp,enable-modesel-pins` in Devicetree. When enabled, all the
allowed modes are configured to be selectable via pins. When disabled,
mode can be set via I2C (using TOP_CNTL3 MODE0/1_I2C fields)
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add system reset control device (sysrst), so that the drivers can
assert/deassert its reset line through the public reset controller
driver API.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Add bindings for Aspeed AST10x0 reset driver. The reset line can be
de-asserted or asserted through the syscon registers.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Add RX and TX fifo size properties to CDC ACM UART bindings.
This allows per instance settings in contrast to Kconfig
USB_CDC_ACM_RINGBUF_SIZE option. New properties takes the default
size value of USB_CDC_ACM_RINGBUF_SIZE which can be removed
subsequently.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add rgb-is-inverted option to indicate module's pixel-format is
inverting from MADCTL settings of ST7735R controller.
This option intends to implement a workaround for LCD modules
that is the actual screen color was different (inverted)
from the RGB setting in MADCTL property.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Implement a LED driver for Microchip XEC using the breathing,
blinking LED controller. The driver supports LED on, off, and
blink API's. The BBLED block uses the 32768 Hz clock domain
allowing the module to operate in light and deep sleep states.
Blink frequency is 32768 divided by 256 * (prescale + 1) where
prescale is a 12-bit value. Duty cycle is specified by an 8-bit
value where 0 = full off, 127 is 50%, and 255 is full on.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add new variant configuration of it81202cx and it81302cx.
This cx variant of it81xx2 changes are as follows:
1. SRAM size will increase from 60k to 128k.
2. Configurable ILM size is still 60k.
3. Support M extension of RISC-V.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Re-enable the CAAM for entropy
now that the HAL driver has been fixed
Job descriptors must be accessed coherently
between CAAM DMA and core.
The M4 Cores still do not work
because of mpu/cache/kconfig arch complications,
disable caam for M4 cores in DTS
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Remove regulator-fixed-sync specialization, create a single driver that
is always synchronous. The asynchronous part is rarely/never used, so
let's keep things simple for now.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enable RTU System Timer Module (STM) instances on
s32z270dc2_r52 boards. Module clock frequency is fixed to
133.333333 MHz.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
NXP S32 System Timer module includes a 32-bit count-up timer and four
32-bit compare channels with a separate interrupt source for each
channel. The timer is driven by the module clock divided by an 8-bit
prescale value.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Microchip XEC GPIO pins support inverting the output of
alternate pin functions. This feature may be useful for
those peripherals that do not implement output inversion
in the peripheral. GPIO control register pad input and
parallel input register values are not affected by the
function output invert feature. GPIO interrupt detection
of an output is inverted if the invert polarity is enabled.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
add Intel HDA DAI driver
Long device list in dtsi needs to be refactored in the future
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
The driver had a conceptual issue regarding current limitation. PCA9420
is able to limit the current flowing through VIN, ie input current. This
is a global setting, not individual to each regulator. This patch
creates a new DT property: nxp,vin-ilim-microamp to specify such limit.
It is applied when the device is initialized.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Voltage ranges were hardcoded in Devicetree, however, things can be
significantly simplified by using the recently introduce linear ranges
API. All values are now computed using information stored in the driver,
so there is no need to store any lookup table in ROM. Code should now
both be faster in average and consume less ROM.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Maximum current was not specified. Even though not used, yet, it is a
valuable information. Values taken from PCA9420 datasheet, Figure 1
"Simplified block diagram".
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Regulator registers were set for each BUCK/LDO in DT, likely because of
the way the devices were instantiated. When using a generic iterator,
ie, DT_INST_FOREACH_CHILD, there's no way to differentiate the child
being _parsed_. Since instantiation happens now based on child node
names, we are able to know which registers each devices gets assigned at
the driver level. This greatly simplifies Devicetree, and it actually
removes information that is not strictly hardware description from it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Right now the PCA9420 driver instantiates by iterating over all
children. This is somewhat problematic, for a few reasons:
- Since instantiation is generic code, we're forced to put internal
details on Devicetree, e.g. reg-masks. After this change, this will no
longer be necessary.
- We take all children, regardless of what is defined in DT.
While we have no means to validate Devicetree node names as in Linux
dtschema, this approach allows us to have per-child specific
initialization code. This is somewhat similar to the Linux approach.
Note: nodelabels have been removed, since they were not used.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
regulator-allowed-modes/regulator-initial-mode are standard properties
defined in regulator.yaml, so use them.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Import all Linux properties, so that we can maximize compatiblity with
upstream bindings.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Following Linux regulator.yaml, regulator-name is a common property for
all regulators.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Define the octospi node for the stm32l4plus MCUs from
STMicroelectronics.
It is controlled by a OSPIMgr in front of each peripheral.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The sdhc-spi-slot requies an spi bus, but sd nodes (like sdmmc-disk)
cannot be added to it without a warning because it does not declare an
sd bus.
Signed-off-by: JP Sugarbroad <jpsugar@amazon.com>
RT1718S is an i2c-based TCPC chip that supports 3 additional GPIOs.
The pins can be used for USB-C operations e.g. handling FRS, but they
can also work as usual GPIOs.
Add a driver for the RT1718S GPIO and a handler for an alert signal from
the chip. The handler reads the alert register once asserted and calls
the GPIO interrupt handler if needed(Vendor-defined alert).
gpio_rt1718s.c file and "richtek,rt1718s" node collect common properties
and data for all RS1718S functionalities. The file can be extended for
TCPC driver. rt1718s.h file also defines inline functions with i2c
operations common for all drivers. The common header and source files
can be moved to tcpc directories once the tcpc driver is added since it
is the main functionality.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Add drdy_pulsed property in Device Tree in order to select how
data ready irq should behave (either pulsed or latched mode).
Moreover change/fix the API called to set drdy irq mode.
(fix#51944)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Since we can include other binding files at any level (child,
grand-child, etc.) it makes no sense to maintain two copies of pinctrl
props definitions (pincfg-node/pincfg-node-group). Instead,
pincfg-node.yaml defines props at root level, and it is included where
needed, either child-binding or grandchild-binding.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Added i-cache-line-size and d-cache-line-size values
to device tree for cavs and ace platforms. These values
are used by sys_cache_instr_line_size_get and
sys_cache_data_line_size_get functions.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Added to the device tree values of the dma-copy-alignment
and dma-buf-size-alignment attributes.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Added to the device tree values of the dma-copy-alignment
and dma-buf-size-alignment attributes.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
dma-buf-size-alignment: Buffer size alignment required by the DMA
controller.
dma-copy-alignment: Minimal chunk of data possible to be copied
by the controller.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Renamed the dma-buf-alignment field to a more explicit
and descriptive name dma-buf-addr-alignment.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
