Remove wifi patch as it was a temporary location and
new Wi-Fi patch dfu solution will be proposed in next
update.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
Rearrange NS only flash layout, reduce the default NS memory partition
to 192KiB, maximize available memory to use for nrf7120 ns application.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
Add the WWDT0 devicetree node for the MCXL255 CM33 target.
WWDT0 is disabled by default and can be enabled by board or application
devicetree files.
Signed-off-by: Samuel Slesar <samuel.slesar@nxp.com>
Add the ability to run cameras in a logical
snapshot mode instead of always running
in video mode. In particular, the camera
starts when you ask for an image to be dequeued
and stops when it receives an image.
There are two ways to setup to run in this mode:
a) Tell it to do so in the overlay by giving the DCMI object
the property: snapshot-mode
b) At run time: I added a video control: VIDEO_CID_SNAPSHOT_MODE
Which can have the values
0 - normal - continuous video mode
1 - snapshot - snapshot mode enabled.
As mentioned in the snapshot modes, the HAL DMA is stopped after each
image and restarted when the user asks for another image. I added a
timeout default to 1 second, that handles the case where sometimes
the HAL is silently not successful in retrieving an image.
Signed-off-by: Kurt Eckhardt <kurte@rockisland.com>
Several ARM64 devicetrees declare their CPU nodes with
compatible = "arm,armv8", but no binding for that compatible exists.
With no matching binding, gen_defines emits no properties for the
node, so its device_type never reaches the generated devicetree
header.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
cortex_r8_virt.dtsi declares its CPU node with
compatible = "arm,cortex-r8f", but no binding for that compatible
exists; dts/bindings/cpu/ only carries arm,cortex-r8.yaml and
arm,cortex-r82.yaml. With no matching binding, gen_defines emits no
properties for the node, so its device_type never reaches the
generated devicetree header.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Promote zephyr,transfer-timeout-ms to the base i2c-controller.yaml
binding so the property is available on every I2C controller node
regardless of SoC vendor.
Add two macros to <zephyr/drivers/i2c.h>:
- I2C_DT_INST_TRANSFER_TIMEOUT_MS(inst): resolves the raw millisecond
value (DT per-bus override -> CONFIG_I2C_TRANSFER_TIMEOUT_MS)
- I2C_DT_INST_TRANSFER_TIMEOUT(inst): wraps the above using
SYS_TIMEOUT_MS_INIT as a k_timeout_t struct initializer, using
SYS_FOREVER_MS when the resolved value is 0
This composes with the Kconfig added in #104163: the Kconfig remains the
portable app-wide default; the DT property is the per-bus escape hatch.
Signed-off-by: BhuvanChandra DV <bhuvanchandra.dv@rapyuta-robotics.com>
split the props for the mac address into
its own yaml, so that can be reused by the
wifi bindings, as their drivers also use the
ethernet api.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add empty ranges properties to standalone STM32 pinctrl nodes such that
the GPIO port nodes are mapped in the root address space on all series.
Previously, only STM32N6 had this property as it was required for proper
switching between Secure and Non-Secure aliases.
Validation:
- scanned standalone STM32 pinctrl nodes to confirm ranges is now
present in each touched DTSI
Assisted-by: GitHub Copilot:GPT-5.4
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
In `stm32u595.dtsi`, various properties of the pinctrl node were being
redefined for no reason. Drop them entirely except for one: the `reg`
size of the pinctrl node is increased to 0x2800, but now at root DTSI
level instead. This is fine on STM32U5 since there is only one Reference
Manual so it's obvious where the value comes from, regardless of how
many GPIO ports actually exist in the final SoC.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The GPIOF and GPIOI nodes were declared as children of `/soc` when they
should have been childred of the `pin-controller@42020000` node instead.
Fix this error by reparenting the GPIO port nodes.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Implement counter capture callbacks for MCUX QTMR timer channels. Each
Zephyr counter device maps to one QTMR channel, so the API accepts
channel 0 and uses the DT secondary-source property as the capture
input.
Reject capture in modes that already consume the secondary source and
keep alarm and capture ownership exclusive on the channel. Add reset
support so generic counter capture tests can prepare the timer state.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Currently there is no inclusion of "device_type" in cpu.yaml, which
prevents the property from being used in gen_defines.py since it would
not show up in node.props. This is needed to enable the use of
device_type for the new set of DT CPU macros.
Signed-off-by: Omar Naffaa <onaffaa@qti.qualcomm.com>
Wi-Fi driver for ST67W611M1 coprocessor.
It communicates with an SPI interface and depends on Zephyr's own
TCP/IP stack.
Communication with host is a mix of AT commands (scan, connect,...)
and raw L2 layer data frames.
Signed-off-by: Eliott Speyser <eliott.speyser@st.com>
This commit removes a redundant HSE clock frequency definition for wch.
This value is really dependent on the component placed on a board, so
two layers of default are not necessary.
Signed-off-by: Perry Naseck <pnaseck@media.mit.edu>
Add all predefined values for phy-connection-type
from the devicetree specification (Table 4.13).
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
XIP in Zephyr is a software configuration concept (CONFIG_XIP). The MSPI
feature gated by MSPI_XIP only memory-maps the device into the SoC
address space; the mapped region can be used for plain data access as
well as code execution. Rename the feature to MEMMAP to reflect what it
actually does:
- CONFIG_MSPI_XIP -> CONFIG_MSPI_MEMMAP
- CONFIG_FLASH_MSPI_XIP_READ -> CONFIG_FLASH_MSPI_MEMMAP_READ
- struct mspi_xip_cfg -> struct mspi_memmap_cfg
- enum mspi_xip_permit / MSPI_XIP_READ_* -> mspi_memmap_permit /
MSPI_MEMMAP_READ_*
- mspi_xip_config() -> mspi_memmap_config(), driver API entry
xip_config -> memmap_config
- MSPI_XIP_CONFIG_DT{,_INST,_NO_CHECK} -> MSPI_MEMMAP_CONFIG_DT{,...}
- MSPI_XIP_CFG_STRUCT_DECLARE / MSPI_XIP_BASE_ADDR_{DECLARE,INIT} ->
MSPI_MEMMAP_*
- devicetree property xip-config -> memmap-config
Vendor HAL symbols (am_hal_mspi_xip_*) and DesignWare register names,
where XIP is the hardware documentation terminology, are unchanged.
The MSPI API is experimental, so no deprecated aliases are provided;
a migration guide entry is added in a separate commit. Add missing
Doxygen comments on new API symbols. Add missing SPDX header to the
nrf54h20dk code_relocation_nocopy overlay touched by this rename.
Fixes#104657
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Channel preselection is defined in st/h7/stm32h7.dtsi for ADC3 in whole
STM32H7 series. ADC3 in STM32H72x and STM32H73X don't support channel
preselection so it's removed from corresponding adc3 node.
Signed-off-by: Marin Jurjević <marinjurjevic@outlook.com>
Instead of the vendor-specific `stm32_lp_tick_source` nodelabel, update
the STM32 LPTIM systimer driver to use the `zephyr,system-timer` chosen
as singleton instance selection.
Remove support for the old mechanism entirely, triggering instead
a build error during Kconfig parsing (to avoid unnecessary compilation).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The STM32WB55 VREFBUF supports scale change while active. Add the
corresponding property on the node at SoC DTSI level.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a new property to the STM32 VREFBUF binding indicating whether the
hardware supports changing voltage scale while the regulator is active.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a Kconfig option, DMA_MCHP_XEC_DMAC_MAX_CHANNELS, defaulting to the
dmac node's dma-channels devicetree property,
Updated PCR and GIRQ properties of DMA node to use new macros
Also removed the XEC_DMA_DEBUG logic.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
The TDP2004 is a four-channel linear repeater or redriver designed
to support DisplayPort 2.1 up to 20Gbps and AC coupled HDMI2.1 source
up to 12Gbps.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Add device tree source files for the TI MSPM33C321A.
CPU node, ARMv8-M NVIC with 2 priority bits, and
base SRAM/flash memory nodes common to the MSPM33C series
with mspm33c321a device specific memory sizes.
Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
Add an in-process virtual Wi-Fi simulator (wifi_hwsim) for testing the
Zephyr Wi-Fi stack (wpa_supplicant / hostapd -> driver) without
physical hardware, modeled after Linux's mac80211_hwsim.
The driver instantiates N virtual radios from devicetree, each backed
by a net_if with Ethernet L2 and Wi-Fi offload. An in-process
frame-relay "medium" connects radios tuned to the same frequency.
Management frames (802.11) are handed to wpa_supplicant; data frames
(802.3) are delivered by L2 destination MAC, so a unicast frame reaches
only the matching radio while broadcast/multicast frames reach all
peers on the channel.
Because all radios share a single IP stack, a peer's source address is
also a local address. Injected data frames are flagged as loopback so
they are not dropped by the IP input anti-spoof check; deployments must
also disable the "destination is my own address" short-circuit
(CONFIG_NET_IP_ADDR_CHECK) so inter-radio data frames traverse the
medium.
Open, WPA2-PSK and WPA3-SAE associations work end to end. Since both
radios live in one process, the driver relays the association between
the STA and AP contexts as an EVENT_ASSOC carrying the STA's RSN IE (the
way a FullMAC firmware reports it) rather than serializing
(Re)Association frames. For a secured network the STA port is left
unauthorized so wpa_supplicant runs the real 4-way handshake, whose
EAPOL frames cross the medium as ordinary data frames. The AP's beacon
IEs (including the RSN element) are surfaced in scan results so a STA
can match a secured network, and the AP-side station ops are accepted
so the authenticator can authorize the station.
For WPA3-SAE the driver advertises WPA_DRIVER_FLAGS_SAE and relays the
SAE Authentication commit/confirm frames over the medium (built from the
SME auth_data on the STA, parsed back into EVENT_AUTH), so the real SAE
exchange runs before the 4-way handshake.
MAC addresses follow the standard Ethernet MAC config mechanism
(local-mac-address / zephyr,random-mac-address / NVMEM via
net_eth_mac_load()), falling back to a random locally-administered
address.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Assisted-by: Claude:claude-opus-4.8
On the RP2040, interrupt 15 is used for the RX FIFO on core 0, and
interrupt 16 is used for the RX FIFO on core 1. By splitting the mailbox
node into separate ones for each core, the correct interrupt for each core
can be selectively enabled in an overlay.
This benefits AMP use cases with the RP2040 where each core runs its own
distinct application. Without this, only the interrupt for core 0 would be
enabled.
Signed-off-by: Eric Hay <erichay@live.ca>
Set the 'power-domains' property for the I2C node and enable automatic
runtime PM device management with 'zephyr,pm-device-runtime-auto'. This
allows the I2C peripheral to properly integrate with power management
policies, ensuring it is controlled according to the state of the
associated power domain.
Upstream-status: pending
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Introducing a devicetree description for the STM32F103X6 SoC
(low-density value line).
changes summary:
1. stm32f103X6.dtsi becomes the new base for the low-density F103 line.
It includes stm32f1.dtsi directly and carries the peripherals shared by
X6 and X8 (usb, can1, usb_fs_phy).
2. stm32f103X8.dtsi now includes stm32f103X6.dtsi
and gains i2c2, usart3 and timers4, which are not present on X6.
3. i2c2, usart3, timers4 and the smbus2 node (which references i2c2)
are removed from the common stm32f1.dtsi, since they are not present
on every F1 chip.
4. stm32f100Xb.dtsi and stm32f105.dtsi, which include stm32f1.dtsi
directly and do not chain through stm32f103X8.dtsi, gain local copies
of i2c2, usart3, timers4 and smbus2, following the existing pattern
already used there for spi2.
Build-tested (samples/hello_world) against
- stm32vl_disco,
- stm3210c_eval,
- nucleo_f103rb,
- olimexino_stm32,
- stm32_min_dev,
- stm32f103_mini,
- waveshare_open103z,
- e80_900mbl_01
and All have passed!
Assisted-by: Claude:claude-sonnet-5
Signed-off-by: Mohammed Siddique <mohammed.siddique@solitontech.com>
Move `phy-handle` to use the dependency-mode prop
key instead of the hardcoded code.
Because all ethernet drivers only need to use the
phy-handle in the iface init, we can ignore the
phy-handle dependency completly instead of only
ignoring it if the phy-handle pointing to a child
node of the ethernet node.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add a basic flash driver for intel pflash. This flash implements a CFI
interface, and is available as "pflash" within QEMU targets.
Assisted-by: Claude:Haiku 4.5
Signed-off-by: Daniel DeGrasse <daniel.degrasse@analog.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find dts/arm -type f -exec ./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add driver for the ADIS16477 6-axis IMU sensor family.
Supports polling, trigger (DRDY interrupt), RTIO async, and
streaming modes. Includes SPI bus access, burst read, decoder,
temperature and inertial data channels, decimation rate
configuration via devicetree, hardware reset, and diagnostic
status checking.
Signed-off-by: Iustin Stolniceanu <iustin.stolniceanu@analog.com>
Add TTC0 nodes for Versal-Net using a parent xlnx,ttc block with
three child xlnx,ttc-counter timer instances.
Signed-off-by: Satya Sri <satyasri.katru@amd.com>
Add TTC0 nodes for Versal2 using a parent xlnx,ttc block with
three child xlnx,ttc-counter timer instances.
Signed-off-by: Satya Sri <satyasri.katru@amd.com>
Add devicetree bindings for the AMD/Xilinx TTC block and timer
instances. Model the hardware as a parent xlnx,ttc node with child
xlnx,ttc-counter nodes.
Signed-off-by: Satya Sri <satyasri.katru@amd.com>
Adding a binding property to enable speaker output and updating the
driver to support driving the speaker in addition to the headphone
outputs.
Signed-off-by: Brett Peterson <brett.peterson@infineon.com>
Add nodes for the two Cadence SPI controllers in the Versal.
These nodes describe the standard SPI controllers and do not
include the separate QSPI/OSPI controller.
Signed-off-by: Takumi Ando <takumi@spacecubics.com>
Add AON QTMR0 and QTMR1 devicetree nodes for MCXL255.
Each QTMR channel is represented as a separate nxp,imx-tmr child node
and disabled by default.
Model the AON QTMR clock as a fixed-clock provider based on the
configured 2.5 MHz AON QTMR clock.
Override the QTMR interrupt numbers for the CM33 core.
Signed-off-by: Samuel Slesar <samuel.slesar@nxp.com>
Implement a driver for the ADC ADS1220.
Currently only the single shot mode is supported.
Origin: Original
Signed-off-by: Hasler Pauline <phasler@baumer.com>
Adds SoC support for SHAKTI Ganga, a 64-bit
RISCV SoC from SHAKTI processor initiative at
RISE Lab, IIT Madras. Ganga is commonly ran as
soft core on FPGA boards.
This commit adds SoC family Kconfig and
the base devicetree.
Signed-off-by: Vedant Malkar <vedantitsme@gmail.com>
Add bare-minimum board support for UIAPduino Pro Micro CH32V003.
This enables the WCH CH32V003F4U SoC and basic GPIO support only. The board
definition provides an LED on PC0 so the blinky sample can run.
USART is not enabled yet.
Configure minichlink as the default runner with the board-specific probe
identifier.
Product page:
https://www.uiap.jp/en/uiapduino/
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
