Add shared interrupt support for STM32 UART on SoC families where
multiple USART/LPUART peripherals share a single IRQ line (F0, G0,
L0, U0, C0).
Add a compile-time BUILD_ASSERT in the STM32 UART driver that detects
when two or more enabled UART instances share an IRQ and
CONFIG_SHARED_INTERRUPTS is not set.
Add configdefault SHARED_INTERRUPTS and SHARED_IRQ_MAX_NUM_CLIENTS
to the SoC Kconfig for STM32F0x, STM32L0x, STM32U0x, and STM32C0x.
Update DTS comments in the F0 family that previously stated shared
UART IRQs are unsupported.
The SHARED_IRQ_MAX_NUM_CLIENTS combinations in the F0x Kconfig were
generated with:
from itertools import combinations
usarts = ['usart3','usart4','usart5','usart6','usart7','usart8']
for n in range(6, 2, -1):
for combo in combinations(usarts, n):
conds = ' && '.join(
f'$(dt_nodelabel_enabled,{u})'
for u in combo)
print(f'\tdefault {n} if {conds}')
Fixes zephyrproject-rtos#39565
Signed-off-by: Anand Kumar <anandvtu16158@gmail.com>
Check for secondary RV32 support by way of devicetree checks, not enabling
explicitly for each SoC in Kconfig.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Add I2C driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Master mode operation
- 7-bit and 10-bit addressing
- Standard and Fast mode speeds
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add support for configuring the Set Tear ScanLine (STE) command in the
ST7796S LCD display driver. This allows users to specify the exact
scanline where the Tearing Effect (TE) signal becomes active, providing
better control over display synchronization.
Changes:
- Add ST7796S_CMD_STE (0x44) command definition
- Add tear-scanline property to device tree binding
- Add tear_scanline field to driver configuration structure
- Implement STE command configuration in LCD initialization
The tear scanline can now be configured via device tree:
tear-scanline = <240>; // TE signal at scanline 240
Signed-off-by: Ankitkumar Modi <ankit.modi912@gmail.com>
- Added mcux_lcdifv3_set_pixel_format api
- Fix pointer-to-integer cast error by using uintptr_t intermediate cast
instead of direct uint64_t cast
- Fixed the pixel_format setting on waveshare_dsi_lcd shield
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
Add DAC devicetree nodes for MSPM0 G-Series SoCs that include the DAC
peripheral: mspm0g150x, mspm0g350x and mspm0gx51x.
Signed-off-by: Santhosh Charles <santhosh@linumiz.com>
This commit adds the "soc-nv-flash" compatibility to the NXP C40
flash node, allowing mcuboot's automatic layout detection mechanism
(which relies on the erase-block-size and write-block-size
properties which are already there) to work.
It is a partial and required step to fix:
zephyrproject-rtos/zephyr#106597
Signed-off-by: Rob Newberry <rob@zenomoto.com>
Signed-off-by: rob-zeno <rob@zenomoto.com>
Fix a typo in `st,stm32n6-ic-clock-mux.yaml`.
Description was using `div` property instead of `ic-div`.
Signed-off-by: Basile GRUNER <basile.gruner@smile.fr>
The ulp_shm DTS node at 0x3bf0 overlapped with the last
16 bytes of the ulp_ram region (0x0..0x3c00) on both
ESP32-C5 and ESP32-C6.
Move ulp_shm to 0x3c00, right after ulp_ram, and shift
lp_rtc from 0x3c00 to 0x3c10 (shrinking it by 16 bytes
from 0xf8 to 0xe8) to make room. All other regions
(retainedmem, ipc_shm, mbox0) keep their addresses.
Update LP core linker scripts to stop subtracting
shared mem size from the ram segment length, since
ulp_shm is now outside the coprocessor reservation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Corret the RV32 core interrupt numbers for MAX32690 specific peripherals,
to allow proper interrupt usage with those peripherals.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
NXP FlexSPI NOR flash nodes were missing the soc-nv-flash child
node expected by Zephyr's flash map API.
Without this child node, DT_MTD_FROM_FIXED_PARTITION resolved to
the FlexSPI memory controller instead of the flash device. Since
the controller has api = NULL, MCUboot could hit a NULL pointer
dereference during boot on Zephyr 4.4.
Fix this by updating the DTS structure to match the soc-nv-flash
convention used by the flash map infrastructure.
Changes:
- add a soc-nv-flash child under each nxp,imx-flexspi-nor node
- move erase-block-size, write-block-size, and partitions into it
- add ranges to flash controller nodes for address translation
- update zephyr,flash to point to the soc-nv-flash child
- add zephyr,flash-controller chosen for the flash driver node
- remove soc-nv-flash.yaml from nxp,imx-flexspi-nor.yaml
- use zephyr,flash-controller in flash CMake XIP decisions
- update FlexSPI XIP Kconfig logic to walk to the grandparent
This keeps the controller and flash device roles separate and
restores correct flash map resolution for MCUboot and XIP logic.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
This property can be used by various modems. Used it successfully with
nRF91-SLM when waiting for "Ready" signal after automatic power-on.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This PR removes duplicate properties in the same closure. The last
instance is the one the is keept.
This PR only cleans up current instances a separate PR will be done to
update the dts-linter to enforce this in the compliance check.
Signed-off-by: Kyle Bonnici <kylebonnici@hotmail.com>
SoC, DTS, and board files should live in directories named after the
vendor prefix so rename all occurrences of synaptics/ to syna/.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Currently flexCAN initialization failed when CONFIG_CAN_FD_MODE=y is
enabled on imx9 serial platforms. So remove CAN FD compatible from
flexcan device node to disable CAN FD on these platform temporarily,
and will add it back when the formal fix is available.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Removed timers3 from stm32wba.dtsi as the WBA2x series
does not have this timer. Moved it to stm32wba52.dtsi instead.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
Add FLASH_LAYOUT_STM32WBA2X define to select
the right area for the engineering bytes for the WBA2X series.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
Add CAN-FD devicetree nodes for MSPM0 G-Series SoCs that include
the peripheral: mspm0g310x, mspm0g350x and mspm0gx51x.
Signed-off-by: Santhosh Charles <santhosh@linumiz.com>
Signed-off-by: Tomasz Bursztyka <tobu@bang-olufsen.dk>
Add devicetree bindings for the TI MSPM0 G-Series MCAN module.
Signed-off-by: Santhosh Charles <santhosh@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
The BLE driver and Radio Timer driver register ISRs for interrupts that are
not declared in the Devicetree. Since CONFIG_NUM_IRQS is now determined
automatically based on IRQn appearing in active Devicetree nodes, this now
causes build failures.
Add missing interrupts in the SoC DTSI to fix build failures.
Further cleanup of the aforementionned drivers to actually obtain IRQn from
DT properties should be done at a later time.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
We need to add properties such as interrupts in DT for these devices.
Add them to the binding by including `base.yaml`.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
In order to use HIBERNATE sleep mode, retention of RAM block used
for hibernating the VPR core need to be enabled. Contrary to all other
blocks, retention for this block is usually by default disabled.
Add property to vpr coprocessor node which indicates if hibernation
is going to be used. It need to be used on nRF54L to achieve low
idle current. On nRF54H20 it is not needed as DEEPSLEEP mode gives
good idle current (~5 uA).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Adds a missing include of base.yaml which meant some properties
were not available when using the CMake dt functions
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Update the MCUX WWDT driver to partially use the Zephyr clock control API
instead of direct HAL clock APIs for clock on and get rate.
Keep using HAL clock APIs for set clock divider because the set rate API
accepts clock frequency and it may cause two external calls to get WWDT
frequency.
Support multiple instances.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
Add clock controller references to WWDT device tree nodes across
multiple NXP SoC families. This enables proper clock management
for WWDT peripherals now that the MCUX SYSCON driver supports
WWDT clock control.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
The Arducam mega is a low power, rolling shutter camera, supports
connecting one or more cameras to any microcontroller. It provides
high-quality image capture and processing capabilities, making it
highly suitable for various application fields, including machine
vision, image recognition, and robotics, among others. In current
implementation connecting multiple instances of the same camera
system is problematic.
Co-authored-by: Lee Jackson <lee.jackson@arducam.com>
Signed-off-by: Krystian Balicki <kristos_b@wp.pl>
