The UCPD1 clock enable bit is in
RCC_APB1HENR, which should be represented as "STM32_CLOCK(APB1_2, 23)",
but the SoC DTSI used "APB1" (no _2) instead. As a result, the UCPD
clock could not really be enabled.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Adds the high-performance DMA controller (HPDMA1) node to the STM32N6
base devicetree file. Base address, clocks, and contiguous IRQ lines
(68-83) are derived directly from the vendor CMSIS device headers.
Signed-off-by: Sher Amir Singh Dullat <sheramir51@gmail.com>
Add missing nodes for the OTG_HS USB controller and associated USBPHYC
to the STM32H7R/S SoC DTSI.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Perform a few changes to the st,stm32-usbphyc binding in order to allow
its use on STM32H7R/S series SoCs:
- make the `clock-names` property mandatory
- cell names will be used in the PHY pseudo-driver for STM32H7R/S
- drop requirement to provide `reg`
- USBPHYC does not have a MMIO interface on STM32H7R/S
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a Zephyr mbox driver for the ARM Message Handling Unit v2.
Supports doorbell-only signalling across all hardware channel
windows from a single device instance.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Remove the dedicated xlnx_xuartps driver and consolidate support
into the Cadence UART driver (uart_cdns), as both drivers target
the same underlying Cadence UART IP used by Xilinx platforms.
Update device tree bindings and DTS files to use the Cadence
compatible string on supported platforms, remove obsolete driver
sources, and adjust build system configuration accordingly.
Also update test overlays to reflect the driver consolidation.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
group2 muxed UART0_RTS_GPIO31 a second time instead of
UART0_CTS_GPIO30, leaving the CTS pin unmuxed, so CTS/RTS flow
control did not work for boards using this group. Verified on a
Pi Zero 2 W where GPIO 30-33 at ALT3 route uart0 to the onboard
CYW43436 BT HCI with flow control enabled.
Signed-off-by: Jonathan E. Peace <jep@alphabetiq.com>
Add SIP-level dtsi files for 32 MB flash ESP32-P4 variants:
esp32p4_n32r32.dtsi for the ESP32-P4NRW32 SIP (32 MB in-package
PSRAM and 32 MB external NOR flash) and esp32p4_lpcore_n32.dtsi
for the LP core on 32 MB flash parts.
Also add a default 32 MB partition layout with the 0x2000 boot
offset, mirroring the existing 0x1000 32 MB layout.
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
Map 1:1 using empty 'ranges;' property. Specific range property should
only be use when devices are not on the same bus interface. This also
prevents from redefining Secure/Non-Secure addresses.
Signed-off-by: Raphaël Gallais-Pou <raphael.gallais-pou@foss.st.com>
The `ranges` property should be a `compound` because it can either be
EMPTY (a.k.a. 'boolean') or NUMS (a.k.a. 'array').
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Signed-off-by: Raphaël Gallais-Pou <raphael.gallais-pou@foss.st.com>
Add #address-cells, #size-cells, and ranges properties to flash nodes.
This enables address translation from partition offsets to physical
flash addresses, required for zephyr,mapped-partition compatible.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
The swap-xy, invert-x, and invert-y properties in the
zephyr,lvgl-pointer-input devicetree binding are deprecated. Users should
instead add these properties to the underlying touch input controller
device node.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Apply the default pinctrl state during PM_DEVICE_ACTION_RESUME to restore
normal SHI operation.
Apply the sleep pinctrl state during PM_DEVICE_ACTION_SUSPEND to disable
the SHI interface pins and prevent leakage.
This lets board/shim code control the pin state purely via
pm_device_runtime_get()/put().
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add optional pinctrl support so board files can mux GPT_CLK,
GPT_CAPTUREn, and GPT_COMPAREn pins via the standard pinctrl-0
property. The default state is applied early in driver init, before
GPT_Init. A missing pinctrl state (-ENOENT) is treated as optional
and silently ignored.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Allow selecting from all five GPT clock sources (off, periph,
high-freq, ext, low-freq, osc) via a new clock-source DT property.
The ext source fixes the prescaler at 1 since the frequency
is unknown to software.
gptfreq is no longer required when clock-source = "ext", in which
case counter_get_freq() returns 0 and callers work in raw ticks.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Add a driver for the Hamamatsu S9706 digital RGB sensor using plain
GPIOs. All parameters (e.g. integration time and sensor range) are
runtime-configurable via sensor attributes.
Signed-off-by: Anton Puppe <anton-noel-flynn.puppe@zeiss.com>
The bring-up path pulses the power key unconditionally. On modems that
toggle power with the key, that turns off a modem still running after an
MCU-only reset, and the driver then times out against a dead bus until the
modem completes a full power cycle.
Add an optional mdm-status-gpios input reporting modem power state. When it
is present and asserted at start-up, skip the power-on pulse and bring up
the bus directly; the init script confirms the modem responds, and if it
does not, the driver powers the modem on. Boards without the GPIO behave as
before.
Signed-off-by: Paulo Santos <pauloxrms@gmail.com>
swapped-x-y exchanges only the reported event codes. That is correct
when the touchscreen's coordinate space and the display share an aspect
ratio, and wrong as soon as they do not: on a rotated non-square panel
the swapped axes still carry each other's range, so X arrives bounded by
the screen height while Y overruns the display's.
A concrete case: a 480x272 panel whose controller reports in its own
480x272 space, mounted rotated a quarter turn. swapped-x-y alone
confines the reported X to 0..272 and lets Y reach 480 on a panel 272
tall. There is no combination of the existing properties that expresses
the rotation, because none of them rescale.
Add optional output-width / output-height describing the space
coordinates should land in, and scale into it after inverting and
swapping. Each value keeps its own source range -- the value held as X
always spans screen-width -- while its target dimension follows the code
it is reported under, which swapped-x-y has already chosen. So with the
axes swapped, the X value is scaled by output-height/screen-width and
lands on INPUT_ABS_Y.
The dimensions can also come from a display controller directly: an
optional display phandle sources output-width / output-height from the
referenced node's width / height, so the panel resolution is not
duplicated on the touchscreen node.
Both output dimensions are optional and resolve to 0 when absent, which
disables scaling: every existing driver and board keeps reporting
exactly what the controller produced.
Signed-off-by: Arkadiusz Grzelka <devitwise@gmail.com>
This is almost a copy of the STM32L152xE support.
The STM32L152xE is already supported and is nearly identical.
The STM32L151xE differs only by lacking the LCD interface.
Signed-off-by: Florian Moesch <florian.moesch@draeger.com>
Describe the LTDC display controller available on
STM32 H5E4/H5E5 and H5F4/H5F5.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
(cherry picked from commit 82d6afb375)
Signed-off-by: Arkadiusz Grzelka <devitwise@gmail.com>
RTL87x2G exposes 204 KB of TCM to Zephyr (0x100c00–0x133c00).
The previous 100 KB / 104 KB split left ITCM heavily over-allocated:
actual usage is ~2.2 KB of relocation tables, while the remaining
~101 KB was idle. Meanwhile SRAM is a bottleneck; for example, the
CMSIS-DSP matrix.binary_q15 test requires ≥144 KB and fails with OOM.
Resize the split to give Zephyr more usable SRAM:
tcm0 (zephyr,sram): 0x100c00 + 176 KB → 0x12cc00
tcm1 (zephyr,itcm): 0x12cc00 + 28 KB → 0x133c00
Update the board yaml ram field for all four rtl87x2g variants
(gkh, gku, grh, gru) from the stale placeholder 100 to 176.
Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Route the CPU0 IRTC wake-timer through SLEEPCON0: mark the node
wakeup-source with a wakeup-ctrls line of <&sleepcon0 27>, and enable
sleepcon0 itself. SLEEPCON0 is an always-present on-chip controller, so
it is enabled by default; CONFIG_WUC still gates whether its driver is
built. This lets the IRTC wake CPU0 from deep-sleep retention.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Include the wuc-device.yaml mixin so an nxp,irtc-wake-timer node can
declare a WUC wakeup line via the wakeup-ctrls property. The property is
optional, so SoCs whose IRTC does not route through a WUC leave it unset
and are unaffected.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add a disabled nxp,rtc node for the MCXAXX6.
OSC32k is not available on these devices; clock-source is set to
"LPO" to select the 16.384 kHz FRO16K (VBAT domain) via CR[LPOS]=1.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
- Only timg0 timer seems to be consistent across all L-series. And event
that does not seem guaranteed. So only adding to mspm0l111x.
- Currently tested as counters using samples/drivers/counter/alarm on
beagleconnect_zepto (mspm0l1117).
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Add initial driver support for the Quectel BC66 and BC660K NB-IoT
cellular modems. The driver implements the standard Zephyr
cellular modem APIs and features network offloading via BSD sockets,
specifically supporting TCP and UDP clients. Device Power Management
(PM) support is also included.
Assisted-by: Claude:claude-sonnet-4.6
Assisted-by: Gemini:gemini-3.1-pro
Signed-off-by: Giovanni Piccari <giopiccari@outlook.com>
Some ST7789V panel integrations rely on the controller reset defaults
or on fixed power sequencing and must not receive the default power
and gamma configuration commands during initialization.
Instead of adding a bypass flag, make the power/gamma/tuning
devicetree properties optional (vcom, gctrl, lcm, gamma, porch-param,
cmd2en-param, pwctrl1-param, pvgam-param, nvgam-param, ram-param,
rgb-param) and only send a configuration command when its property is
present, following the existing vrhs/vdvs handling.
Existing boards set all of these properties, so their initialization
sequence is unchanged.
Signed-off-by: Yeray Lois Sanchez <yerayloissanchez@gmail.com>
FlexSPI is NXP's proprietary memory-mapped flash/PSRAM controller
with its own LUT engine, AHB buffers, and clock tree — it is not a
standard SPI bus. Including spi-device.yaml pulled in `on-bus: spi`
semantics and 11 SPI-specific properties (duplex, spi-cpol, spi-cpha,
etc.) that are meaningless for FlexSPI devices.
Replace the spi-device.yaml include with base.yaml and power.yaml,
and directly declare the only two properties FlexSPI actually uses
from the SPI binding: `reg` and `spi-max-frequency`.
This removes the incorrect SPI bus semantics from the FlexSPI binding
chain, which caused all FlexSPI descendants (including `soc-nv-flash`
grandchild nodes) to appear as SPI bus devices, misleading downstream
DTS authors into placing SPI-specific properties on nodes whose
bindings do not declare them.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
The driver reports raw controller coordinates straight to INPUT_ABS_X and
INPUT_ABS_Y, so none of the touchscreen-common orientation properties reach
it: a board wiring this part to a rotated or mirrored panel has no way to
describe that in devicetree. Every other touch driver in the tree goes
through input_touchscreen_report_pos().
Route both report paths through the helper and include
touchscreen-common.yaml in the binding. `select INPUT_TOUCH` comes with it:
input_touch.c is gated on that symbol, so without it the helper is never
compiled and the driver fails to link.
Behaviour is unchanged for existing users -- with none of the orientation
properties set the helper passes the coordinates through untouched.
Signed-off-by: Arkadiusz Grzelka <devitwise@gmail.com>
Commit 7afcac3f51 ("drivers: interrupt_controller: Use new CPU macro
to iterate through CPUs") made CPU enumeration depend on the
device_type property being declared by a matched binding, breaking the
build for CPU node compatibles that have no binding. Commit
0a26f478af3c ("dts: bindings: cpu: add arm,cortex-r8f binding") and
commit 17cf0dabd3 ("dts: bindings: cpu: add arm,armv8 binding") added
two of the three missing bindings, which also unbroke the
rcar_h3ulcb/r8a77951/a57 build through the "arm,armv8" fallback in its
CPU nodes' compatible list.
Add the Cortex-A57 binding as well so those CPUs match their specific
compatible rather than the generic fallback.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The MRAMC driver requires write-block-size to be a multiple of the
16-byte MRAM word size. Set write-block-size to 16 to match the
hardware constraint and the cpuapp_mram definition.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
