move adi,adin1110.yaml adi,adin2111.yaml
from the phy subdir back into the ethernet dir.
They are ethernet controller bindings, not phy bindings.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Re-use the workqueue instead of having dedicated thread for handling
interrupts. This reduces memory usage and complexity.
Furthermore adds an auto mode for 100BASE-T1 negotiation.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Add declarations for High-Speed External (HSE) and High-Speed Internal
(HSI) clocks.
These clocks, based on oscillators, can be used to generate the system
clocks.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Foxville LM (0x125B) i226 variant and Intel Alder Lake platform was
used for developing and stabilizing the i226 Ethernet device driver.
However, users can reuse the provided device tree models as a reference
when enabling the support for other i226 variants and platforms.
This device-tree model include essential configurations for the i226
Ethernet controller, such as PCIe settings, interrupt mappings, Phy
MDIO, and DMA descriptor configurations.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
The Intel i226 Ethernet Controller is a PCIe Gen 2 one-lane modular
endpoint device that integrates a GbE Media Access Control (MAC) and
Physical Layer (PHY) port. This driver provides support for MAC and
DMA-specific initialization and runtime TX/RX operations.
Key features:
- MSI-X interrupts for TX/RX DMA channels.
- Multiple TX/RX DMA channel support with exclusive bottom-half.
- Implements a circular descriptor ring architechture with
producer-consumer semantics for high performance pkt processing.
- Full duplex support for 10/100/1000 Mbps.
- Half duplex support for 10/100 Mbps.
- Auto-negotiation for 10/100/1000 Mbps.
- MTU customization for flexible packet sizes.
- MAC address filtering based on:
- Random MAC generation.
- Local-mac-address mentioned in device tree.
- EEPROM pre-programmed mac address.
- Setting mac address via net shell.
- Support for multiple Ethernet interface instances.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Signed-off-by: Ling Pei Lee <pei.lee.ling@intel.com>
Intel i226 MAC supports MDIO C22 and MDIO C45. Standard PHY registers
are accessible through MDIO C22, whereas PMAPMD and PCS are accssible
through MDIO C45.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
The Ethernet device model consists of multiple subsystem components, such
as MDIO, PHY, MAC and PTP_CLOCK. These components are mapped into a single
PCIe BAR location with same base address.
This platform driver retrieves the MMIO mapping details and provides a
framework to share it with all the child subsystem components. This
approach avoid the duplicate remapping, ensures efficient re-use of
MMIO mappings across related devices.
Example device tree structure for first ethernet instance:
parent0: parent0 {
compatible = "intel,eth-plat";
interrupt-parent = <&intc>;
vendor-id = <0x8086>;
device-id = <0xXXXX>;
igc0: igc0 {
compatible = "intel,igc-mac";
/*
* MAC specific properties.
*/
status = "okay";
};
mdio0: mdio0 {
compatible = "intel,igc-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy";
/*
* PHY specific properties.
*/
reg = <0x0>;
};
};
};
This framework is modular and re-usable for other PCIe based Ethernet
devices. It can also be extended to support additional platform specific
information shared across child nodes.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
According to the datasheet the flash erase timing is
typically 2ms, and max 10ms.
H503: DS14053 Rev 4: section 5.3.10, table 45, t_erase_max=10ms
H562/H563: DS14258 Rev 6: section 5.3.11, table 51, t_erase_max=10ms
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
M4F can use uarts from main domain of AM62. However, interrupts are not
supported.
The common main peripheral dts is kept in dts/venodor/ti to allow
sharing between arm targets (m4, r5) and arm64 targets (a53).
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Add a flash driver that is used to perform flash operations on a flash
chip that is connected to an Andes QSPI controller and is used for XIP
mode.
The driver is as small as possible, because necessary code has to be
placed in RAM. It is not possible to fetch code from flash while
performing erase/write operations.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Add stm32l1_disco and nucleo_l152re overlays for testing
sleep/stop/standby modes:
- samples/boards/st/power_mgmt/blinky;
- samples/boards/st/power_mgmt/wkup_pins;
I've measured consumption for each low-power mode:
- low-power sleep ~1.72mA;
- stop mode ~324uA;
- standby mode ~2.2 uA;
It's possible to use RTC as idle timer to exit from stop mode.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
This commit adds a new driver for the MaxBotix MB7040 ultrasonic
rangefinder. The driver uses I2C communication to read range data
from the sensor and exposes it via the Zephyr sensor API.
Tested on an esp32-s3 board using I2C bus. Verified readings at multiple
distances to confirm accuracy.
Signed-off-by: Sabrina Simkhovich <sabrinasimkhovich@gmail.com>
Adds additional MPU memory permissions to userspace applications by
default. This change addresses an MPU fault encountered when running
tests/kernel/common and tests/drivers/adc/adc_api.
This approach opens additional memory locations up to user space access.
This assumes that end users of applications will tune the MPU regions for
the needs of that application.
Signed-off-by: John Batch <john.batch@infineon.com>
HCI RESET done in common_init() function in
the zephyr\subsys\bluetooth\host\hci_core.c file erase settings done
before in the zephyr\drivers\bluetooth\hci\ipm_stm32wb.c
in the bt_ipm_setup() function.
HCI RESET can be avoided by set a default "no-reset"
in the zephyr\dts\bindings\bluetooth\st,stm32wb-ble-rf.yaml
Signed-off-by: Eric Mechin <eric.mechin@st.com>
Interrupt vectors for lpuart1 and lpuart2 are swapped according to the
reference manual RM0503 table 54.
Fixes the usage of the interrupt-driven uart API.
Signed-off-by: Axel Utech <utech@sofiha.de>
This reverts commit 53375e95ba.
Some boards are failing with:
OverflowError: can't convert negative int to unsigned
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Network Coprocessor on SiWx91x owns a large part of the flash. Zephyr
is not expected to access to theses areas.
However, it is still technically possible to access these. In addition, we
prefer the DTS contains a comprehensive and transparent description of the
hardware. So update the DTS with the real partitioning of the SoC.
Reference documentation is available here[1].
[1]: https://www.silabs.com/documents/public/application-notes/
an1416-siwx917-soc-memory-map.pdf
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
mspm0lx series comes with various SoC's which varies in RAM,
Flash size and also with peripherals. Add support for all
the currently available SoC's with basic template.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
TI MSPM0 timer module has capture block used to capture timings of input
signal. Add a support for TI MSPM0 PWM capture.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Allow for users to define the sampling period via the sampleper
register on a per instance basis through device-tree properties.
The previous value was hard coded. The same value is now the default
value.
Signed-off-by: Mark Geiger <MarkGeiger@posteo.de>
We want to simplify the maintenance burden and confusion of having
more than one driver for the same kernel timer peripheral used on
all Microchip MEC parts. The XEC version of the driver was converted
register definitions in the driver. Register access is performed using
Zephyr sys_read/write architecture specific inline routines. Driver DT
YAML was updated to use phandle for the 32-bit basic timer used for
ARCH_HAS_CUSTOM_BUSY_WAIT support, basic timer max value property,
and GIRQ interrtup aggregator hardware information.
SoC part Kconfigs, chip level/board level DTSI updated to use the
unified driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The leds-group-multicolor binding allows to combines several
monochromatic LEDs into one multi-color LED.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
This patch moves the label and color-mapping LED property definitions
from led-controller.yaml into led-node.yaml.
This allows to use these properties from a LED node which is not a
child node of a LED controller. This is preparatory work for adding
the leds-group-multicolor binding.
In addition this patch also removes the redundant "label" property
definitions in gpio-leds.yaml and pwm-leds.yaml. It is now included
from led-node.yaml.
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
PIO interrupts are useful for some of the virtual
peripherals, so describe them in the DT.
This has no direct implications to existing drivers.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Adding initial support for NXP FRDM K32L2B3 board.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
dts: arm: nxp: Fix SRAM node name
Fix address part of the SRAM node name.
Change the SRAM start address definition to lower
case hexadecimal to be consistent.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
Restructured counter and timer.
CTimer/Timer is now parent to pwm and counter.
Created PWM driver and tied to pwm and pwm-led
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
