Implement the functions of I2C host and target.
I2CM: supports nine hosts and each one able located at I2C interface
0~12.
supports two 32 bytes dedicated FIFO mode for read and write.
I2CS: supports three targets and each one able located at I2C
interface 0~8.
supports 16 bytes dedicated FIFO mode that only supports write or
read mode and the maximum buffer size is 256 bytes.
support non-FIFO write to shared FIFO read mode. The maximum
shared FIFO size for read is 256 bytes.
The APIs test include: i2c_write(), i2c_read(), i2c_burst_read(),
i2c_burst_write(), i2c_write_read()
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Move all the vendor-specific dtsi files that were in dts/common to a
new folder under dts/ designated for vendor-specific files,
since they are not common at all, except for one vendor.
Change MAINTAINERS.yml to reflect the moving of the files.
Update migration guide for this change.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit adds a RAM lock node for both NPCX9 and NPCX4. Then, the
user can use this node to configure the RAM lock settings.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Add driver support for xlnx SD/EMMC host controller. The driver
currently support SD host controller version 3.0 and EMMC host
controller version 5.1. This driver functions with the SDHC subsystem to
perform operations on device.
Driver support both interrupt and polled mode data transfer. Uses ADMA2
to perform data transfer.
Signed-off-by: Paul Alvin <alvin.paulp@amd.com>
MAX32657 is Cortex-M33 based Analog Devices MCU.
It supports ARM TrustZone security model.
There will be two boards of this MCU Secure and Non-Secure
This commit defines Secure version of peripherals.
Basic feature of MAX32657 device:
- Core is Cortex-M33
- 50MHz IPO clock
- There are 54 interrupt vectors
- 1MB flash & 256 SRAM
- MAX32657 has:
- 1 x UART
- 1 x I2C/I3C
- 1 x SPI
- 6 x TIMER
- 1 x RTC
- 1 x WDT
- 1 x TRNG
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
Have ov7670 and video smartdma use video interfaces binding. With
this, we can fix the chicken-egg issue in init priority and don't need
the workaround anymore.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
The CH32V003 CPU is a QingKe V2A while others in the CH32V00x series
use the QingKe V2C. Prepare for adding support for the CH32V006 moving
to the more specifc qingke-v2a, moving some cases of SOC_CH32V003
actually meaning SOC_FAMILY_QINGKE_V2A.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Add PM action for the NXP LCDIC driver so that we can
recover from a lower power mode where we lose the register
settings and we need to reconfigure the block.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
I3C is now a bus supported, by relying on RTIO IODEV which is supported
for all buses (I2C, I3C and SPI). Tested backwards compatibility: I2C
and I3C.
No IBI support yet.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Add clock control support for RZ/A2M
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
Adds a dtsi file for the STM32F401XD family of devices. These devices
are closely related to the STM32F401XE family of devices but with a
reduced flash memory from 512kB to 384kB.
Signed-off-by: Ricardo Rivera-Matos <ricardo.rivera-matos@cirrus.com>
Add Bouffalo Lab serial driver. The driver uses pinctrl to configure
pins and have power management capabilities.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add it515xx analog to digital converter driver which supports 8 channels
ch0 ~ ch7 and 12-bit resolution.
Signed-off-by: Yunshao Chiang <Yunshao.Chiang@ite.com.tw>
When GPIO17 or 16 is used as an external REF_CLK signal, the output is
enabled in eth_esp32.c This was added in PR number #65759 and then refined
in PR #74442. However this does not work for PHYs which need the REF_CLK
for MDIO communication, such as LAN8720A. In such cases phy_mii driver
tries to get the ID of such a PHY before REF_CLK is present. Therefore
in this PR I propose to move REF_CLK initialization from eth_esp32.c to
mdio_esp32.c which gets initialized before PHY and ETH.
Signed-off-by: Łukasz Iwaszkiewicz <lukasz.iwaszkiewicz@gmail.com>
Switches back to equal sized partitions, this fixes an issue
whereby the number of overhead sectors for a swap mode was
incorrectly listed as 2 when it should have been 1, and also
allows using any swap mode. This means that when using swap
using mode, 1 sector in the secondary partition will be unusable,
and when using swap using offset, 1 sector in the primary
partition will be unusable
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
