The SIUL2 external interrupt driver is a native implementation usable
across all NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow
clean reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The SIUL2 GPIO driver is a native implementation usable across all
NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow clean
reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The SIUL2 pin control driver is a native implementation usable across
all NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow clean
reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add support for the Renesas RA Capture Engine Unit (CEU),
including driver source files, Kconfig options, and DTS bindings.
- Add initial implementation of the RA CEU driver
- Add dedicated Kconfig and CMake integration
- Provide Devicetree bindings for the RA CEU
- Update module Kconfig to include the new driver
This enables image capture functionality using the CEU peripheral
on Renesas RA series MCUs.
Signed-off-by: Duy Vo <duy.vo.xc@bp.renesas.com>
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
Originally the driver is selected if `HAS_MCUX_SRC_V2` is
selected in SOC level kConfig.
Change to use dts to mark the driver is avaiable for some SOC.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
RT1160 and RT1170 have different sizes for OCRAM1 and OCRAM2 this PR moves
the static ocram1 and ocram2 labels to the soc specific dtsi and defines
their sizes according to the RM. For RT1160, it combines the OCRAM1,
OCRAM2, and OCRAM M7 (FlexRAM ECC) into 1 node for a better user
experience. 256KB total as opposed to 64KB.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Provide the soc configuration for fdcan1 and fdcan2 controllers.
This includes registers address, clocks and interrupt lines
details.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
Some x86_64 platforms have only one CPU node defined in their
respective devicetree files, while setting `CONFIG_MP_MAX_NUM_CPUS`
to two.
This commit adds missing CPU nodes in said devicetree files.
Signed-off-by: Adrian Ściepura <asciepura@internships.antmicro.com>
Add the Texas Instruments INA228 Power/Energy/Charge
monitor. This chip is similar to the INA237, but has
a more precise ADC and added energy/charge channels.
Signed-off-by: Wilkins White <ww@novadynamics.com>
This commit renames the ina23x folder and common files to ina2xx.
The more generic name will support, e.g., the INA237 and INA228
series chips.
Signed-off-by: Wilkins White <ww@novadynamics.com>
The uart driver for nRF54h20 doesn't call pm_device_runtime_enable().
During an uart driver init `pm_device_driver_init()` return early,
because the `pm_device_is_powered()` returns `false`. Power domains,
where uarts are instantiated, are disabled: `pm->domain->pm_base->state`
is not equal to `PM_DEVICE_STATE_ACTIVE`.
At the end of the day, an uart instance is left disabled.
This is a workaround to make the uart usable when CONFIG_PM,
CONFIG_PM_DEVICE and CONFIG_PM_DEVICE_RUNTIME are enabled.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
This follows change of ethos-u core driver (hal_ethos_u) which
removes cache flush/invalidate mask function ethosu_set_basep_cache_mask.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Remove the hash node from STM32755x SoC DTSI. The node was broken
(wrong node name and compatible property) and seems unused and moreover
most STM32H7xx have an HASH peripheral so a proper fix would rather
be to add the node to all relevant SoC. This will be done later, if
the need arises and after proper validation.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Create separate memory regions for each OFS register. With a single
region the linker will gap fill the load segment with zeros between
each option setting section that gets placed in the region when
generating the .elf file.
Signed-off-by: Jeremy Dick <jdick@pivotint.com>
Introduce nordic NRFS SWEXT power domain bindings and add it to
relevant SoC devicetree files.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add the option to specify an alternate ADC gain value to use if the
initial measurement saturates the range. This enables higher data
resolutions when the values are small compared to the maximum signal
values, while still supporting the maximum.
As a concrete example, measuring charge currents from a small solar
panel (0 - 50mA), while also supporting high USB charge currents
(up to 1A).
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add a driver for the VIRTIO Ethernet device.
This is a minimal driver which sets a MAC address and transmits packets,
but does not support any extra features like the control channel or
checksum offloading.
Confirmed to work with the networking subsystem samples. For example, the
zperf sample shows a result of 85 Mbps download and 14 Mbps upload.
Signed-off-by: Jakub Klimczak <jklimczak@internships.antmicro.com>
Enables bbram driver for motorola, mc146818 under its MFD
to access the RAM of the RTC.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Enabled Motorola, mc146818 MFD, which implements RTC
read/write operations and prevents data corruption
by synchronizing these operations.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Bit 8 of AHB3 is reserved, there is no clock-enable bit for the flash
controller according to the Reference Manual.
Signed-off-by: Arthur Gay <arthur.gay@marshmallow.kids>
The MCU_M4FSS has a total of 256KB of SRAM divided into two banks: 192KB
of I-RAM, and 64KB of D-RAM. The I-RAM memory is intended mainly for M4F’s
instruction code, and D-RAM for M4F’s data. The M4F allows
concurrent fetch for instruction code and data via dedicated buses (I-Code
and D-Code, respectively).
The MCU_M4FSS supports unified memory for both banks (I-RAM and D-RAM),
which means instruction code and data can be placed in any bank. Since CM4
converts unaligned accesses into word-aligned accesses internally, cross
RAM access also work fine in unified memory mode.
By having a single parent node for SRAM, we allow both operating modes,
i.e. separate I-RAM and D-RAM and unified SRAM easily.
Also fixed the incorrect D-RAM address.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Add gpio binding file for Microchip Port g1 IPs and
add gpio node in dtsi files.
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
Adds common and SoC-specific .dtsi files for the Microchip
PIC32CM JH family. These files define core peripherals,
address maps, and interrupt controller structure shared
across the PIC32CM JH variants.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
