HX711 pulls DOUT low when data is ready. This commit enabled pin config
to switch from SPI to GPIO and set up GPIIO interrupts for the falling
edge.
The implementation is similar to the `infineon,airoc-wifi` driver, by
using pinctrl.
Signed-off-by: Terry Geng <terry@terriex.com>
HX711 is a specialized 24-bit ADC for load cell and strain gauge sensors.
It uses a two-wire (PD_SCK and DOUT) serial protocol that
- first 24 clock cycles reads out the sample
- last 1 to 3 clock cycles set the PGA gain for the next sample
The requirement of control the exact number of clock cycles makes the
SCK for SPI unsuitable for clocking HX711. Instead, in this commit, the
clock is implemented as a series of 0xAA on the MOSI.
Signed-off-by: Terry Geng <terry@terriex.com>
Fix a few typos and formatting issues in the DTS example of this binding to
be more in line with the project's DTS coding style.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Extend the STM32 VREFBUF regulator driver to support STM32WB devices.
Update the st,stm32-vrefbuf devicetree binding and add the VREFBUF
node to the STM32WB SoC dtsi so that applications can enable the
internal reference buffer on STM32WB.
Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
Change stm32n6xx SoCs DTSI files to ease how a board can use the
secure or non-secure IOMEM and internal SRAMs address ranges depending
on whether the Zephyr application runs in secure or non-secure
world. This relies on use of the ranges DT property.
By default, the existing stm32n6xx SoC DTSI files define the secure
address mapping as prior this change, hence no functional changes.
Boards/platforms embedding a stm32n657X0 compliant SoC and expecting
to run in non-secure world can apply use the standard SoC DTSI file
and apply last stm32n657X0_ns.dtsi overlay file to select the non-secure
mapping address ranges.
For this purpose, use ranges DT properties and a node level for
peripherals and SRAMs:
- Insert axisram12@24000000 node level for the AXI SRAM1 and SRAM2 nodes
with a ranges property to define the address range of these
internal RAMS.
- Add a ranges property in ramcfg@* nodes to define the address ranges
for the AXI SRAMs they each define.
- Insert peripherals@40000000 node level with a ranges property for the
peripherals in soc node and its subnode to define the address ranges
applied.
Update stm32n6x ram_check.ld linker script to consider address ranges
instead of the reg property raw value.
Update the HAL reference that bring pinctrl DTSI files that must be
consistent with the SoC DTSI files regarding pinctrl node path change.
Sync on a MCUboot repo change to consider ranges in stm32n6 memory DT
node properties.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Implement a MAX32 mbox driver with the semaphore peripheral.
Tweak the mbox test to allow testing with only one TX/RX channel pair
available.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Add devicetree binding for the Bouffalo Lab BL70x USB 1.1 Full-Speed
device controller and define the USB peripheral node in bl70x.dtsi.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Set cpu-buffer-stall property on the BL70x USB peripheral node to
ensure proper buffer alignment for DMA transfers.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Extended ADT7420 driver to support:
- extend dtbindings for comprehensive configuration control
- Support 13-bit and 16-bit ADC resolution
- extend Sensor API support
- extend interrupt support to include CT pin
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Nordic's nPM10 Series PMIC Sensor Devicetree bindings and minimal driver
supporting only battery current, voltage and temperature measurements.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Adds CAN RX-TX pin definitions to the CYW20829 package dtsi files where
supported.
Adds canfd0 wrapper and can0/can1 channel nodes to cyw20829.dtsi.
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: John Batch <john.batch@infineon.com>
DeviceTree:
- Adds CAN RX-TX pin definitions to the PSE84 package dtsi files where
supported.
- Adds canfd0 wrapper and can0/can1 channel nodes to the pse84.dtsi and
pse84_s.dtsi files.
- Adds m55 core overrides for can interrupts.
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: John Batch <john.batch@infineon.com>
Adds the following bindings:
- infineon,canfd-controller: Wrapper node for shared CAN controller
registers. Includes timestamp-counter and ecc-enabled properties
for enabling a global timestamp counter and ECC.
- infineon,can: Individual CAN channels, an extension of the
bosch,m_can-base.
DeviceTree:
- Adds CAN RX-TX pin definitions to the PSC3 package dtsi files where
supported.
- Adds canfd0 wrapper and can0/can1 channel nodes to the psc3.dtsi and
psc3_s.dtsi files.
Extends work started by Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
Co-authored-by: Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
Co-authored-by: John Batch <john.batch@infineon.com>
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: John Batch <john.batch@infineon.com>
Add a regulator driver for the internal general-purpose LDO channels
found in some Espressif SoCs. These LDO channels can supply power to
internal and external peripherals such as SPI flash and PSRAM.
The driver supports:
- Enable/disable LDO output channels
- Continuously adjustable voltage from 500mV to 2700mV
- Rail bypass mode at 3300mV
- Standard regulator device tree properties (boot-on, always-on, etc.)
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Implement a device driver for XSPI manager.
This allows to define the xspi controllers configuration that should
be applied towards the xspi IO ports:
- Muxed
- Swapped
- ...
Since its configuration has impact on final application location and
implies the deactivation of xspi clocks, it should be run only at fsbl
stage and not later.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The driver implements the QEMU ramfb as a framebuffer-based display.
It only implements the basic capabilities necessary (ARGB8888) with
resolution configurable via DTS. For initialization it uses the fwcfg
driver.
Signed-off-by: Maximilian Zimmermann <gitmz@posteo.de>
1. Keep drivers/timer/cortex_m_systick.h as a compatibility
shim for legacy Cortex-M-specific names.
2. Switch to use the generic low-power companion timer API
for the Cortex-M SysTick driver.
3. Mark the global CORTEX_M_SYSTICK_LPM_* kconfig options
as 'DEPRECATED' and replace them with SYSTEM_TIMER_LPM_*
4. Rename 'zephyr,cortex-m-idle-timer' to
'zephyr,system-timer-companion'
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
NXP MCXL25x SoCs are not supported.
Add initial dts with peripherals needed for
Hello World and GPIO examples on cpu0 only.
Aon domain clock controls are modeled by fixed-clock
for the initial enablement. The aon clock configuration
corresponds default clock configuration.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Add all device nodes for flexcan on i.MX 95 A55 platform.
Signed-off-by: Jianchao Wang <Jianchao.wang_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Properly declare the io-channel-cells for the samd5x DAC binding for use
with the DAC DT spec helpers.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Properly set #io-channel-cells = <1> for the NXP GAU DAC driver, which does
in fact support output channel binding.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Add the ability to specify channel details in devicetree, and enhance the
DAC API to support a new struct dac_dt_spec with corresponding DT helper
functions:
- dac_channel_setup_dt
- dac_write_value_dt
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
