Add non-cacheable memory support on the esp32p4 by reserving a
power-of-two window at the top of HP SRAM and marking it
non-cacheable with a PMA NAPOT entry at boot. The window keeps its
normal cached address so it stays reachable by the DMA engine,
while CPU accesses bypass the cache, so both masters see coherent
data through one address.
The region size comes from the sramhp_nocache devicetree node and
the base is derived per silicon revision, whose SRAM and cache
layouts differ. The PMA entry is re-applied on wake from standby
because the PMA CSRs are volatile across CPU power-down sleep.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The comparator nodes had address-cells and size-cells
without ranges or a child reg property causing warnings
at build time. Removed them as they are unnecessary.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Adds support for the TI TLA2528 I2C ADC with GPIOs.
The TLA2528 is a 12-bit 8-channel ADC, where each channel can also be
configured as a GPIO in- or output in push-pull or open-drain.
Signed-off-by: Oliver Schmidhauser <oliver.schmidhauser@leica-geosystems.com>
Add esp32c5 and esp32p4 support to the esp32 mailbox driver. The HP and
LP cores signal each other through the PMU software interrupt, the same
mechanism used on the esp32c6, with the esp32p4 LP interrupt status bit
handled per its register layout.
The esp32p4 LP core uses a multi-vectored interrupt controller that
jumps directly to the handler, so tag the LP PMU handler with
LP_CORE_ISR_ATTR so it saves and restores registers and returns with
mret; on the single-vector esp32c5 and esp32c6 the attribute is empty.
Also shrink the esp32p4 LP ulp_ram region so it stops before the shared
ulp_shm block that holds the mailbox coordination data, matching the HP
view and preventing the loader from clobbering it.
Mark the esp32c5 and esp32p4 mailbox nodes okay to match the other socs.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Add power management support for Infineon PSOC4 for Deepsleep.
- Configure Watchdog Timer as the wakeup source.
Signed-off-by: Deepika R <deepika@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Niranjan M <niranjan@aerlync.com>
Add support for the counter capture API to the MCUX CTIMER driver.
The driver stores capture callbacks per channel, maps Zephyr edge
flags to CTIMER capture modes, enables capture interrupts, and reports
captured TC values from the CTIMER CR registers.
Capture is mutually exclusive with alarms on the same channel because
both features share the counter channel namespace. Add optional
pinctrl and INPUTMUX routing support so boards can route CTIMER capture
sources from devicetree without changing the public counter API.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add three TDM DAI instances (tdm_dai0/1/2) and one unified
acp_tdm_dma DMA controller node to the ACP 7.X device tree.
Update dma-channels default to 6 (2 per instance x 3 TDM
instances) in Kconfig.acp_tdm.
Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
Signed-off-by: Sneha Voona <sneha.voona@amd.com>
SSD1680 supports RAM ping-pong for display mode 2 through the display
option register. Enable F[6] when switching to the partial refresh
profile so partial updates can use the controller's buffer swap behavior.
Expose this as a "ram-ping-pong-mode2" devicetree property on the
SSD1680-specific binding.
Signed-off-by: Aleksandrs Sevastjanovs <sevalks@gmail.com>
Replace the CONFIG_SOC_MCXW70AC / CONFIG_SOC_MCXW716C Kconfig guards
that conditionalize SIRC hardware access with a new DT boolean
property 'sirc-supported' on the nxp,mcxw7x-clock binding.
MCXW70 and MCXW71 carry the SIRC hardware block; MCXW72 (MCXW727C)
does not - its SIRCCSR register block was removed from the SDK
headers, making kCLOCK_ScgSircClk, CLOCK_UnlockSircControlStatusReg,
scg_sirc_config_t, kSCG_SircEnableInSleep and CLOCK_InitSirc
undefined at build time for frdm_mcxw72.
Set sirc-supported in the MCXW70 and MCXW71 clk_ctrl DT nodes.
Leave it absent on MCXW72 so DT_INST_PROP(0, sirc_supported)
evaluates to 0 at compile time, bypassing all three affected sites:
- get_rate() FRO_6M: fall back to the fixed 6000000U constant
- clock_control_init(): skip CLOCK_UnlockSircControlStatusReg()
- clock_control_init(): skip the SIRC LP-mode init block,
which also bypasses enable_sirc_in_lp_mode
Move enable-sirc-in-lp-mode out of nxp_mcxw7x_common.dtsi (where
it was incorrectly inherited by MCXW72) into the MCXW70/MCXW71
per-variant DTS nodes.
Tested: west build -p=always -b frdm_mcxw72 tests/lib/cpp/cxx
builds cleanly after this change.
Signed-off-by: Allen Zhang <chunfeng.zhang@nxp.com>
Add a required ngpios property to the BCM2711 pinctrl binding
and set it in the SoC dtsi. Update the driver to read the number
of GPIOs from devicetree via DT_INST_PROP.
This makes the GPIO count explicit in devicetree and avoids
hardcoded assumptions in the driver.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Series 0 and 1 have 32768 Hz low-frequency oscillators, while
DT_FREQ_K(32) is 32000 Hz.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The MCXW7x clock controller configured the OSC32K 32 kHz crystal
oscillator with an 8 pF internal load capacitance (cap value 4) on
both the XTAL and EXTAL pins, and hardcoded the amplifier coarse
gain to Range0. This configuration leads to a clock precision issue
of around 180 ppm on the 32 kHz clock.
A 16 pF internal load capacitance is the best configuration to
achieve the best precision, together with a per-SoC coarse amplifier
gain. Fix the default configuration:
- Use a 16 pF internal load capacitance on XTAL and EXTAL.
- Add an osc32k-coarse-adjustment devicetree property so the coarse
amplifier gain is configurable (the driver previously forced
Range0), and wire it into the CCM32K oscillator config.
- Set the coarse gain per SoC: Range3 on MCXW72, Range1 on MCXW71.
MCXW70 is aligned with MCXW72 (Range3).
Also add named dt-bindings macros for the OSC32K load capacitance
(MCXW_CLK_OSC32K_CAP_*pF, value N maps to 2*N pF) and coarse gain
(MCXW_CLK_OSC32K_COARSE_RANGE*) so the devicetree no longer relies
on opaque magic numbers.
Built samples/hello_world for frdm_mcxw70, frdm_mcxw71 and
frdm_mcxw72 and verified the generated devicetree resolves to 16 pF
caps with coarse gain Range3 (W70/W72) and Range1 (W71).
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Remove the default value for DT properties that are required.
Edtlib.py mandates DTS files to provide a value for required properties
even when a default value is defined in the YAML file hence no functional
changes.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Several peripheral reg sizes in rv32m1.dtsi are too small and do not
cover their full documented register maps.
Update the affected ranges to match the actual peripheral layouts:
gpio*: 0x14 -> 0x40 PDDR @ 0x14 ends at 0x18; 0x40 matches
the 0x40-aligned port slots and every
other Kinetis dtsi (nxp_kw41z, nxp_k6x,
nxp_k2x, nxp_k8x, nxp_ke1x*).
lpuart*: 0x2C -> 0x1000 WATER @ 0x2C ends at 0x30; 0x1000
matches nxp_k8x and nxp_k32l2b3.
lpi2c*: 0x170 -> 0x1000 SRDR @ 0x170 ends at 0x174; 0x1000
matches the 0x1000-spaced layout.
pcc*: 0x200 -> 0x1000 CLKCFG[130] runs to 0x208; 0x1000
matches nxp_ke1xf/nxp_ke1xz.
intmux1: 0x20 -> 0x200 Typo - intmux0 (same IP, same struct)
is 0x200.
Signed-off-by: Adrian Śliwa <asliwa@internships.antmicro.com>
Add missing #address-cells = <0> property to all IRQSTEER
interrupt-controller master nodes to eliminate devicetree warnings.
Adding #address-cells = <0> indicates that interrupt specifiers do
not contain address information, only interrupt number and flags.
Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
Add sar_adc node to nxp_imx952_m7.dtsi.
Enable it on imx952_evk M7 board and add adc to supported features.
Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
This patch adds driver support for TI ECAP module which can capture an
external input or work as a standalone APWM generator.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
ADd `brcm,iproc-pcie-ep-v2` to represent the version difference
with `brcm,iproc-pcie-ep`.
This property can replace the CONFIG_PCIE_EP_IPROC_V2.
So, we removed it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The TSTMR on i.MX93, i.MX943, i.MX95 and i.MX952 runs at 24 MHz
(sourced from the 24 MHz OSC). Correct the clock-frequency property
from the erroneous 1 MHz to 24 MHz in the respective dtsi files.
Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
Add ambiq,flash-controller and soc-nv-flash nodes to ambiq_apollo2.dtsi.
Correct the flash controller binding in ambiq_apollo4p_blue.dtsi. Add the
MRAM controller node to ambiq_apollo510.dtsi; no register base is needed
as the driver programs MRAM via bootROM helper functions.
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
This allows for more secure entropy, which is useful for e.g. Bluetooth or
OpenThread. The changes were adapted from xg12.dtsi.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Address parameter is not accepts zero leaded value expression
such as `@000`. Fix it to simple `@0`
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Enable STM32C5 PM integration in soc build and Kconfig, and add power
state definitions for STOP0 and STOP1 in stm32c5.dtsi.
Add soc-level PM implementation files for suspend-to-idle and poweroff
handling on STM32C5.
Assisted-by: GitHub Copilot:GPT-5.3-Codex
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add the lptim1 node to stm32c5.dtsi with clocks, reset, IRQ, and
U5-style LPTIM compatible strings.
This enables board-level selection of LPTIM as a low-power tick source
on STM32C5 targets.
Assisted-by: GitHub Copilot:GPT-5.3-Codex
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Switch the STM32 LPTIM timer driver from SoC-series checks to a
Devicetree compatible check for U5-style LPTIM instances.
Update STM32 dtsi files to advertise "st,stm32u5-lptim" alongside
the legacy compatible so the new detection path is used consistently.
Assisted-by: GitHub Copilot:GPT-5.3-Codex
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a dedicated Devicetree compatible for STM32 U5-style LPTIM
instances and include the common STM32 LPTIM binding schema.
This provides a stable compatible to key driver behavior on register
interface differences.
Assisted-by: GitHub Copilot:GPT-5.3-Codex
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove/move some properties to the correct place.
- Move interrupt-names properties to the dtsi level.
- Remove other properties that are already present in the
board dts/dtsi level.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Add the ESP32-P4 USB-OTG high-speed controller using the
espressif,esp32-usb-otg-hs binding and the internal UTMI PHY. The
high-speed PHY uses dedicated pins, so no pad configuration is
needed. Enable the controller on the function ev board.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Introduce a shared Espressif USB-OTG binding scheme and rename the
existing full-speed quirk to the speed specific
espressif,esp32-usb-otg-fs compatible. The internal PHY D+/D- pad
numbers now come from the phy-dp-pin and phy-dm-pin device tree
properties, so migrate the esp32s3 node accordingly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the ESP32-P4 USB-OTG full-speed controller node using the
espressif,esp32-usb-otg-fs binding, with the internal PHY D+/D- pad
numbers provided through the phy-dp-pin and phy-dm-pin properties.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Adds arch-level instruction memory API with functions
for memcpying / memsetting and determining whether a
region is in instruction memory. Implement API for
Xtensa and ESP32, with support for word granular access.
Adds definitions for instruction memory to
Xtensa ESP32 platforms.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Add DT nodes for TI's Enhanced PWM. This requires addition of a syscon node
as well to configure the timebase clock.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Add DT nodes for TI's Enhanced PWM. This requires addition of a syscon node
as well to configure the timebase clock.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
