zynqmp.dtsi: UART0 and UART1 reg sizes were set to 0x4c (the bare
register count), not the full 4 KB page window. Expand both to 0x1000
to match the ZynqMP memory map and ensure correct MPU region coverage.
zynqmp_rpu.dtsi: The GIC CPU interface (GICC) reg size was 0x100;
expand it to 0x1000 to cover the full 4 KB aperture. Also add the
missing #address-cells = <0> property required by the arm,gic binding.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Introduce SOC_XILINX_ZYNQMP_APU for ARM64 Cortex-A53 with MMU and
arm_arch_timer defaults. Build soc.c and arm_mpu_regions.c only for
the RPU variant; add ARM64 linker script for the APU.
Register zynqmp_apu in soc.yml and add dts/arm64/xilinx/zynqmp_a53.dtsi
with GIC-400 (GICD @ 0xf9010000, GICC @ 0xf9020000) and core PS
peripherals: UART0/1, TTC0-3 timers, and ARMv8 arch timer.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Commit 5d1241dd17 ("atmel: migrate samd21 to mapped-partition")
added a ranges property to the shared samx2xx1x dtsi files (including
samx2xx18.dtsi, used by samc21n_xpro) but only added the matching
address/size cell declarations to samd2x.dtsi, not samc2x.dtsi.
Without #address-cells/#size-cells on the samc2x flash0 node, the
devicetree tooling falls back to the spec default of #address-cells=2,
so the 3-cell ranges no longer validates against the required 4-cell
layout. This surfaces as a build error on any samc2x board that
declares a partitions child under flash0, e.g. samc21n_xpro:
'ranges' property in flash@0 has length 12, which is not evenly
divisible by 16 (= 4*(2 + 1 + 1))
Mirror the samd2x.dtsi fix: add ranges to the nvmctrl node and
samx2xx1x dtsi validates correctly.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support for selecting eMMC HS400 Enhanced Strobe (HS400ES) when
supported by both the card and host.
Track enhanced strobe state in sdhc_io so hosts can apply it through
sdhc_set_io(). Add the corresponding host capability and devicetree
property, and decode STROBE_SUPPORT from EXT_CSD[184].
Enter HS400ES directly from HS timing using 8-bit DDR with the strobe bit
set, then configure HS400 signaling with enhanced strobe in the host I/O
state. Clear residual enhanced-strobe state during SDHC I/O initialization.
Signed-off-by: Piter Zhang <zhangtdvip@163.com>
The type for the `clocks` and `resets` standard properties is already
defined by base.yaml and reset-device.yaml respectively. Don't provide
it again in the VREFBUF binding.
While at it, also move these properties below `reg` to group all
standard properties together.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Updated QEMU AIA board variants to implement the ISA extensions SMAIA
and SSAIA as defined in the AIA specification.
Signed-off-by: Omar Naffaa <onaffaa@qti.qualcomm.com>
Extend bflb_rf_init() to support WiFi mode (WL_API_MODE_ALL) with
TX power targets and country code configuration when CONFIG_BFLB_WIFI
is enabled.
Add WiFi platform glue: MAC ISR wiring, task creation, low-power
stubs, wl80211 RTOS primitives (heap, RNG, timers), and the linker
section for WiFi shared RAM.
Introduce CONFIG_BFLB_BL61X_WL_RMEM_SIZE for PHY/RF retention memory
sizing.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add the wifi0 node for the BL61x WiFi MAC peripheral at 0x24b08000
with its devicetree binding.
Introduce bl61x_em_32kb_wifi.dtsi which carves 128 KB from WRAM for
WiFi MAC shared structures (TX/RX descriptors, IPC) via the
non-cached bus-remap alias, and scales sram1 down to 32 KB.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add a GPIO nexus binding for ESP-01 module headers.
Document the connector labels in the shield porting guide so boards and
shields can describe ESP-01-compatible headers consistently.
Signed-off-by: Duc Viet Le <levietduc0712@gmail.com>
Add a GPIO nexus binding and STMod+ pin constants.
This lets boards expose GPIO-capable STMod+ pins with stable
symbolic names, so shields do not hard-code board MCU pins.
Signed-off-by: Duc Viet Le <levietduc0712@gmail.com>
Update the driver used for ESP32, ESP32-S2 and ESP32-S3 to the
latest version and add support for ESP32-P4.
Signed-off-by: Tiago Medicci <tiago.medicci@espressif.com>
The Wi-Fi firmware needs a crystal oscillator (XO) frequency offset trim
for its calibration. This is a board-level value that depends on the
crystal, so express it in devicetree rather than sourcing it from a
fixed register.
Add a nordic,wifi-xo-freq-offset property to the nordic,nrf7120-wifi
binding (default 0) and set it on the nRF7120 DK.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Assisted-by: Claude:claude-opus-4.8
Add the power-state nodes (runtime-idle, suspend-to-idle,
standby and the opt-in suspend-to-ram / Deep Power Down),
the SPC, WUU and VBAT system module nodes, and the LPTMR0
WUU wakeup routing to the MCXA5x devicetree.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Include wuc-device.yaml in the gpio-keys child-binding so a key node can
carry a "wakeup-ctrls" property describing the wakeup controller (for
example an NXP WUU external pin) that wakes the system when the button is
pressed. The property is optional, so existing gpio-keys users are
unaffected.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Promote the "wuu" node to the "nxp,wuc-wuu" binding and add
"#wakeup-ctrl-cells" so it acts as a WUC wakeup controller, and give
lptmr0 a "wakeup-ctrls" entry selecting the WUU internal-module source.
This lets the low-power code reach the wakeup through the WUC subsystem
instead of hard-coding the WUU module index in the SoC code.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Adds a gcm-ccm-supported property to the crypto driver.
This allows to enable or disable support for AES GCM and CCM,
providing flexibility to remove the functionality
if it's not needed.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
Add DTS definitions and bindings to enable the GPIO controllers
for Allwinner H618 SoC on the Orange Pi Zero 2W board.
Signed-off-by: Khai Do <dovankhai97@gmail.com>
- systick: split multi-statement lines into one per line (Zephyr style)
- ch32v103.dtsi: add missing reg property alongside ranges in flash0 node
Signed-off-by: Lucy Wong <mova845@outlook.com>
Add initial DeviceTree support for the Microchip SmartFusion2
M2S010 microcontroller family.
This commit introduces the base SoC description for the M2S010
platform together with the required Devicetree bindings used by
the SmartFusion2 architecture. The newly added bindings cover
clock configuration, flash controller support, interrupt
controller handling, and common SmartFusion2-specific properties.
Signed-off-by: Anton Vynohradov <vynohradov.external@bavariamatic.com>
After this commit, enabling CONFIG_PM=y will let the device enter EM2 (deep
sleep), which drops the power consumption from multiple mA into tens of uA.
While the chip may also support EM3 and EM4, EM0-EM2 are the only ones I've
tested successfully, so let's stick to those for now.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Combined with future commits, this allows decreasing power consumption. The
rtcc0 device can still be used a counter driver, it's just provided by a
different driver now (CONFIG_COUNTER_GECKO_STIMER).
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
The NXP MCXE31x Wake-up Unit (WKPU) is register-compatible with the
S32K3 WKPU already supported by the intc_wkpu_nxp_s32 driver: same
register map, base address 0x402B4000, IRQ 83, and 64 wake-up
sources. Bind the MCXE31x WKPU node to that driver by switching its
compatible from the placeholder "nxp,wkpu" (which had no binding or
driver behind it) to "nxp,s32-wkpu".
Every SoC that instantiates this controller exposes 64 wake-up
sources, so generalise NXP_S32_WKPU_SOURCES_MAX to a plain
"default 64" instead of a per-SoC-series default; the range 32-64
still lets a future 32-source part override it.
The node lives in the shared nxp_mcxe31x_common.dtsi, so this enables
the WKPU on MCXE315/316/317/31B. The driver source itself is not
modified.
Verified on frdm_mcxe31b: the WKPU device binds and initializes, and
an RTC-timeout event (WKPU internal source 1) triggers the WKPU ISR.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The ADTM is a superset of the GPTM and has the same core register
layout. See section 11.2.2 of the CH32V003RM for details on the
differences.
Use the same technique as the GD32 driver, i.e. use the same basic
driver with tweaks based on the features.
Add the common 3x GTPM and 1x ADTM Devicetree and pinctrl entries for
the 20x and 30x series and the extra 1x GPTM for the CH32V208 used in
linkw. I can follow up with the other chips in a separate PR.
Tested on the ch32v006evt and linkw by running
`samples/basic/blinky_pwm` and `tests/drivers/pwm/pwm_api` and
checking the output with a logic analyser.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Wire the gdma driver to the esp32p4 AXI and AHB DMA instances,
selecting the per-bus LL calls and 8-byte aligned descriptors so
both buses work through the common driver.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a PWM trigger-source backend that drives the capture pad with a
static duty and loops it back to the capture input, so the loopback
test runs with no external wire on any board that provides a PWM
routed to its capture pad.
Signed-off-by: Sylvio Alves <sylviojalves@gmail.com>
Add counter capture support to the GP-Timer driver. A GPIO edge is
routed through the ETM to the timer capture task, latching the counter
value in hardware. Only available on ETM capable SoCs.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Some drivers or Kconfig item (for example: CONFIG_SDHC_BUFFER_ALIGNMENT
for imx_usdhc) depends on CONFIG_DCACHE_LINE_SIZE, but if the board use
CONFIG_DCACHE_LINE_SIZE_DETECT is enabled to detect cache size at runtime,
the value of CONFIG_DCACHE_LINE_SIZE will be NULL and will have some
building issue, in order to fix this issue, change all the boards of
i.MX 91 and i.MX93 to use fixed cache line size which is got from
dts property.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add the inputmux@40001000 and eqdc@400a7000 nodes to the MCXA SoCs that
provide the Enhanced Quadrature Decoder: MCXA153, MCXA156, MCXA344 and
the MCXA-xx6 common dtsi (MCXA266/346/366). A second eqdc@400a8000
instance is added on the parts that expose two EQDCs (MCXA156, MCXA344
and MCXA266/346/366); MCXA153 has a single instance. The eqdc nodes are
disabled by default and enabled through board overlays.
Co-authored-by: bnina-ayoub <ouba.bnina@gmail.com>
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a sensor driver for the NXP MCUX Enhanced Quadrature Decoder (EQDC)
using the fsl_eqdc HAL. The PHASEA/PHASEB decoder inputs are routed
through the on-chip INPUTMUX, described by an "inputmux-connections"
phandle-array following the nxp,inputmux convention.
The driver exposes SENSOR_CHAN_ROTATION, SENSOR_CHAN_RPM,
SENSOR_CHAN_ENCODER_COUNT and SENSOR_CHAN_ENCODER_REVOLUTIONS; the last
channel is added to the sensor API. Velocity uses the EQDC period
measurement (POSDH/POSDPERH), so a prescaler keeps the 16-bit period
counter from saturating at the sample rate.
A single-phase-mode property selects single-phase decode (one count per
PHASEA pulse, with the direction taken from PHASEB) instead of the
default quadrature X4 decoding, with the counts-per-revolution scaling
adjusted accordingly.
Co-authored-by: bnina-ayoub <ouba.bnina@gmail.com>
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The LPC55S2x, LPC55S3x, and LPC55S0x SoC families carry the same
CTIMER peripheral IP as LPC55S6x and LPC55S1x: five instances at
identical base addresses (CTIMER0-4: 0x40008000-0x4002A000) with
the same IRQ numbers (10, 11, 36, 13, 37). Their SoC common dtsi
files were missing ctimer node definitions entirely; add ctimer0-4
to nxp_lpc55S2x_common.dtsi, nxp_lpc55S3x_common.dtsi, and
nxp_lpc55S0x_common.dtsi.
Enable ctimer0-4 on lpcxpresso55s28, lpcxpresso55s36, and
lpcxpresso55s06, and add counter to each board's supported
feature list.
Tested by building samples/hello_world and
tests/drivers/counter/counter_basic_api for all three boards.
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
- The TRNG frequency range as stated in mspm0l1117 datasheet is 9.5 to 25
MHz. Since the input is 32 MHz, the only divider that lies in the range
is 2. Also 2 is the clock divider that is used in the TI example.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Based on the DS18B20 driver. Only the temperature sensor functionality is
exposed by this driver, not eeprom access nor parasite power configuration.
Signed-off-by: Tomas Groth Christensen <tgc@foss.dk>
Add DT binding for Hall-effect pulse-output flow meters.
Supports a required pulse GPIO, an optional power GPIO, and a
pulses-per-liter integer property for calibration.
Signed-off-by: Nicolas Belin <nbelin@baylibre.com>
Add a controller and PHY driver for the BL808 UHS PSRAM. The PHY read/write
eye is calibrated at boot by sweeping the DQS/DQ delay taps and latency, so
any supported rate works without per-rate constants. Add the devicetree
nodes and enable on the M1S Dock.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add the UHS PLL, a dedicated PLL that feeds only the UHS PSRAM PHY. It is
outside the system clock tree and brought up on demand; the output
frequency comes from the clk_uhspll devicetree node.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add Zephyr memory region attributes to SRAM and TCMSRAM.
Mark F4xx backup SRAM (BKPSRAM) as non-volatile.
Signed-off-by: Egill Sigurdur <egill@egill.xyz>
Describe the switchable GD32A50x shared SRAM block as a separate memory
region, since the block can be used as a fast program buffer.
Signed-off-by: Egill Sigurdur <egill@egill.xyz>
