Add USB node to apollo510 qualifier, and apollo510_evb board to enable
USB support on the SoC and its EVB.
Signed-off-by: Chew Zeh Yang <zeon.chew@ambiq.com>
The CH32V003 has a 8 channel, 10 bit onboard ADC. Add an immediate
mode driver and the appropriate pinctrl bindings. Note that the
CH32V003 GPIO pins have both a floating input and an analogue input
mode, and the pinctrl is needed to put the pin in analogue mode.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Make axisram2 which is used in fsbl mode available as well to
chainloaded application in order not to loose 1M of RAM
In order to avoid conflicts with bootloader, verify that code + ro data
of the loaded application won't go further than bootloader start address.
This is done with a linker assert.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The WCH External Trigger and Interrupt controller (EXTI) supports
between 8 and 22 lines where each line can trigger an interrupt on
rising edge, falling edge, or both edges. Lines are assigned to a
group, and each group has a separate interrupt. On the CH32V003/6,
there is one group of 8 lines, while on the CH32V208 there are
multiple groups with between one and six lines per group.
In the same way as the STM32 and GD32, define an EXTI driver that
configures the peripheral and an internal interface that can configure
individual lines.
Signed-off-by: Michael Hope <michaelh@juju.nz>
RA8P1 has 14 ports (from 0 to d) and 32 external irq while current
driver support 12 ports (0 to b) and 16 external irq.
This add addtional support for remain ports and external irq to be
able to work with RA8P1.
Fix the lack condition GPIO_RA_IOPORT for GPIO_RA_HAS_VBTICTLR
config
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
STM32U0 specific changes to enable the PM feature.
Base on the power-related code from the STM32U5 target.
Signed-off-by: Mickael Bosch <mickael.bosch@linux.com>
Add support for trng, spi, pwm (gpt), counter (agt), i2c (iic_master),
adc and dac for RA2L1.
Add external interrupt for RA2L1.
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
1. The edma version 5 share one driver with edma 4.
2. Edma5 tcd structure some difference, Use tcd type to distinguish,
and Edma5 uses 64 bytes for alignment instead of 32.
3. Some platforms have some address offsets for certain memory
when processing from a DMA perspective, such as imx95 cm7 TCM,
so add offset processing.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
The CH32V20x and CH32V30x SoCs have 16 pins per GPIO bank, but in the
devicetree, `ngpios` was incorrectly set to 8.
Fix the devicetrees by setting the correct value.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
- Add support for gpio interrupt on RX130.
- Add support for gpio-keys input subsys on RSK_RX130_512KB boards.
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Add support for gating/ungating IMX8QM/IMX8QXP's ESAI clocks and the
AUD_PLL_DIV_CLK0 clock used as source for ESAI's EXTAL.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
The st,stm32-qspi compatible is defining the reg property
with the register address and size at first index
followed by the external mem base address and max allocated size.
For the stm32F412, stm32F7, stm32L4, stm32H7, stm32WB series.
qspi is addressing max 256 MBytes from 0x90000000.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Allow setting fifo-highres from DT, also unify the
naming of all registers and expand to a more complete list.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Add initial support for i2c on Renesas RX MCU
This driver is controlling the RIIC HW of RX MCU for i2c bus
interface on Zephyr
Only master mode is supported
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Add nPM1304 device tree bindings. Extract the properties common to
nPM1300 and nPM1304 into npm13xx-common files.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
