Add the flash controller node to the psoc4100smax SoC DTSI, wrapping
the existing flash0 node as a child of the controller. This mirrors
the structure already present in psoc4100tp.dtsi.
The flash controller is at CPUSS_BASE + 4 (0x40100004), with register
size 0x104, matching the psoc4100tp. The write-block-size and
erase-block-size are both 256 bytes, confirmed by
CPUSS_SPCIF_FLASH_PAGE_SIZE=3 in the HAL device config header.
This enables the FLASH_INFINEON_PSOC4 Kconfig option for boards
using the psoc4100smax SoC, such as the CY8CKIT-041S-MAX.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Add devicetree source files, clock definitions, interrupt mapping,
GPIO signal map, and pin control bindings for ESP32-C5.
Also add 8 MB flash partition layout with 0x2000 offset and extend
the espressif,riscv CPU binding to accept 48 MHz XTAL frequency.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Adds the support of timers for STM32C5. This includes all timer instances
for the series, and the support of the counter, PWM and QDEC drivers.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add timer subnodes under the MAX32657 Wake‑up Timer device nodes to
enable system timer configuration in devicetree.
Also set default SYS_CLOCK_TICKS_PER_SECOND to 8192 if Wake-up Timer is
selected as system timer.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Introduce a system timer driver that uses the MAX32 Wake-up Timer as the
system tick source. This enables the MAX32 SoC family to use the WUT for
kernel timing operations.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Add an HCI driver for the BL702 on-chip BLE controller. The controller
is a precompiled binary blob communicating via vendor on-chip HCI
functions (bt_onchiphci_send/bt_onchiphci_interface_init).
The driver:
- Translates between Zephyr HCI net_buf and the vendor's internal
packet structures for both TX (commands, ACL data) and RX (events,
ACL data)
- Uses a dedicated RX thread with FIFO+semaphore to dequeue messages
from the controller callback (which may run in ISR context)
- Reads the BLE MAC address from eFuse during initialization
- Supports multiple controller binary variants via Kconfig choice
(peripheral-only, multi-role, observer, etc.)
- Provides proper open/close lifecycle with RX queue draining
Also adds the DT binding (bflb,bl70x-bt-hci) and a bt-hci node in
the BL70X SoC dtsi (disabled by default).
Signed-off-by: William Markezana <william.markezana@gmail.com>
# Conflicts:
# drivers/bluetooth/hci/CMakeLists.txt
Add driver for the QST QMI8658A 6-axis inertial measurement unit
with accelerometer and gyroscope. Supports I2C bus, configurable
full-scale range and ODR via devicetree, temperature readout, and
optional data-ready interrupt trigger on INT2.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add QST Corporation to the list of known vendor prefixes. This is
needed for the QMI8658A IMU sensor driver.
Signed-off-by: William Markezana <william.markezana@gmail.com>
The edma0 interrupts list had 16 entries (IRQs 0-15) but
was missing DMA_ERROR_IRQn (IRQ 16). The eDMA driver treats
the last entry as the error IRQ, so IRQ 15 (DMA15_DMA31
transfer-complete) was misused as the error handler. This
broke DMA channels 15 and 31 entirely.
Add <16 0> as the 17th entry.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Add the CRC peripheral to DTSI of STM32 SoCs.
(Note: CRC is not added to SoC series STM32F1, STM32F2, STM32F4, STM32L1
and some STM32F0 SoCs because their CRC peripheral is not supported by
the driver due to HW limitations - this matches the binding's description)
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a binding for the STM32 CRC calculation unit. Note that this binding
only covers the programmable variant of the CRC peripheral: the older CRCv1
found in series such as STM32F1/F2/F4/L1 and some STM32F0 products is not
supported due to HW limitations.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Create a dts property specifying clock tolerance and add it
to affected i2c instances. The property is to be used in
the i2c driver to ensure the actual SCL frequency does not
exceed the value in "clock-frequency".
Signed-off-by: Michał Bainczyk <michal.bainczyk@nordicsemi.no>
Add all device nodes for flexcan on i.MX 943 A55 platform.
Signed-off-by: Jianchao Wang <Jianchao.wang_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Removes resource reservation for cpuflpr from the cpuapp build and
only applies it when either of the flpr snippets are used
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Track success explicitly and only report timeout when no matching PHY ID
was found after all retries.
Extend the Motorcomm YT8521 PHY driver to support YT8531 chip.
The YT8531 is compatible with YT8521 and shares the same register
layout and configuration interface.
- "motorcomm,yt8521" for YT8521
- "motorcomm,yt8531" for YT8531
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add device tree for STM32C5 series, including all SoCs,
all GPIOs and (LP)U(S)ART nodes.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
- Define the HCI node in the SoC series' dtsi.
- Adjust main thread stack sizes and buffer counts required
for Blutooth operation.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Added Silabs Kconfig support for counter driver and implemented the
counter APIs using protimer underneath.
Signed-off-by: sree sreerajatha <sree.sreerajatha@silabs.com>
Remove ranges property in partition node for rtl8752h, otherwise
the CONFIG_FLASH_LOAD_OFFSET would be wrong.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Switch the common keyboard matrix binding to use microseconds for its
polling interval properties.
Rename the properties and change their units:
- poll-period-ms -> poll-period-us
- stable-poll-period-ms -> stable-poll-period-us
Devicetrees must update the property names and convert
values from milliseconds to microseconds.
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
- Removes the unused items from the device structures for peri clock.
- Removes the now unused `resource-type`, `resource-instance`, and
`resource-channel` binding properties.
- Updates the Migration Guide with removed binding properties.
- Remove the binding properties from board, samples, and test overlays.
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: John Batch <john.batch@infineon.com>
Add Third Reality, Inc. to the devicetree vendor prefix registry
for use with ThirdReality board definitions.
Signed-off-by: Camille BAUD <mail@massdriver.space>
Fixes the mix-up of HCLK and SYSCLK in h7 clock driver and also makes sure
to calculate the correct startup frequency:
- Take care of bootloader might already have configured clocks instead of
relying on #defines/dts).
- Use HAL HSI_VALUE instead of STM32_HSI_FREQ which can be 0 if hsi node
is disabled in DT (but is default on after reset...)
Also move calculation of old_hclk_freq above set_up_plls() during
stm32_clock_control_init(), which can change the current clock setting and
make it impossible to get the previous clock.
Remove not needed special handling for h7rsx controllers.
Add a comment to the clk_hsi node in the h7x / h7rsx DT stating that the
clock is enabled by default after reset.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
Nordic's nPM10 Series PMIC Multi-function Device devicetree properties and
driver.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Introduce the new stm32h5e4, stm32h5e5, stm32h5f4, stm32h5f5 mcu
The Xj variant has 4MB of internal flash whereas the Xk variant has 3MB.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add Silabs General GPCRC driver for Series 2 boards
Enable crc sample and test cases for Silabs series 2
Tested on real boards and compared result with all CRC16
and CRC32-IEEE algorithm
Signed-off-by: Phuc Hoang <donp172748@gmail.com>
Increase SCMI shared memory region from 256 bytes to 4KB to support
larger SCMI message payloads required for clock and power domain
operations.
Signed-off-by: Soumya Tripathy <s-tripathy@ti.com>
