This is mainly testing purpose from native_posize ethernet
driver. Enable CONFIG_ETH_NATIVE_POSIX_VLAN_TAG_STRIP to have
VLAN tag strip feature on ethernet Rx frames.
Signed-off-by: Ravi kumar Veeramally <ravikumar.veeramally@linux.intel.com>
We shall not enable by default a system timer in ARM
platforms, namely the SysTick, the Nordic, or the SAM0
RTC timer, simply by assessing the hardware capabilities
(e.g. by conditioning on CPU_CORTEX_M_HAS_SYSTICK).
Instead, now, all ARM platforms needs to explicitly set
their system timer module. Note that this has already
been the case for ca 80% of the ARM platforms.
This clean-up allows us to decouple HW capabilities from
system configuration (for example, Nordic platforms may
enable option CPU_CORTEX_M_HAS_SYSTICK, and still use
the platform-specific RTC timer for system timing).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit renames the symbol CPU_HAS_SYSTICK to
CPU_CORTEX_M_HAS_SYSTICK, to look similar to all
other CPU_CORTEX_M_HAS_ options, and moves the
K-config symbol definition from arm/core/Kconfig to
arm/core/cortex_m/Kconfig.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
For example it should be possible to compile and use the SLIP module
with NET_L2_DUMMY. This required the following changes:
* Fix a typo in the initializer for struct dummy_api
* Only define eth_capabilities if CONFIG_NET_L2_ETHERNET is defined to
silence a -Wunused-function compiler warning
* Unconditionally include net/dummy.h
Signed-off-by: Sören Tempel <soeren+git@soeren-tempel.net>
Without this change compilation of the SLIP module would fail if LLDP
wasn't enabled. There is also no need to include net/lldp.h explicitly
as net/ethernet.h will include it conditionally if CONFIG_NET_LLDP is
defined.
Signed-off-by: Sören Tempel <soeren+git@soeren-tempel.net>
Enabling the RTC event is intended to support peripheral-to-peripheral
interconnects, so introduces a request for HFCLK and PCLK16M when the
event is triggered. This specific event is never used with PPI so
enabling events apparently does nothing but increase power consumption.
Closes#15513
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Statistic for flash has limitation regards number of pages possible to
be counted. This path introduces check for that in source file as it is
not possible to preserve the limit in Kconfig.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
This commit adds a flash driver implementation that writes to RAM and
exports statistics through stats.h. It can be used to simulate flash
memory for testing purposes.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
When there is no need to divide the PWM clock (i.e. the requested
period cycles fit the 15-bit PWM counter), the prescaler value
should be 0, not 1.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The GPIO driver for the Intel Apollo Lake has so many pins it has to
export ten devices to shoehorn its one device into the GPIO API. The
current implementation uses the shared IRQ driver because these
pseudodevices all share one IRQ. However, since the GPIO driver is
aware of all the possible interrupt sources, it's smaller and faster
(and not even messy) to handle it internally, so this patch eliminates
the dependency on the shared IRQ driver.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Provide access functions for manipulating network interface flags.
There is no need for the caller of this API to know about the inner
details of the flags.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Migrate from "legacy" PCI support (drivers/pci) to new PCI(e) support.
The e1000 driver is merely for testing with QEMU and so should not be
a model for the use of PCI(e) functions. Consult instead "real-world"
PCI(e) drivers like the NS16550 UART (drivers/serial/uart_ns16550.c).
Signed-off-by: Charles Youse <charles.youse@intel.com>
Make sure that when e.g. CONFIG_SERIAL is set, CONFIG_UART_SAM0 is
selected automatically when the sam0 SoC family is used.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Add GPIO support to stm32wb series.
Only ABCDE and H ports are available for now on this series.
Accordingly, update series dtsi file.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support to stm32wb series in stm32 clock_control driver.
Ip is similar to stm32l4 one but AHB bus presacler is renamed
to "CPU1" and CPU2 and AHB4 prescalers should be defined.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Implementation of AMS (Austria Micro Systems) ENS210 temperature and
relative humidity sensor.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
In order to generalize the currently specialized nRF51 IC setup hook,
make the following changes:
- Generalize the hook to bt_ic_setup()
- Use a weak NOP version by default
- Move the currently existing one to the board folder
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
nRF9160 can't provide FICR data while operation in non-secure
domain.
This patch start using flash layout properties provides by
nrfx API for get flash properties, which resolves problem
described above.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Introduce nrfx_nvmc driver into nordic flash driver implementation.
Thanks to that nrf9160 SoC becomes supported by the driver.
nrfx helps dealing with differences with interface to the NVMC
in secure and non-secure execution modes.
This patch adds NRFX_NVMC Kconfig entry for enabling nrfx_nvmc and
select it along with nordic flash driver.
Disabled UICR operation on nRF9160 for non-secure build
as UICR is not available in this mode.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Add driver support for Atmel SAM0 device ID, which is 16-bytes long.
The device ID can simply be read from memory at a known location, but
the location is only described in the data sheet, not in ASF.
For SAMD2x it's 0x0080A00C, 0x0080A040, 0x0080A044 & 0x0080A048.
For SAMD5x it's 0x008061FC, 0x00806010, 0x00806014 & 0x00806018.
This adds a new property to the device tree to define the device ID
registers for this SoC family.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Added option to have LFCLK synthesized from HFCLK. It is not low
power but ensures constant relation between HFCLK and LFCLK and
might be useful in certain scenarios (e.g. testing).
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add driver and device tree binding for the Low Power Inter-Integrated
Circuit (LPI2C) controllers found in the RV32M1 RI5CY SoC.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Use the RV32M1 SoC intmux driver initialization priority set by
Kconfig. Change the default to match the default value of 40 used
before.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
I does make sense to use index only after we make sure it is valid,
issue is found in harness tests.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
In stereo case the pdm stream continuosly alternates 1-bit from
the left channel with 1-bit from the right channel. In this case
we need first to demultiplex channels bits on byte basis.
Then the Open_PDM_Filter library has to be called twice, one for
each channel.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
This commit adds CAN support for nucleo F746zg.
Furtermore CAN was added in stm32f7.dtsi and pinmuc_stm32f7.h
CAN_RX: PD0, CAN_TX: PD1
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
Add support for pulsing the hardware reset pin of the FXOS8700 high
during initialization.
According to the datasheet, this is required for the I2C/SPI bus
auto-detection logic to work properly if the VDD/VDDIO power
sequencing order cannot be guaranteed.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
gpio_intel_apl_read() should set *value to 1, not 2, when the
GPIO input is a logical high.
Fixes: #15499
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
For STM32L47x/48x series devices, register ASCR should be configured to
connect analog switch of gpio lines to the ADC.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Allows to enable initial RTS/CTS hardware flow control
in the dts.
Co-authored-by: Benoit Leforestier <benoit.leforestier@gmail.com>
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
