Update mbedTLS commit along with the following fixes:
* Fix naming inconsistencies in some cipher modes, to match core mbedTLS
configs
* Add Kconfig to enable CTR cipher mode
Fixes#22421
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
During communication initialisation, the IMSI of the inserted SIM
card is evaluated to determine the APN. This is done by comparing
the first 5 characters of the IMSI to a list of known providers.
The list can be given in Kconfig.
To enable this functionality, set following bool in Kconfig:
MODEM_UBLOX_SARA_AUTODETECT_APN
To set a list of providers, set following string:
MODEM_UBLOX_SARA_AUTODETECT_APN_PROFILES
If the provider can not be found in the list, the APN given in
following entry is used as a fallback:
MODEM_UBLOX_SARA_R4_APN
Signed-off-by: Hans Wilmers <hans@wilmers.no>
The modem type (Sara R410 or Sara U201) is detected automatically after
hardware initialisation of the modem. Further initialisation and
functionality is then chosen depending on the detected modem type.
To enable this functionality, set following bool in Kconfig:
MODEM_UBLOX_SARA_AUTODETECT_VARIANT
Signed-off-by: Hans Wilmers <hans@wilmers.no>
Many chips have only one serial port. When the serial port is occupied
by other devices, there is a lack of a console to output debugging
information. Semihosting can provide a console. The disadvantage of
semihosting is that a debugger must be connected, so it can only be
used for online debugging.
Signed-off-by: ZhongYao Luo <LuoZhongYao@gmail.com>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add initial support for Decawave DW1000
IEEE 802.15.4-2011 UWB transceiver.
Driver has basic functionality. Additional functions such
as reading out timestamps and delayed TX were implemented
for test purposes, but also require support in the 802154
subsystem.
Register, sub-register, and defaults defines in the file
ieee802154_dw1000_regs.h are taken from the Decawave's
DW1000 driver for the Mynewt OS.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Add support for ADC on H7 series. Note that ADC1 and ADC2 share the same
register set, so it is added as "adc1_2".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Like stm32 L4 does,
when the STM32WBx SoC goes into STOP mode, the SPI device is disabled.
This cause the pins to not be drived anymore (i.e. they are floating)
except through their pull-up or pull-down.
From the logical point of view, the NSS pin is held high by a pull-up
so it's not a problem if the other pins are floating. However those pins
are floating input for the slaves, which increase their power
consumption.
The solution is to hold the state of the pins through a pull-up or a
pull-down. This is already done for the NSS and MOSI pins, but not for
SCK. Fix that by using pull-down on the SCK pin the same way it is
already done for the MOSI pin.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Convert i2s_sam_ssc driver to utilize devicetree. We replace Kconfig
options for specifying the DMA configuration (channel, DMA device name)
with getting that from devicetree. We also get pincfg from devicetree,
however we still have Kconfig sybmols to specify if the RF or RK pin is
enabled.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert sam_xdmac driver to utilize devicetree. As part of the
controller binding we specify that dmas should contain a channel and the
perid for the DMA transaction.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The conversion in 9b096f40b6 left out a
few tidbits that were not converted properly. Complete the conversion
properly.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Remove semicolon between instance invocations of DT_FOREACH_IMPL_ and
thus DT_INST_FOREACH. This provides more flexibility to the user. This
requires we fixup in tree users to add semicolon where needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
MCHP Soc operation uses clear-on-write register for interrupt
status, read-OR-write operation may clear interrupts unintentional.
Fixes#24464
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Attached Flexcomm SPI driver to the main clock used by the core.
This means setting the SPI clock the same value as the core clock.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This fixes some cases where an integer timeout received as a parameter
was not converted to a timeout before being used in standard API.
Changes to the POSIX library were not included as that's being
reworked in a separate PR.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The DS3231 is an I2C real-time clock with internal temperature
compensated oscillator, maintaining civil time to 1 s precision with
nominal 2 ppm accuracy from 0-40 Cel.
The basic functionality is exposed as a counter that is always running
at 1 Hz. Much more functionality is exposed as driver-specific API,
including the ability to translate between the time scale of the DS3231
and the time scale of the Zephyr uptime clock. This allows correlation
of events in the system clock to UTC, TAI, or whatever time scale is
used to maintain the DS3231.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Add a driver that can handle several instances of AT45 family chips,
which are enabled by specifying DT nodes for them with the "compatible"
property set to "atmel,at45" and other required properties like JEDEC
ID, chip capacity, block and page size etc. configured accordingly.
The driver is only capable of using "power of 2" binary page sizes in
those chips and at initialization configures them to work in that mode
(unless it is already done).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
referring the ARM's Systick driver, we did the following improvements:
* use 31 bits of 32-bit counter to avoid the rare but possible
overflow of elapsed(). If 32 bits val are used, elpased() may
return a wrong value. then wrong HW cycles.
* two ways to update the correct cycles
- through systick timer irq
- when systick timer irq cann't be handled because of irq
locked/disabled, call z_timer_cycle_get_32->elapsed to update
the correct cylces. no more than one counter-wrap is allowed.
* if elapsed() is not called too long (more than one counter-wrap) from
systick tiemr irq or from z_timer_cycle_get_32. The lost of HW cycles
is unavoidable.
* some detailed discussion can be found in #24332
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Fix use of DT_HAS_DRV_INST which does not exist.
Use DT_HAS_NODE_STATUS_OKAY(DT_DRV_INST(n)) instead.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Provide basic commands that are useful when testing a LoRa
radio. Currently, the shell supports:
> lora conf ...
> lora send ...
> lora recv ...
> lora test_cw ...
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Add an API to transmit a continuous wave at a fixed frequency. This
functionality is useful to test the radio in a lab setup.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Add basic driver for GIC V3 interrupt controller.
This implementation supports
- distributor, re-distributor and cpu interface initialization
- configuration and handling of SPI, PPI and SGI.
- V2 Legacy mode is not supported and uses system interface.
Current implementation supports GIC secure state only.
All interrupts are routed to Secure EL1 as 'irq' by configuring
them as Group1 Secure.
TODO:
- MPIDR based affinity routing setting.
- percpu redistributor probe
- message based SPI and SGI generation api
- EL1NS support. Legacy mode support.
- LPI/ITS is not supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Port the I2S and DMIC drivers to the new timeout API so that they do
not need to enable legacy timeouts.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
As we phase out per instance Kconfig symbols convert to utilize
DT_DRV_INST to initialize CAN instances.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As we phase out per instance Kconfig symbols convert to utilize
DT_DRV_INST to initialize CAN instances.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a build-time assert to check that the configured SHM_SIZE
does not exceed the memory allocated as shared memory. USe DT
to extract the shared memory size.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The sam0 has a page size of 64 bytes, making it incompatible with
the nvs driver that specifies a maximum write block size of
32 bytes. When CONFIG_SOC_FLASH_SAM0_EMULATE_BYTE_PAGES is set,
it should report a write block size of 1 byte, which is compatible
with nvs.
Signed-off-by: Adam Serbinski <aserbinski@gmail.com>
The dpd-wake-sequence has a value that is an array of three integers,
which was formerly indexed by a suffix on the property name. This was
updated to new accessors but failed to separate the index from the
property name. Update the access idiom.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Convert to using DT_INST_LABEL() in the dma driver and convert dma users
to use the DMA property macros to get the dma controller name. We make
the assumption in the drivers that there is a single DMA controller
instance.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Had an extra comma between macro and macro usage that casued the
following compile error:
adc_shell.c:477:22: error: expected expression before ',' token
Easy fix to remove trailing comma in ADC_SHELL_COMMAND
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Clean up as we wish to move away from using these Kconfig settings.
Also removing them from the boards' default config.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Make drivers multi-instance wherever possible using DT_INST_FOREACH.
This allows removing DT_HAS_DRV_INST in favor of making drivers just
do the right thing regardless of how many instances there are.
There are a few exceptions:
- SoC drivers which use CMake input files (like i2c_dw.c) or otherwise
would require more time to convert than I have at the moment. For the
sake of expediency, just inline the DT_HAS_DRV_INST expansion for
now in these cases.
- SoC drivers which are explicitly single-instance (like the nRF SAADC
driver). Again for the sake of expediency, drop a BUILD_ASSERT in
those cases to make sure the assumption that all supported SoCs have
at most one available instance is valid, failing fast otherwise.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The TPM (Timer/PWM Module) is a 2- to 8-channel timer which supports
input capture, output compare, and the generation of PWM signals to
control electric motor and power management applications.
This patch adds the driver and the binding necessary for instantiating
the driver. The work is based on the RV32M1 driver for TPM done by
Henrik Brix Andersen. A later patch will enable this driver to be used
for the KW41Z SoC, if PWM support is requested.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
* Define USB driver for base stm32wb device.
* Enable USB for the nucleo_wb55rg board.
* Properly initialize USB power + clock for the platform.
Signed-off-by: Pete Johanson <peter@peterjohanson.com>
Use the endop bit in the status register (instead of using a k_sleep)
to wait until the current shub operation is completed.
Please note that the recent changes to k_sleep() API was also
breaking the compilation.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Rename DT_HAS_NODE to DT_HAS_NODE_STATUS_OKAY so the semantics are
clear. As going forward DT_HAS_NODE will report if a NODE exists
regardless of its status.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert all canbus related API/samples/tests/subsys
to the new timeout API with k_timeout_t.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
