drivers: i2c: rv32m1: add I2C driver for the RV32M1 RI5CY SoC
Add driver and device tree binding for the Low Power Inter-Integrated Circuit (LPI2C) controllers found in the RV32M1 RI5CY SoC. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit is contained in:
parent
a061443940
commit
8a4dbb5b03
10 changed files with 423 additions and 0 deletions
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@ -140,6 +140,7 @@
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/drivers/usb/ @jfischer-phytec-iot @finikorg
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/drivers/usb/device/usb_dc_stm32.c @ydamigos @loicpoulain
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/drivers/i2c/i2c_ll_stm32* @ldts @ydamigos
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/drivers/i2c/i2c_rv32m1_lpi2c* @henrikbrixandersen
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/drivers/wifi/ @jukkar @tbursztyka @pfalcon
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/drivers/wifi/eswifi/ @loicpoulain
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/dts/arm/st/ @erwango
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@ -20,6 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_I2C_SBCON i2c_sbcon.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_SIFIVE i2c_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_NIOS2 i2c_nios2.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_GECKO i2c_gecko.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_RV32M1_LPI2C i2c_rv32m1_lpi2c.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_STM32_V1
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i2c_ll_stm32_v1.c
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@ -300,4 +300,11 @@ config I2C_NIOS2
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help
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Enable the Nios-II I2C driver.
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config I2C_RV32M1_LPI2C
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bool "RV32M1 LPI2C driver"
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depends on HAS_RV32M1_LPI2C && CLOCK_CONTROL
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select HAS_DTS_I2C
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help
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Enable the RV32M1 LPI2C driver.
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endif # I2C
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313
drivers/i2c/i2c_rv32m1_lpi2c.c
Normal file
313
drivers/i2c/i2c_rv32m1_lpi2c.c
Normal file
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@ -0,0 +1,313 @@
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/*
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* Copyright (c) 2019, Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* Based on the i2c_mcux_lpi2c.c driver, which is:
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* Copyright (c) 2016 Freescale Semiconductor, Inc.
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* Copyright (c) 2019, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <i2c.h>
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#include <clock_control.h>
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#include <fsl_lpi2c.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(rv32m1_lpi2c);
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#include "i2c-priv.h"
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struct rv32m1_lpi2c_config {
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LPI2C_Type *base;
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char *clock_controller;
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clock_control_subsys_t clock_subsys;
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clock_ip_name_t clock_ip_name;
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u32_t clock_ip_src;
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u32_t bitrate;
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void (*irq_config_func)(struct device *dev);
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};
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struct rv32m1_lpi2c_data {
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lpi2c_master_handle_t handle;
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struct k_sem transfer_sync;
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struct k_sem completion_sync;
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status_t completion_status;
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};
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static int rv32m1_lpi2c_configure(struct device *dev, u32_t dev_config)
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{
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const struct rv32m1_lpi2c_config *config = dev->config->config_info;
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struct device *clk;
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u32_t baudrate;
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u32_t clk_freq;
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int err;
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if (!(I2C_MODE_MASTER & dev_config)) {
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/* Slave mode not supported - yet */
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LOG_ERR("Slave mode not supported");
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return -ENOTSUP;
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}
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if (I2C_ADDR_10_BITS & dev_config) {
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/* FSL LPI2C driver only supports 7-bit addressing */
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LOG_ERR("10 bit addressing not supported");
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return -ENOTSUP;
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}
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switch (I2C_SPEED_GET(dev_config)) {
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case I2C_SPEED_STANDARD:
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baudrate = KHZ(100);
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break;
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case I2C_SPEED_FAST:
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baudrate = KHZ(400);
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break;
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case I2C_SPEED_FAST_PLUS:
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baudrate = MHZ(1);
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break;
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/* TODO: only if SCL pin implements current source pull-up */
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/* case I2C_SPEED_HIGH: */
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/* baudrate = KHZ(3400); */
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/* break; */
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/* TODO: ultra-fast requires pin_config setting */
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/* case I2C_SPEED_ULTRA: */
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/* baudrate = MHZ(5); */
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/* break; */
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default:
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LOG_ERR("Unsupported speed");
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return -ENOTSUP;
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}
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clk = device_get_binding(config->clock_controller);
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if (!clk) {
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LOG_ERR("Could not get clock controller '%s'",
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config->clock_controller);
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return -EINVAL;
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}
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err = clock_control_get_rate(clk, config->clock_subsys, &clk_freq);
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if (err) {
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LOG_ERR("Could not get clock frequency (err %d)", err);
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return -EINVAL;
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}
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LPI2C_MasterSetBaudRate(config->base, clk_freq, baudrate);
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return 0;
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}
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static void rv32m1_lpi2c_master_transfer_callback(LPI2C_Type *base,
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lpi2c_master_handle_t *handle,
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status_t completionStatus,
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void *userData)
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{
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struct device *dev = userData;
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struct rv32m1_lpi2c_data *data = dev->driver_data;
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ARG_UNUSED(base);
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ARG_UNUSED(handle);
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data->completion_status = completionStatus;
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k_sem_give(&data->completion_sync);
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}
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static u32_t rv32m1_lpi2c_convert_flags(int msg_flags)
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{
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u32_t flags = 0U;
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if (!(msg_flags & I2C_MSG_STOP)) {
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flags |= kLPI2C_TransferNoStopFlag;
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}
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if (msg_flags & I2C_MSG_RESTART) {
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flags |= kLPI2C_TransferRepeatedStartFlag;
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}
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return flags;
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}
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static int rv32m1_lpi2c_transfer(struct device *dev, struct i2c_msg *msgs,
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u8_t num_msgs, u16_t addr)
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{
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const struct rv32m1_lpi2c_config *config = dev->config->config_info;
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struct rv32m1_lpi2c_data *data = dev->driver_data;
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lpi2c_master_transfer_t transfer;
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status_t status;
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int ret = 0;
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k_sem_take(&data->transfer_sync, K_FOREVER);
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/* Iterate over all the messages */
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for (int i = 0; i < num_msgs; i++) {
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if (I2C_MSG_ADDR_10_BITS & msgs->flags) {
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ret = -ENOTSUP;
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goto out;
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}
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/* Initialize the transfer descriptor */
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transfer.flags = rv32m1_lpi2c_convert_flags(msgs->flags);
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/* Prevent the controller to send a start condition between
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* messages, except if explicitly requested.
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*/
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if (i != 0 && !(msgs->flags & I2C_MSG_RESTART)) {
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transfer.flags |= kLPI2C_TransferNoStartFlag;
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}
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transfer.slaveAddress = addr;
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transfer.direction = (msgs->flags & I2C_MSG_READ)
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? kLPI2C_Read : kLPI2C_Write;
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transfer.subaddress = 0;
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transfer.subaddressSize = 0;
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transfer.data = msgs->buf;
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transfer.dataSize = msgs->len;
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/* Start the transfer */
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status = LPI2C_MasterTransferNonBlocking(config->base,
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&data->handle,
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&transfer);
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/* Return an error if the transfer didn't start successfully
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* e.g., if the bus was busy
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*/
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if (status != kStatus_Success) {
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LOG_DBG("Could not start transfer (status %d)", status);
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ret = -EIO;
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goto out;
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}
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/* Wait for the transfer to complete */
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k_sem_take(&data->completion_sync, K_FOREVER);
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/* Return an error if the transfer didn't complete
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* successfully. e.g., nak, timeout, lost arbitration
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*/
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if (data->completion_status != kStatus_Success) {
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LOG_DBG("Transfer failed (status %d)",
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data->completion_status);
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LPI2C_MasterTransferAbort(config->base, &data->handle);
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ret = -EIO;
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goto out;
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}
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/* Move to the next message */
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msgs++;
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}
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out:
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k_sem_give(&data->transfer_sync);
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return ret;
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}
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static void rv32m1_lpi2c_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct rv32m1_lpi2c_config *config = dev->config->config_info;
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struct rv32m1_lpi2c_data *data = dev->driver_data;
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LPI2C_MasterTransferHandleIRQ(config->base, &data->handle);
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}
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static int rv32m1_lpi2c_init(struct device *dev)
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{
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const struct rv32m1_lpi2c_config *config = dev->config->config_info;
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struct rv32m1_lpi2c_data *data = dev->driver_data;
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lpi2c_master_config_t master_config;
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struct device *clk;
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u32_t clk_freq, dev_cfg;
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int err;
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CLOCK_SetIpSrc(config->clock_ip_name, config->clock_ip_src);
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clk = device_get_binding(config->clock_controller);
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if (!clk) {
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LOG_ERR("Could not get clock controller '%s'",
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config->clock_controller);
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return -EINVAL;
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}
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err = clock_control_on(clk, config->clock_subsys);
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if (err) {
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LOG_ERR("Could not turn on clock (err %d)", err);
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return -EINVAL;
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}
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err = clock_control_get_rate(clk, config->clock_subsys, &clk_freq);
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if (err) {
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LOG_ERR("Could not get clock frequency (err %d)", err);
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return -EINVAL;
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}
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LPI2C_MasterGetDefaultConfig(&master_config);
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LPI2C_MasterInit(config->base, &master_config, clk_freq);
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LPI2C_MasterTransferCreateHandle(config->base, &data->handle,
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rv32m1_lpi2c_master_transfer_callback,
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dev);
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dev_cfg = i2c_map_dt_bitrate(config->bitrate);
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err = rv32m1_lpi2c_configure(dev, dev_cfg | I2C_MODE_MASTER);
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if (err) {
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LOG_ERR("Could not configure controller (err %d)", err);
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return err;
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}
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config->irq_config_func(dev);
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return 0;
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}
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static const struct i2c_driver_api rv32m1_lpi2c_driver_api = {
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.configure = rv32m1_lpi2c_configure,
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.transfer = rv32m1_lpi2c_transfer,
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};
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#define RV32M1_LPI2C_DEVICE(id) \
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static void rv32m1_lpi2c_irq_config_func_##id(struct device *dev); \
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static const struct rv32m1_lpi2c_config rv32m1_lpi2c_##id##_config = { \
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.base = \
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(LPI2C_Type *)DT_OPENISA_RV32M1_LPI2C_I2C_##id##_BASE_ADDRESS, \
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.clock_controller = \
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DT_OPENISA_RV32M1_LPI2C_I2C_##id##_CLOCK_CONTROLLER, \
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.clock_subsys = \
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(clock_control_subsys_t) \
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DT_OPENISA_RV32M1_LPI2C_I2C_##id##_CLOCK_NAME, \
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.clock_ip_name = kCLOCK_Lpi2c##id, \
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.clock_ip_src = kCLOCK_IpSrcFircAsync, \
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.bitrate = DT_OPENISA_RV32M1_LPI2C_I2C_##id##_CLOCK_FREQUENCY, \
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.irq_config_func = rv32m1_lpi2c_irq_config_func_##id, \
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}; \
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static struct rv32m1_lpi2c_data rv32m1_lpi2c_##id##_data = { \
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.transfer_sync = Z_SEM_INITIALIZER( \
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rv32m1_lpi2c_##id##_data.transfer_sync, 1, 1), \
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.completion_sync = Z_SEM_INITIALIZER( \
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rv32m1_lpi2c_##id##_data.completion_sync, 0, 1), \
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}; \
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DEVICE_AND_API_INIT(rv32m1_lpi2c_##id, \
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DT_OPENISA_RV32M1_LPI2C_I2C_##id##_LABEL, \
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&rv32m1_lpi2c_init, \
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&rv32m1_lpi2c_##id##_data, \
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&rv32m1_lpi2c_##id##_config, \
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POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
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&rv32m1_lpi2c_driver_api); \
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static void rv32m1_lpi2c_irq_config_func_##id(struct device *dev) \
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{ \
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IRQ_CONNECT(DT_OPENISA_RV32M1_LPI2C_I2C_##id##_IRQ, \
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DT_OPENISA_RV32M1_LPI2C_I2C_##id##_IRQ_PRI, \
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rv32m1_lpi2c_isr, DEVICE_GET(rv32m1_lpi2c_##id), \
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0); \
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irq_enable(DT_OPENISA_RV32M1_LPI2C_I2C_##id##_IRQ); \
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} \
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#ifdef CONFIG_I2C_0
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RV32M1_LPI2C_DEVICE(0)
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#endif
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#ifdef CONFIG_I2C_1
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RV32M1_LPI2C_DEVICE(1)
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#endif
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#ifdef CONFIG_I2C_2
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RV32M1_LPI2C_DEVICE(2)
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#endif
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#ifdef CONFIG_I2C_3
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RV32M1_LPI2C_DEVICE(3)
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#endif
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30
dts/bindings/i2c/openisa,rv32m1-lpi2c.yaml
Normal file
30
dts/bindings/i2c/openisa,rv32m1-lpi2c.yaml
Normal file
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#
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# Copyright (c) 2019, Henrik Brix Andersen <henrik@brixandersen.dk>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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---
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title: OpenISA LPI2C
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version: 0.1
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description: >
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This binding gives a base representation of the OpenISA LPI2C controller
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inherits:
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!include i2c.yaml
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properties:
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compatible:
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constraint: "openisa,rv32m1-lpi2c"
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reg:
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type: int
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description: mmio register space
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generation: define
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category: required
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interrupts:
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type: compound
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category: required
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description: required interrupts
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generation: define
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@ -5,6 +5,7 @@
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#include <dt-bindings/interrupt-controller/openisa-intmux.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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/ {
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#address-cells = <1>;
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@ -29,6 +30,10 @@
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uart-1 = &uart1;
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uart-2 = &uart2;
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uart-3 = &uart3;
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i2c-0 = &i2c0;
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i2c-1 = &i2c1;
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i2c-2 = &i2c2;
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i2c-3 = &i2c3;
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};
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cpus {
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@ -244,5 +249,57 @@
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label = "UART_3";
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status = "disabled";
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};
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i2c0: lpi2c@4003a000 {
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compatible = "openisa,rv32m1-lpi2c";
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reg = <0x4003a000 0x170>;
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interrupt-parent = <&event>;
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interrupts = <15>;
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clocks = <&pcc0 0xe8>;
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label = "I2C_0";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: lpi2c@4003b000 {
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compatible = "openisa,rv32m1-lpi2c";
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reg = <0x4003b000 0x170>;
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interrupt-parent = <&event>;
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interrupts = <16>;
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clocks = <&pcc0 0xec>;
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label = "I2C_1";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: lpi2c@4003c000 {
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compatible = "openisa,rv32m1-lpi2c";
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reg = <0x4003c000 0x170>;
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interrupt-parent = <&intmux>;
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interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 11)>;
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clocks = <&pcc0 0xf0>;
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label = "I2C_2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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|
||||
i2c3: lpi2c@4102e000 {
|
||||
compatible = "openisa,rv32m1-lpi2c";
|
||||
reg = <0x4102e000 0x170>;
|
||||
interrupt-parent = <&intmux>;
|
||||
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 24)>;
|
||||
clocks = <&pcc1 0xb8>;
|
||||
label = "I2C_3";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -10,3 +10,8 @@ config HAS_RV32M1_LPUART
|
|||
bool
|
||||
help
|
||||
Set if the low power uart (LPUART) module is present in the SoC.
|
||||
|
||||
config HAS_RV32M1_LPI2C
|
||||
bool
|
||||
help
|
||||
Set if the low power i2c (LPI2C) module is present in the SoC.
|
||||
|
|
|
@ -2,3 +2,4 @@ zephyr_include_directories(.)
|
|||
|
||||
zephyr_sources(fsl_clock.c)
|
||||
zephyr_sources_ifdef(CONFIG_UART_RV32M1_LPUART fsl_lpuart.c)
|
||||
zephyr_sources_ifdef(CONFIG_I2C_RV32M1_LPI2C fsl_lpi2c.c)
|
||||
|
|
|
@ -185,4 +185,11 @@ config UART_RV32M1_LPUART
|
|||
|
||||
endif # SERIAL
|
||||
|
||||
if I2C
|
||||
|
||||
config I2C_RV32M1_LPI2C
|
||||
def_bool y
|
||||
|
||||
endif # I2C
|
||||
|
||||
endif # SOC_OPENISA_RV32M1_RISCV32
|
||||
|
|
|
@ -12,6 +12,7 @@ config SOC_OPENISA_RV32M1_RISCV32
|
|||
# (We can't make it a 'depends on' without causing a dependency loop).
|
||||
select XIP
|
||||
select HAS_RV32M1_LPUART
|
||||
select HAS_RV32M1_LPI2C
|
||||
select ATOMIC_OPERATIONS_C
|
||||
select VEGA_SDK_HAL
|
||||
select RISCV_SOC_INTERRUPT_INIT
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue