drivers: ethernet: phy: add common functions for PHYs
This commit adds common functions for PHYs to the mii driver. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This commit is contained in:
parent
62b5785d7a
commit
847be49dbd
7 changed files with 110 additions and 289 deletions
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@ -23,6 +23,8 @@
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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#include "phy_mii.h"
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#define PHY_MC_KSZ8081_OMSO_REG 0x16
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#define PHY_MC_KSZ8081_OMSO_FACTORY_MODE_MASK BIT(15)
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#define PHY_MC_KSZ8081_OMSO_NAND_TREE_MASK BIT(5)
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@ -339,7 +341,6 @@ static int phy_mc_ksz8081_cfg_link(const struct device *dev,
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struct mc_ksz8081_data *data = dev->data;
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struct phy_link_state state = {};
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int ret;
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uint32_t anar;
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/* Lock mutex */
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ret = k_mutex_lock(&data->mutex, K_FOREVER);
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@ -357,39 +358,9 @@ static int phy_mc_ksz8081_cfg_link(const struct device *dev,
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goto done;
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}
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/* Read ANAR register to write back */
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ret = phy_mc_ksz8081_read(dev, MII_ANAR, &anar);
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if (ret) {
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LOG_ERR("Error reading phy (%d) advertising register", config->addr);
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goto done;
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}
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/* Setup advertising register */
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if (speeds & LINK_FULL_100BASE) {
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anar |= MII_ADVERTISE_100_FULL;
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} else {
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anar &= ~MII_ADVERTISE_100_FULL;
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}
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if (speeds & LINK_HALF_100BASE) {
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anar |= MII_ADVERTISE_100_HALF;
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} else {
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anar &= ~MII_ADVERTISE_100_HALF;
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}
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if (speeds & LINK_FULL_10BASE) {
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anar |= MII_ADVERTISE_10_FULL;
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} else {
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anar &= ~MII_ADVERTISE_10_FULL;
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}
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if (speeds & LINK_HALF_10BASE) {
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anar |= MII_ADVERTISE_10_HALF;
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} else {
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anar &= ~MII_ADVERTISE_10_HALF;
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}
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/* Write capabilities to advertising register */
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ret = phy_mc_ksz8081_write(dev, MII_ANAR, anar);
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if (ret) {
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LOG_ERR("Error writing phy (%d) advertising register", config->addr);
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ret = phy_mii_set_anar_reg(dev, speeds);
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if ((ret < 0) && (ret != -EALREADY)) {
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LOG_ERR("Error setting ANAR register for phy (%d)", config->addr);
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goto done;
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}
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@ -18,6 +18,8 @@
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(phy_mii, CONFIG_PHY_LOG_LEVEL);
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#include "phy_mii.h"
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#define ANY_DYNAMIC_LINK UTIL_NOT(DT_ALL_INST_HAS_PROP_STATUS_OKAY(fixed_link))
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#define ANY_FIXED_LINK DT_ANY_INST_HAS_PROP_STATUS_OKAY(fixed_link)
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@ -350,11 +352,7 @@ static int phy_mii_cfg_link(const struct device *dev,
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{
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struct phy_mii_dev_data *const data = dev->data;
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const struct phy_mii_dev_config *const cfg = dev->config;
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uint16_t anar_reg;
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uint16_t anar_reg_old;
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uint16_t bmcr_reg;
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uint16_t c1kt_reg;
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uint16_t c1kt_reg_old;
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int ret = 0;
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/* if there is no mdio (fixed-link) it is not supported to configure link */
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@ -368,79 +366,30 @@ static int phy_mii_cfg_link(const struct device *dev,
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k_sem_take(&data->sem, K_FOREVER);
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if (phy_mii_reg_read(dev, MII_ANAR, &anar_reg) < 0) {
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ret = -EIO;
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goto cfg_link_end;
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}
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anar_reg_old = anar_reg;
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if (phy_mii_reg_read(dev, MII_BMCR, &bmcr_reg) < 0) {
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ret = -EIO;
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goto cfg_link_end;
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}
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if (data->gigabit_supported) {
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if (phy_mii_reg_read(dev, MII_1KTCR, &c1kt_reg) < 0) {
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ret = -EIO;
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ret = phy_mii_set_c1kt_reg(dev, adv_speeds);
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if (ret == -EALREADY) {
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/* If the C1KT register is already set, we don't need to do anything */
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ret = 0;
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} else if (ret < 0) {
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goto cfg_link_end;
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}
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}
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if (adv_speeds & LINK_FULL_10BASE) {
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anar_reg |= MII_ADVERTISE_10_FULL;
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} else {
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anar_reg &= ~MII_ADVERTISE_10_FULL;
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}
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if (adv_speeds & LINK_HALF_10BASE) {
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anar_reg |= MII_ADVERTISE_10_HALF;
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} else {
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anar_reg &= ~MII_ADVERTISE_10_HALF;
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}
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if (adv_speeds & LINK_FULL_100BASE) {
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anar_reg |= MII_ADVERTISE_100_FULL;
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} else {
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anar_reg &= ~MII_ADVERTISE_100_FULL;
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}
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if (adv_speeds & LINK_HALF_100BASE) {
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anar_reg |= MII_ADVERTISE_100_HALF;
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} else {
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anar_reg &= ~MII_ADVERTISE_100_HALF;
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}
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if (data->gigabit_supported) {
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c1kt_reg_old = c1kt_reg;
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if (adv_speeds & LINK_FULL_1000BASE) {
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c1kt_reg |= MII_ADVERTISE_1000_FULL;
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} else {
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c1kt_reg &= ~MII_ADVERTISE_1000_FULL;
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}
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if (adv_speeds & LINK_HALF_1000BASE) {
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c1kt_reg |= MII_ADVERTISE_1000_HALF;
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} else {
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c1kt_reg &= ~MII_ADVERTISE_1000_HALF;
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}
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if (c1kt_reg != c1kt_reg_old) {
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if (phy_mii_reg_write(dev, MII_1KTCR, c1kt_reg) < 0) {
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ret = -EIO;
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goto cfg_link_end;
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}
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data->restart_autoneg = true;
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}
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}
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if (anar_reg != anar_reg_old) {
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if (phy_mii_reg_write(dev, MII_ANAR, anar_reg) < 0) {
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ret = -EIO;
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goto cfg_link_end;
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}
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ret = phy_mii_set_anar_reg(dev, adv_speeds);
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if (ret == -EALREADY) {
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/* If the ANAR register is already set, we don't need to do anything */
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ret = 0;
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} else if (ret < 0) {
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goto cfg_link_end;
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} else {
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data->restart_autoneg = true;
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}
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63
drivers/ethernet/phy/phy_mii.h
Normal file
63
drivers/ethernet/phy/phy_mii.h
Normal file
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@ -0,0 +1,63 @@
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/*
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* Copyright The Zephyr Project Contributors
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_PHY_MII_H_
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#define ZEPHYR_PHY_MII_H_
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#include <zephyr/device.h>
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#include <zephyr/net/phy.h>
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#include <zephyr/net/mii.h>
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static inline int phy_mii_set_anar_reg(const struct device *dev, enum phy_link_speed adv_speeds)
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{
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uint32_t anar_reg = 0U;
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uint32_t anar_reg_old;
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if (phy_read(dev, MII_ANAR, &anar_reg) < 0) {
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return -EIO;
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}
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anar_reg_old = anar_reg;
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WRITE_BIT(anar_reg, MII_ADVERTISE_10_FULL_BIT, (adv_speeds & LINK_FULL_10BASE) != 0U);
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WRITE_BIT(anar_reg, MII_ADVERTISE_10_HALF_BIT, (adv_speeds & LINK_HALF_10BASE) != 0U);
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WRITE_BIT(anar_reg, MII_ADVERTISE_100_FULL_BIT, (adv_speeds & LINK_FULL_100BASE) != 0U);
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WRITE_BIT(anar_reg, MII_ADVERTISE_100_HALF_BIT, (adv_speeds & LINK_HALF_100BASE) != 0U);
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if (anar_reg == anar_reg_old) {
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return -EALREADY;
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}
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if (phy_write(dev, MII_ANAR, anar_reg) < 0) {
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return -EIO;
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}
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return 0;
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}
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static inline int phy_mii_set_c1kt_reg(const struct device *dev, enum phy_link_speed adv_speeds)
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{
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uint32_t c1kt_reg = 0U;
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uint32_t c1kt_reg_old;
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if (phy_read(dev, MII_1KTCR, &c1kt_reg) < 0) {
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return -EIO;
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}
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c1kt_reg_old = c1kt_reg;
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WRITE_BIT(c1kt_reg, MII_ADVERTISE_1000_FULL_BIT, (adv_speeds & LINK_FULL_1000BASE) != 0U);
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WRITE_BIT(c1kt_reg, MII_ADVERTISE_1000_HALF_BIT, (adv_speeds & LINK_HALF_1000BASE) != 0U);
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if (c1kt_reg == c1kt_reg_old) {
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return -EALREADY;
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}
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if (phy_write(dev, MII_1KTCR, c1kt_reg) < 0) {
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return -EIO;
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}
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return 0;
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}
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#endif /* ZEPHYR_PHY_MII_H_ */
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@ -22,6 +22,8 @@
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(phy_qc_ar8031, CONFIG_PHY_LOG_LEVEL);
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#include "phy_mii.h"
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#define AR8031_PHY_ID1 0x004DU
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#define PHY_READID_TIMEOUT_COUNT 1000U
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static int qc_ar8031_cfg_link(const struct device *dev, enum phy_link_speed adv_speeds)
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{
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uint32_t anar_reg;
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uint32_t bmcr_reg;
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uint32_t c1kt_reg;
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if (qc_ar8031_read(dev, MII_ANAR, &anar_reg) < 0) {
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return -EIO;
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}
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if (qc_ar8031_read(dev, MII_BMCR, &bmcr_reg) < 0) {
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return -EIO;
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}
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if (qc_ar8031_read(dev, MII_1KTCR, &c1kt_reg) < 0) {
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ret = phy_mii_set_anar_reg(dev, speeds);
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if ((ret < 0) && (ret != -EALREADY)) {
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return -EIO;
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}
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if (adv_speeds & LINK_FULL_10BASE) {
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anar_reg |= MII_ADVERTISE_10_FULL;
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} else {
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anar_reg &= ~MII_ADVERTISE_10_FULL;
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}
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if (adv_speeds & LINK_HALF_10BASE) {
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anar_reg |= MII_ADVERTISE_10_HALF;
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} else {
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anar_reg &= ~MII_ADVERTISE_10_HALF;
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}
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if (adv_speeds & LINK_FULL_100BASE) {
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anar_reg |= MII_ADVERTISE_100_FULL;
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} else {
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anar_reg &= ~MII_ADVERTISE_100_FULL;
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}
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if (adv_speeds & LINK_HALF_100BASE) {
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anar_reg |= MII_ADVERTISE_100_HALF;
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} else {
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anar_reg &= ~MII_ADVERTISE_100_HALF;
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}
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if (adv_speeds & LINK_FULL_1000BASE) {
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c1kt_reg |= MII_ADVERTISE_1000_FULL;
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} else {
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c1kt_reg &= ~MII_ADVERTISE_1000_FULL;
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}
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if (adv_speeds & LINK_HALF_1000BASE) {
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c1kt_reg |= MII_ADVERTISE_1000_HALF;
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} else {
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c1kt_reg &= ~MII_ADVERTISE_1000_HALF;
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}
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if (qc_ar8031_write(dev, MII_1KTCR, c1kt_reg) < 0) {
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ret = phy_mii_set_c1kt_reg(dev, speeds);
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if ((ret < 0) && (ret != -EALREADY)) {
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return -EIO;
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}
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bmcr_reg |= MII_BMCR_AUTONEG_ENABLE | MII_BMCR_AUTONEG_RESTART;
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if (qc_ar8031_write(dev, MII_ANAR, anar_reg) < 0) {
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return -EIO;
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}
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if (qc_ar8031_write(dev, MII_BMCR, bmcr_reg) < 0) {
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return -EIO;
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}
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@ -25,6 +25,8 @@
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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#include "phy_mii.h"
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#define REALTEK_OUI_MSB (0x1CU)
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#define PHY_RT_RTL8211F_PHYSR_REG (0x1A)
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@ -283,8 +285,6 @@ static int phy_rt_rtl8211f_cfg_link(const struct device *dev,
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{
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const struct rt_rtl8211f_config *config = dev->config;
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struct rt_rtl8211f_data *data = dev->data;
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uint32_t anar;
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uint32_t gbcr;
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int ret;
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/* Lock mutex */
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@ -303,60 +303,15 @@ static int phy_rt_rtl8211f_cfg_link(const struct device *dev,
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k_work_cancel_delayable(&data->phy_monitor_work);
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#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) */
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/* Read ANAR register to write back */
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ret = phy_rt_rtl8211f_read(dev, MII_ANAR, &anar);
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if (ret) {
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LOG_ERR("Error reading phy (%d) advertising register", config->addr);
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ret = phy_mii_set_anar_reg(dev, speeds);
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if (ret < 0 && ret != -EALREADY) {
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LOG_ERR("Error setting ANAR register for phy (%d)", config->addr);
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goto done;
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}
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/* Read GBCR register to write back */
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ret = phy_rt_rtl8211f_read(dev, MII_1KTCR, &gbcr);
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if (ret) {
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LOG_ERR("Error reading phy (%d) 1000Base-T control register", config->addr);
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goto done;
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}
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/* Setup advertising register */
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if (speeds & LINK_FULL_100BASE) {
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anar |= MII_ADVERTISE_100_FULL;
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} else {
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anar &= ~MII_ADVERTISE_100_FULL;
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}
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if (speeds & LINK_HALF_100BASE) {
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anar |= MII_ADVERTISE_100_HALF;
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} else {
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anar &= ~MII_ADVERTISE_100_HALF;
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}
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if (speeds & LINK_FULL_10BASE) {
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anar |= MII_ADVERTISE_10_FULL;
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} else {
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anar &= ~MII_ADVERTISE_10_FULL;
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}
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if (speeds & LINK_HALF_10BASE) {
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anar |= MII_ADVERTISE_10_HALF;
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} else {
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anar &= ~MII_ADVERTISE_10_HALF;
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}
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/* Setup 1000Base-T control register */
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if (speeds & LINK_FULL_1000BASE) {
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gbcr |= MII_ADVERTISE_1000_FULL;
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} else {
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gbcr &= ~MII_ADVERTISE_1000_FULL;
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}
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/* Write capabilities to advertising register */
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ret = phy_rt_rtl8211f_write(dev, MII_ANAR, anar);
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if (ret) {
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LOG_ERR("Error writing phy (%d) advertising register", config->addr);
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goto done;
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}
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/* Write capabilities to 1000Base-T control register */
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ret = phy_rt_rtl8211f_write(dev, MII_1KTCR, gbcr);
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if (ret) {
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LOG_ERR("Error writing phy (%d) 1000Base-T control register", config->addr);
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ret = phy_mii_set_c1kt_reg(dev, speeds);
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if (ret < 0 && ret != -EALREADY) {
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LOG_ERR("Error setting C1KT register for phy (%d)", config->addr);
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goto done;
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}
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@ -22,6 +22,8 @@
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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#include "phy_mii.h"
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#define PHY_TI_DP83825_PHYSCR_REG 0x11
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#define PHY_TI_DP83825_PHYSCR_REG_IE BIT(1)
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#define PHY_TI_DP83825_PHYSCR_REG_IOE BIT(0)
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@ -363,7 +365,6 @@ static int phy_ti_dp83825_cfg_link(const struct device *dev, enum phy_link_speed
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const struct ti_dp83825_config *config = dev->config;
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struct ti_dp83825_data *data = dev->data;
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int ret;
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uint32_t anar;
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/* Lock mutex */
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ret = k_mutex_lock(&data->mutex, K_FOREVER);
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@ -393,42 +394,9 @@ static int phy_ti_dp83825_cfg_link(const struct device *dev, enum phy_link_speed
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goto done;
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}
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|
||||
/* Read ANAR register to write back */
|
||||
ret = phy_ti_dp83825_read(dev, MII_ANAR, &anar);
|
||||
if (ret) {
|
||||
LOG_ERR("Error reading phy (%d) advertising register", config->addr);
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* Setup advertising register */
|
||||
if (speeds & LINK_FULL_100BASE) {
|
||||
anar |= MII_ADVERTISE_100_FULL;
|
||||
} else {
|
||||
anar &= ~MII_ADVERTISE_100_FULL;
|
||||
}
|
||||
|
||||
if (speeds & LINK_HALF_100BASE) {
|
||||
anar |= MII_ADVERTISE_100_HALF;
|
||||
} else {
|
||||
anar &= ~MII_ADVERTISE_100_HALF;
|
||||
}
|
||||
|
||||
if (speeds & LINK_FULL_10BASE) {
|
||||
anar |= MII_ADVERTISE_10_FULL;
|
||||
} else {
|
||||
anar &= ~MII_ADVERTISE_10_FULL;
|
||||
}
|
||||
|
||||
if (speeds & LINK_HALF_10BASE) {
|
||||
anar |= MII_ADVERTISE_10_HALF;
|
||||
} else {
|
||||
anar &= ~MII_ADVERTISE_10_HALF;
|
||||
}
|
||||
|
||||
/* Write capabilities to advertising register */
|
||||
ret = phy_ti_dp83825_write(dev, MII_ANAR, anar);
|
||||
if (ret) {
|
||||
LOG_ERR("Error writing phy (%d) advertising register", config->addr);
|
||||
ret = phy_mii_set_anar_reg(dev, speeds);
|
||||
if ((ret < 0) && (ret != -EALREADY)) {
|
||||
LOG_ERR("Error setting ANAR register for phy (%d)", config->addr);
|
||||
goto done;
|
||||
}
|
||||
|
||||
|
|
|
@ -20,6 +20,8 @@
|
|||
#include <zephyr/logging/log.h>
|
||||
LOG_MODULE_REGISTER(LOG_MODULE_NAME, LOG_LEVEL);
|
||||
|
||||
#include "phy_mii.h"
|
||||
|
||||
#define PHY_TI_DP83867_PHYSTS 0x11
|
||||
#define PHY_TI_DP83867_PHYSTS_LINKSTATUS_MASK BIT(10)
|
||||
#define PHY_TI_DP83867_PHYSTS_LINKDUPLEX_MASK BIT(13)
|
||||
|
@ -309,7 +311,7 @@ static int phy_ti_dp83867_cfg_link(const struct device *dev, enum phy_link_speed
|
|||
const struct ti_dp83867_config *config = dev->config;
|
||||
struct ti_dp83867_data *data = dev->data;
|
||||
int ret;
|
||||
uint32_t anar, cfg1, val;
|
||||
uint32_t val;
|
||||
|
||||
/* Lock mutex */
|
||||
ret = k_mutex_lock(&data->mutex, K_FOREVER);
|
||||
|
@ -356,60 +358,15 @@ static int phy_ti_dp83867_cfg_link(const struct device *dev, enum phy_link_speed
|
|||
k_work_cancel_delayable(&data->phy_monitor_work);
|
||||
#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) */
|
||||
|
||||
/* Read ANAR register to write back */
|
||||
ret = phy_ti_dp83867_read(dev, MII_ANAR, &anar);
|
||||
if (ret) {
|
||||
LOG_ERR("Error reading phy (%d) advertising register", config->addr);
|
||||
ret = phy_mii_set_anar_reg(dev, speeds);
|
||||
if ((ret < 0) && (ret != -EALREADY)) {
|
||||
LOG_ERR("Error setting ANAR register for phy (%d)", config->addr);
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* Read CFG1 register to write back */
|
||||
ret = phy_ti_dp83867_read(dev, MII_1KTCR, &cfg1);
|
||||
if (ret) {
|
||||
LOG_ERR("Error reading phy (%d) 1000Base-T control register", config->addr);
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* Setup advertising register */
|
||||
if (speeds & LINK_FULL_100BASE) {
|
||||
anar |= MII_ADVERTISE_100_FULL;
|
||||
} else {
|
||||
anar &= ~MII_ADVERTISE_100_FULL;
|
||||
}
|
||||
if (speeds & LINK_HALF_100BASE) {
|
||||
anar |= MII_ADVERTISE_100_HALF;
|
||||
} else {
|
||||
anar &= ~MII_ADVERTISE_100_HALF;
|
||||
}
|
||||
if (speeds & LINK_FULL_10BASE) {
|
||||
anar |= MII_ADVERTISE_10_FULL;
|
||||
} else {
|
||||
anar &= ~MII_ADVERTISE_10_FULL;
|
||||
}
|
||||
if (speeds & LINK_HALF_10BASE) {
|
||||
anar |= MII_ADVERTISE_10_HALF;
|
||||
} else {
|
||||
anar &= ~MII_ADVERTISE_10_HALF;
|
||||
}
|
||||
|
||||
/* Setup 1000Base-T control register */
|
||||
if (speeds & LINK_FULL_1000BASE) {
|
||||
cfg1 |= MII_ADVERTISE_1000_FULL;
|
||||
} else {
|
||||
cfg1 &= ~MII_ADVERTISE_1000_FULL;
|
||||
}
|
||||
|
||||
/* Write capabilities to advertising register */
|
||||
ret = phy_ti_dp83867_write(dev, MII_ANAR, anar);
|
||||
if (ret) {
|
||||
LOG_ERR("Error writing phy (%d) advertising register", config->addr);
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* Write capabilities to 1000Base-T control register */
|
||||
ret = phy_ti_dp83867_write(dev, MII_1KTCR, cfg1);
|
||||
if (ret) {
|
||||
LOG_ERR("Error writing phy (%d) 1000Base-T control register", config->addr);
|
||||
ret = phy_mii_set_c1kt_reg(dev, speeds);
|
||||
if ((ret < 0) && (ret != -EALREADY)) {
|
||||
LOG_ERR("Error setting C1KT register for phy (%d)", config->addr);
|
||||
goto done;
|
||||
}
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue