Create clock_stm32_ll_mco.h file to bring stm32_clock_control_mco_init,
mco1_prescaler, mco2_prescaler, MCO1_SOURCE and MCO2_SOURCE definitions
which were previously in clock_stm32_ll_common.{c,h}. This is done so that
stm32_clock_control_mco_init can be called from clock_stm32_ll_h7.c.
Also update Kconfig.stm32 and add new MCO sources to allow H7 support.
Signed-off-by: Johan Lafon <johan.lafon@syslinbit.com>
To demonstrate how to configure Zephyr to use the IPM
driver over the IVSHMEM subsystem. Since this driver
is intended to generate inter QEMU VM notifications
it was better to create a sample app using the shell
for quick demonstration for the users.
Signed-off-by: Felipe Neves <felipe.neves@linaro.org>
This driver is built on top of the IVSHMEM doorbell
notification mechanism providing an unified way
to generate inter VM interrupts.
Signed-off-by: Felipe Neves <felipe.neves@linaro.org>
If a timer is left running on an stm32mp1, (most likely) on the next run
the timer is stuck.
A simple timer reset before initialization fixes the issue.
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
When ENET_ENHANCEDBUFFERDESCRIPTOR_MODE enabled,
MAC will automatic capture receive nanosecond from 1588TMR
and return back to ENET_ReadFrame. It is a highest accuracy
recv timestamp_ns, we do not need manually read from 1588TMR.
By this change, receive timestamp accuracy increase
from 20us to 200ns above.
Signed-off-by: Chen Caidy <chen@caidy.cc>
The Broadcom pcie setup has a devicetree dependency like:
/pcie/paxdma -> /pcie/pcie -> /soc/pl330
Add a separate init symbol for iproc_pax_v2 so that these gets
initialized in order, fixes this error:
$ west build -p -b bcm958402m2_m7 tests/kernel/common \
-DCONFIG_CHECK_INIT_PRIORITIES=y
...
ERROR: /pcie/paxdma@4e100800 POST_KERNEL 40 < \
/pcie/pcie@4e100000 POST_KERNEL 50
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Set a dedicated priority for the video_mcux_csi instead of using the
default kernel device init priority. This allows initializing the device
in a sequence that matches the devicetree hirearchy compared to mt9m114.
Fixes the error:
ERROR: /soc/csi@402bc000 POST_KERNEL 50 <
/soc/i2c@403f0000/mt9m114@48 POST_KERNEL 60
found using:
$ west build -p -b mimxrt1064_evk samples/subsys/video/capture \
-DCONFIG_CHECK_INIT_PRIORITIES=y
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix for bug:
https://github.com/zephyrproject-rtos/zephyr/issues/59802
The DMA controller only supports one transfer size, but
the Zephyr DMA driver api allows specifying a source_data_size
and dest_data_size which might be different. An old
version was always using dest_data_size for the transfer
size (variable is called "width"), but a recent change
made the driver use the MIN for the source and dest data
sizes. The MIN choice breaks the I2S driver because it
always set source_data_size to 1, but dest_data_size was
typically 4 for like two-channel 16-bit PCM data. So the
old driver worked using dest_data_size, but the new driver
broke I2S using MIN since source_data_size was 1.
To prevent confusion, change the DMA driver to assert that
source_data_size and dest_data_size are the same.
Also assert that the source_address and dest_address for
each block_config are properly aligned for the transfer size,
since that is a documentated requirement for the DMA controller.
Also rename max_xfer to max_xfer-bytes to be more clear what
the units are, and use this value in many places that
are comparing block_size in bytes rather than converting
block_size to words by dividing by width and
then comparing to NXP_LPC_DMA_MAX_XFER.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The MCUX DMA controller only supports a single data_size
for a DMA transfer, not separate ones for source and
dest. An older version of the DMA driver used
dest_data_size as the DMA transfer size, but the
current one uses MIN(dest/source) as the trasnfer
size, which breaks case when SPI wants to do 2-byte
transfers.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Fix for bugs described in:
https://github.com/zephyrproject-rtos/zephyr/issues/59803
1. the size argument passed to i2s_write() was being ignored.
change the code so that the size is queued with the
tx mem_block and the dma transfer is configured with this
size.
2. change how CONFIG_I2S_MCUX_FLEXCOMM_RX_BLOCK_COUNT and
CONFIG_I2S_MCUX_FLEXCOMM_TX_BLOCK_COUNT are used so that
the queue buffers are allocated correctly when the two
config values are not the same
3. set source_data_size and dest_data_size to be the same
since the DMA controller can only set one size per
DMA transfer. the driver was already computing a dest_data_size
but always passing 1 for the source_data_size.
For I2S RX case, I think source_data_size should be
set to the expected FIFO read size instead of dest_data_size.
Also some smaller improvements like:
* don't allocate two dma_blocks for tx in the static dev_mem
when it only needs one
* memset both rx_dma_blocks together instead of separtely
* set dma_cfg block_count for tx and rx statically instead
of at runtime
Signed-off-by: Mike J. Chen <mjchen@google.com>
Depending on the ADC implementation it might happen that
the driver is waiting on an external interrupt. If this interrupt
gets lost, for instance due to a race condition with an external
port expander, the system will get stuck.
Making this configurable allows the user to recover from such
an error.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
A recent factorisation moved F2 to non const TIM_TypeDef.
This is an error, move it back to const TIM_TypeDef.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Fixes a bug in intel_adsp_gpdma_release_ownership(). Before fix, this
function actually did nothing for ACE platform and the ownership was
not released. Now ownership is released to host CPU + DSP.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
This PR is Calling "clock_control_on" and checking return value
(as is done elsewhere 10 out of 11 times)
CID 322066: Error handling issues (CHECKED_RETURN)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
AXP192 is a small and simple power management IC featuring different
LDOs, DCDCs, AINs and also GPIOs. It also offers functionaltiy for
battery management.
This change includes the basic regulator driver functionaltiy for
LDO2-3 and DCDC1-3 as well as the mfd driver layer. Further drivers
for GPIO and ADC will follow.
Drivers have been developed and tested on M5StackCore2, an ESP32-based
board. Support for M5StackCore2 is still in progress.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
Add few missing check on gpio_add_callback and gpio_add_callback_dt
calls, fixes a coverity warning.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
GT911 IC uses the INT pin to select the correct I2C address during
reset. However, some boards may not route this pin (or may only support
receiving inputs on it). This results in the I2C address selected by the
GT911 IC being arbitrary based on the state of the (floating) INT pin.
To resolve this, introduce an `alt-addr` property for this device. When
set, the INT pin will not be pulled low. Instead, the I2C address will be
probed at runtime, starting with the devicetree address and falling back to
`alt-addr`.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
New reset function which performs a full power reset
New hibernate function which powers down and wakes after
specified timeout
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
The `spi_mcux_transceive` had 2 return calls when the
`CONFIG_SPI_MCUX_LPSPI_DMA` flag was active. The first return would be
called and the later was unreachable. With the fix, now the return calls
are mutually exclusive. Also, the `transceive` call is not compiled with
the `CONFIG_SPI_MCUX_LPSPI_DMA` flag is active.
Fixes#59533
Signed-off-by: Dipak Shetty <dipak.shetty@zeiss.com>
Only 12-bit resolution is currently available in the driver,
and each of the 16-bit samples store the actual data
aligned to the left.
A sample should be shifted 4 bits to the right to allow
proper interpretation.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
With the phy-clock being specified in devicetree (and thus under user
control), there is no need to artificially enlarge the DPHY clock to
insure it is fast enough. Instead, we can calculate the DPHY clock
directly, selecting the closest realizable value that is at least as
fast as the value requested by the user.
Fixes#59215
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Both the IRQ API and Asynchronous API support callback.
However, since they are both interrupt driven, having
callbacks on both API would interfere with each other
in almost all cases. So this adds a kconfig to signal
that the callbacks should be exclusive to each other.
In other words, if one is set, the other should not
be active. Drivers implementing both APIs have been
updated to remove the callbacks from the other API.
Though, this still leaves the option to disable
the kconfig and allows both APIs to have callbacks
if one desires.
Fixes#48606
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add support of the dedicated STM32F0 14 MHz HSI clock for ADC.
Also remove ADC clock source selection as it is obsolete.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
When CONFIG_PM_DEVICE is enabled, the FDC2x1x driver includes code that
doesn't access the name of the shutdown pin's GPIO port correctly.
Correct this so the code derefences the right struct members.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
The FDC2X1X driver depends on newlib in Kconfig. This prevents the
driver from being built in a native_posix testing environment, which uses
an external libc from the host. Allow the driver to be built with an
external libc as well.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
STM32 RTC driver for the new RTC API.
Can't coexist with old COUNTER based RTC
Though supported by HW, RTC_ALARM still to be supported by driver
Signed-off-by: Kim Bøndergaard <kim.bondergaard@prevas.dk>
New RTC API seems to conflict with old RTC implementations based on
COUNTER
This scheme follows Zephyrproject-rtos issue 56599 while keeping backward
compatibility.
Signed-off-by: Kim Bøndergaard <kim.bondergaard@prevas.dk>
The SSP driver depends on DMA as there are references in the devicetree,
but it currently initialize before the DMA driver itself. This is
exposed by the build time priority checking
(CONFIG_CHECK_INIT_PRIORITIES=y) and shows up as:
ERROR: /soc/ssp@77a00 POST_KERNEL 32 < /soc/dma@7c000 POST_KERNEL 40
ERROR: /soc/ssp@77800 POST_KERNEL 32 < /soc/dma@7c000 POST_KERNEL 40
ERROR: /soc/ssp@77600 POST_KERNEL 32 < /soc/dma@7c000 POST_KERNEL 40
...
Bumping up the SSP priority so the initialization is in sync with the
devicetree node hirearchy.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The set_brightness function of the led_pwm driver uses a default PWM
period (defined in the pwms DT property) to compute a pulse passed to
the pwm_set_pulse_dt function. If this default period is greater than
2^32/100 nanoseconds (about 43 milliseconds) then the calculation may
overflow.
This patch prevents this overflow by running the pulse computation under
a cast with a larger type (uint64_t).
Reported-by: Scott Worley <scott.worley@microchip.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Add a Kconfig to have the ability to fine tune the amount of RAM that
the driver uses based on the number of channels expected to be used.
Most of the code is already there but just need this Kconfig to get the
benefit of it by reducing the size of the statically created arrays.
Also change the number of channels field in the configuration to a byte
instead of a 32 bit integer because that should be sufficient to
describe the number of DMA channels.
Rename LPC DMA Driver Kconfigs with namespace to MCUX_LPC
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Setting higher priority to reset controller to initialize it before
other dependent drivers running at CONFIG_KERNEL_INIT_PRIORITY_DEFAULT
priority which is 40.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
The rv32m1 pinctrl driver depends on clock controller, add a new symbol
and set it so it gets initialized after that, and before other devices.
Fixes:
$ west build -p -b rv32m1_vega_ri5cy tests/kernel/common \
-DCONFIG_CHECK_INIT_PRIORITIES=y
...
ERROR: /soc/pinmux@41037000 PRE_KERNEL_1 1 < \
/soc/clock-controller@41027000 PRE_KERNEL_1 30
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The Kconfig IEEE802154_NRF5_MULTIPLE_CCA option is added.
The new functions `z_ieee802154_nrf5_extra_cca_attempts_set` and
`z_ieee802154_nrf5_extra_cca_attempts_get` are added.
The ieee802154_nrf5.c is updated allowing to pass extra cca attempts
to nRF 802.15.4 Radio Driver.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
