Soft resetting a STM32 device currently does not reset the USB
connection, which causes a few problems: The endpoints do not respond
anymore, and within zephyr any kind of status information like
CDC_SET_CONTROL_LINE_STATE is also missing as they are not
re-negotiated.
This is fixed by stopping the USB device from zephyr side, right after
initialising the USB device.
Signed-off-by: David Jablonski <dayjaby@gmail.com>
This commit fixes an issue introduced in 5ee9392 where FlexSPI
pinctrl states where applied based on the SoC type.
However multiple FlexSPI instances can be active, some of which
are not pre-configured from ROM.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The HAS_I2C_DW was to limit Kconfig visibility to only platforms
that utilize the I2C DW IP. The Kconfig for I2C_DW depends on
DT_HAS_SNPS_DESIGNWARE_I2C_ENABLED which will cause the same
visbility limitation to only platforms that have I2C DW devicetree
nodes. Thus we can remove HAS_I2C_DW and its references.
Signed-off-by: Kumar Gala <galak@kernel.org>
This adds a driver for Maxims DS2484 Single-Channel 1-Wire master
driver. The DS2484 features an extra pin to enable sleep modes which
is available if the pin is configured in the device tree.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
Add ESP32 TWAI CAN controller driver. The TWAI is register-compatible with
the NXP SJA1000 CAN controller.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Update flash drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <galak@kernel.org>
MSIS frequency at boot time can be different from the one we intent to
set from device tree configuration.
In order to avoid issues, read MSIS configuration from registers to get
the actual freq rather than the devicetree one which may be not yet
configured (which is the case at startup).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When configuring PLL, we should first make sure we're not running on PLL,
and if running on PLL, first switch to a fixed clock before proceeding
with PLL configuration.
Current code is doing the switch systematically which is not useful as
default startup case is to use MSI as sysclk source.
So add a test before doing this switch.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Unlike stated in 57df225b396e43358aac4cc998ed2e99fdb57780, RM0456.pdf
reference manual mentions about PLL1R that "Only division by 1 and even
division factors are allowed."
Though, in reference manual, there is one issue on PLL1R values
description, which should actually be:
0000000: pll1_r_ck = vco1_ck
0000001: pll1_r_ck = vco1_ck / 2 (default after reset)
0000010: Not allowed
0000011: pll1_r_ck = vco1_ck / 4
...
This description will be fixed.
Reflect this in binding and driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update w1 drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
Signed-off-by: Kumar Gala <galak@kernel.org>
Update dac drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Martin Jäger <martin@libre.solar>
This PR adds a KConfig option that allows moving
all .noinit content related to wifi a net stack into external
ram. This free dram space to application.
Linker script files are also modified so that the content
are mapped into external ram.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Update i2c drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <galak@kernel.org>
This power down bit of eSPI module is loacted in the bit 7 of PWDWN_CTL6
register rather than the bit 4. This commit fixs the incorrect setting.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This is a follow-up to commit 63d6cfd654.
Use a bit mask to store information about channels that need to be
driven by the PWM peripheral instead of inspecting the `seq_values`
array each time.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
As we phase out label properties from devicetree the devicetree
node may not have a label so utilize DEVICE_DT_NAME instead
which will use a label if it exists and the node name if not.
Signed-off-by: Kumar Gala <galak@kernel.org>
AST10x0 series SOCs provide the clock controller through the syscon
hardware block. The current driver supports the clock gating capability
for the hardware IPs embedded in the SOC. Each clock source has a
clock ID that can simply map to a bit in syscon registers CLK_STOP_CTRL0
(group 0) or CLK_STOP_CTRL1 (group 1). There are some clock sources
that don't have associated clock gating control, which are always on,
are grouped to into group 2.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
This is a follow-up to commit 63d6cfd654.
Revert unwanted PWM_NRFX_CH_POLARITY_MASK to PWM_NRFX_CH_COMPARE_MASK
replacement that was accidentally done in the above commit.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
With the introduction of the OSPI NOR flash controller
the stm32H7 serie requires the HAL MDMA in anycase.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the ssd16xx_read_ram() function that can be used to read the raw
contents of the two display RAM in the controller. This function is
similar to display_read(), but lets the caller specify the RAM to
operate on. The intention is that this can be used to read out the
contents of the old frame buffer after a partial refresh that
automatically swaps the black/red buffers.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Read operations only work on SPI controllers that support half
duplex. To enable read operations, set the device mode to half duplex
by adding the following to the device's DTB node:
duplex = <SPI_HALF_DUPLEX>;
If read requests will fail with -ENOTSUP if the device isn't in half
duplex mode.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The UC8179 supports automatic power management where the DC-DC is
enabled automatically. This is not supported on the UC8176. Explicitly
call PON/DRF/POF from uc81xx_update_display instead. This ensures that
the DC-DC is only enabled while actually updating the display for all
supported chips.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The CDI register in UC8176 and UC8179 have different layouts. Add a
helper function to the quirks structure to handle CDI updates.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The UC8176 and UC8179 chips that exist in tree have subtly different
register layouts. Use separate compatible strings for these chips and
a quirks structure that describe device-specific behavior.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The GD7965 driver is really just a vendor name for the UltraChip
UC8179. Rename the driver to UC81xx since there are other chips in the
family (e.g., the UC8176) with an almost identical register interface.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Some Series were calculating the pll output frequency from an
clock source index instead of the clock source frequency.
This commit resolves this issue for l0, l1.
get_pllout_frequency() is only used for PLLCLK, therefore remove it.
F2, F4, and F7 have several pll dividers and might decide to implement
these as clock sources won't need PLLCLK.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Update clock_control drivers to use DT_HAS_<compat>_ENABLED Kconfig
symbol to expose the driver and enable it by default based on
devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <galak@kernel.org>
The KW40Z/KW41Z don't have a Fixed Freq MCG clock so the code
associated with that in get_rate fails to build. ifdef around
the code with enum kCLOCK_McgFixedFreqClk so things work
correctly.
Signed-off-by: Kumar Gala <galak@kernel.org>
The ESP32 clock control for ESP32C3 was unified into a single
driver a while back. However the files associated with the
ESP32C3 didn't get removed than. Remove them now.
Signed-off-by: Kumar Gala <galak@kernel.org>
MISRA C:2012 Rule 14.4 (The controlling expression of an if statement
and the controlling expression of an iteration-statement shall have
essentially Boolean type.)
Use `do { ... } while (false)' instead of `do { ... } while (0)'.
Use comparisons with zero instead of implicitly testing integers.
The commit is a subset of the original auditable-branch commit:
5d02614e34a86b549c7707d3d9f0984bc3a5f22a
Signed-off-by: Simon Hein <SHein@baumer.com>
For the !SOC_I2C_SUPPORT_HW_CLR_BUS in which we implement bus
reset via GPIOs, change the devicetree properties to be actual
gpio properties and update the code to reflect this.
Signed-off-by: Kumar Gala <galak@kernel.org>
This commits refactors implementation of the pwm_set_cycles function
to fix the following issues:
- when a channel was already set with a non-zero pulse width, setting
cycles for another one required specifying a matching period value,
even if that value was to be ignored anyway when the channel was to
be set to constant inactive or active level; due to this limitation,
it was not possible to e.g. use the LED driver API and turn off a LED
while another one (within the same PWM instance) was blinking
- the above limitation also applied when a channel was set with a pulse
width equal to period (duty 100%); even though such channel was not
in fact using the PWM peripheral, other channels within the same PWM
instance were forced to use the same period
- after a PWM generation was started for a channel, it was not possible
to change its pulse width before two PWM periods passed (while it
should be possible to change it after every period); this was caused
by a looping mechanism that was unnecessarily activated in the PWM
peripheral
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In update the Kconfig to depend on devicetree, the SAM4L
driver was missing a 'default y'.
Also remove unnecessary 'depends on GPIO'.
Signed-off-by: Kumar Gala <galak@kernel.org>
This commit adds required code to setup pll2 and pll3 as defined
in dts. Also these plls can now be used as alternate clock sources.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit changes the range for stm32u5 pll divider values
to allow divider value of 1.
- DIVQ is allowed to beconfigured 1 for all PLL instances
- DIVR can be 1 for PLL2 and PLL3, but is not valid for PLl1.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit controls the stream busy flag of the dma channnel
Set as true : stream is busy each time the channel is
started or reloaded.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When the channel is overriden by the HAL,
the dma irq must always be handled (even if not busy).
Only when the dma channel is not overriden by the HAL
the irq is exiting when the channel is no more busy.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Intel ADSP CAVS is now a proper series with all CAVS SoCs running under
it. This will give us to Intel ADSP series:
- CAVS
- ACE v1.x
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
