Commit graph

25,525 commits

Author SHA1 Message Date
Sylvio Alves
34eb58c043 espressif: fix Kconfig style issues
Fix Kconfig style issues in Espressif files.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-08-21 18:41:52 +02:00
Jake Greaves
ba4bb91b1b drivers: serial: STM32U5 series lpuart
Allow LPUART to function and wakeup the device from STOP modes

Signed-off-by: Jake Greaves <jake.greaves@analog.com>
2025-08-21 17:13:36 +02:00
Sven Ginka
410ce46578 drivers: ethernet: vsc8541: fix init
added missing config.

Signed-off-by: Sven Ginka <s.ginka@sensry.de>
2025-08-21 17:06:21 +02:00
Guillaume Gautier
78fa4f0142 drivers: clock: n6: prevent clock configuration if NO_SEL is used
For STM32N6, when a device clock source is defined with NO_SEL, do not
configure it.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-08-21 17:05:57 +02:00
Kevin Wang
618b6b46a5 tests: drivers: dma: Update board config and overlay for adp_xc7k_ae350
1. Add config and overlay file in test scatter_gather for adp_xc7k_ae350
   and adp_xc7k_ae350_clic to support the test case.
2. Modify the config file in test chan_blen_transfer and loop_transfer
   because the tests do not support the NOCACHE memory configuration,
   the DCACHE configuration needs to be disabled.

Signed-off-by: Kevin Wang <kevinwang821020@google.com>
2025-08-21 15:58:35 +02:00
Kevin Wang
06bec271d9 drivers: dma: atcdmac300: Upgrade atcdmac driver to support series device
1. Upgrade the ATCDMAC driver to make it compatible with multiple
   ATCDMAC series drivers.
2. Rename the driver from ATCDMAC300 to ATCDMACX00.

Signed-off-by: Kevin Wang <kevinwang821020@google.com>
2025-08-21 15:58:35 +02:00
Ayush Singh
ef9baf67e7 drivers: clock_control: mspm0: Check SOC for HFCLK
- The function DL_SYSCTL_setHFCLKSourceHFCLKIN is not defined for
  MSPM0L11XX and MSPM0L13XX.

Signed-off-by: Ayush Singh <ayush@beagleboard.org>
2025-08-21 15:46:28 +02:00
Thomas Altenbach
7436b9dd85 drivers: flash: flash_stm32_qspi: Add support for cs-high-time
This commit adds support for the new cs-high-time devicetree property.
The QUADSPI_DCR_CSHT is now configured according to the value indicated
in the devicetree, for both single and dual flash modes.

Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
2025-08-21 15:46:12 +02:00
Thomas Altenbach
b147d78c2f drivers: flash: stm32_qspi: Use sample shift also in single flash mode
The QSPI 1/2 sample shift (SSHIFT) was only enabled in dual flash mode.
This feature is useful to guarantee that data is ready at the sampling
moment, even if the signals are a bit delayed due to PCB constraints.
Therefore, it should be enabled when possible (only supported in STR
mode).

Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
2025-08-21 15:46:12 +02:00
Guillaume Gautier
308e219ea5 drivers: pwm: stm32: use kernel clock instead of dedicated function
Now that the timer kernel clocks are defined in device tree, use the
clock get API to fetch the clock frequency instead of calculating the
value in the driver.
Removes the now unused function get_tim_clk.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-08-21 13:06:58 +02:00
Guillaume Gautier
2ab5452b32 drivers: counter: stm32: use kernel clock instead of dedicated function
Now that the timer kernel clocks are defined in device tree, use the
clock get API to fetch the clock frequency instead of calculating the
value in the driver.
Removes the now unused function counter_stm32_get_tim_clk.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-08-21 13:06:58 +02:00
Guillaume Gautier
4ccef2d443 dts: arm: st: wba: add support for timer kernel clock
Add support for timer kernel clock for STM32WBA.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-08-21 13:06:58 +02:00
Guillaume Gautier
525227e28a dts: arm: st: u5: add support for timer kernel clock
Add support for timer kernel clock for STM32U5.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-08-21 13:06:58 +02:00
Guillaume Gautier
7c44ebe493 dts: arm: st: h7: add support for timer kernel clock
Add support for timer kernel clock for STM32H7.

Define a new property for the timer prescaler in the RCC binding of H7.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-08-21 13:06:58 +02:00
Guillaume Gautier
1614da68c7 dts: arm: st: h5: add support for timer kernel clock
Add support for timer kernel clock for STM32H5.

Define a new RCC binding for H5 with the timer prescaler property (timpre).

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-08-21 13:06:58 +02:00
Guillaume Gautier
142f62a911 drivers: clock: stm32: add support for timer kernel clock
Add initial support for timer kernel clock for STM32.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2025-08-21 13:06:58 +02:00
Rafal Dyla
8876a3bbd2 modules: hal_nordic: nrfs: Disabling subscription
- Code optimization for platforms which don't use subscription feature
in the temperature service.
- Test adaptation to code changes

Signed-off-by: Rafal Dyla <rafal.dyla@nordicsemi.no>
2025-08-21 11:08:09 +02:00
Tomasz Bursztyka
347fb0a75a drivers: pwm: Use DEVICE_API relevantly on mspm0 driver
It was missing thus it was not possible to get a valid answer
from DEVICE_API_IS().

Signed-off-by: Tomasz Bursztyka <tobu@bang-olufsen.dk>
2025-08-21 06:52:34 +02:00
Ren Chen
80d5ecc148 drivers: spi: it51xxx: move interrupt flags check to compile time
as title.

Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
2025-08-21 06:51:59 +02:00
Ren Chen
8563510dfd driver: spi: it51xxx: enable spi clock only when spi transaction
This commit disables spi clock during idle to reduce power
consumption.

Tested with: reduce current cons. by around 0.08mA on it515xx_evb

Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
2025-08-21 06:51:59 +02:00
Derek Snell
6d748db7c7 drivers: mipi_dbi: nxp_lcdic: add DMA_ADDR_ADJ_NO_CHANGE
Update dma_block_config for memory to peripheral transfers.

Signed-off-by: Derek Snell <derek.snell@nxp.com>
2025-08-21 01:43:50 +02:00
Jake Greaves
e247cc3d9c drivers: counter: stm32: config rtc prescaler from DT
Handle RTC prescaler options inside RTC counter driver

Signed-off-by: Jake Greaves <jake.greaves@analog.com>
2025-08-20 18:46:47 +02:00
Jake Greaves
20d9780f61 drivers: rtc: STM32U5XX rtc scalers
Allow RTC prescalers to be configurable via dts

Signed-off-by: Jake Greaves <jake.greaves@analog.com>
2025-08-20 18:46:47 +02:00
Terry Geng
7210087cbc drivers: spi: spi_pico_pio: Implement DMA support for 4-wire operation
This commit largely mirrors the approach of implementing DMA in the pl022
driver.

Signed-off-by: Terry Geng <terry@terriex.com>
2025-08-20 18:46:31 +02:00
Henrik Brix Andersen
816f6cbd99 drivers: retained_mem: retained_mem_zephyr_ram: flush d-cache if enabled
Flush the data cache if cache management is enabled. Flushing the data
cache is required to ensure data retention across system resets.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2025-08-20 16:31:52 +02:00
Pieter De Gendt
08336629c1 drivers: display: mcux_elcdif: Optional start on init
After 8495e30726 some display controller
drivers failed to start. Make the start optional and enabled by default if
there are frame buffers allocated by the driver.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2025-08-20 16:31:09 +02:00
Camille BAUD
eab94972ed drivers: uart: Update bflb uart driver for BL70x
BL70x almost equal BL60x here

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-08-20 16:30:48 +02:00
Camille BAUD
d68418c068 drivers: clock_control: Add BL70x clock control
Adds clock_control driver for BL70x

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-08-20 16:30:48 +02:00
Camille BAUD
41ab7ec622 drivers: pinctrl: Update bflb pinctrl for bl70x
BL70x = BL60x here

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-08-20 16:30:48 +02:00
Camille BAUD
ea06ab3e93 drivers: syscon: Add condition for BL70x
BL70x = BL60x in this case

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-08-20 16:30:48 +02:00
Camille BAUD
0ab46a6d9c drivers: clock_control: Add BL61x clock control
Adds clock_control driver for BL61x

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-08-20 13:45:26 +02:00
Camille BAUD
14c449986e drivers: pinctrl: Add BL61x pinctrl
This adds pinctrl support in the bflb driver for BL61x

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-08-20 13:45:26 +02:00
Camille BAUD
61e79b32e6 drivers: syscon: fix headers used in BFLB efuse driver
Fixes wrong headers

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-08-20 13:45:26 +02:00
Jamie McCrae
db8f991c77 kconfig: Use $(...) instead of ${...} for getting variables
Updates this to comply with the Zephyr Kconfig recommendations

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-08-20 12:05:41 +02:00
BUDKE Gerson Fernando
77070941fa dts: phy: Add clock-reference prop in stm32u5-otghs-phy
The OTG_HS PHY from stm32u5a5xx device require the correct reference
clock frequency selction in SYSCFG_OTGHSPHYCR. The current default is
hard coded to 16Mhz (which matches the development board crystal).
However, a custom board my require a different crystal and then the
USB will not work. This add a required field in the
st,stm32u5-otghs-phy binding to force user to select the correct
clock reference. The current nucleo_u5a5zj_q baord was updated to
reflect the mandatory field.

Signed-off-by: BUDKE Gerson Fernando <gerson.budke@leica-geosystems.com>
2025-08-20 12:05:24 +02:00
Pieter De Gendt
f1b4c7c992 drivers: ethernet: nxp_imx_netc: Fix LAA bit location
The Locally Administered Address (LAA) bit should be set on the first
octet of the MAC address.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2025-08-20 09:29:14 +02:00
Adrian Gielniewski
163526b2fc drivers: Do not use deprecated OpenThread instance pointer.
Implementation should use a dedicated function to get OpenThread
instance instead of using the deprecated pointer from context.

Signed-off-by: Adrian Gielniewski <adrian.gielniewski@nordicsemi.no>
2025-08-20 09:28:10 +02:00
Alain Volmat
7d447a1dda drivers: clock: stm32: add PLLSAI2 support (common + L4)
Add stm32 common clock handling for the SAI2 PLL.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-08-20 09:28:02 +02:00
Alain Volmat
0abbc2f0f3 drivers: clock: stm32: add PLLSAI1 support (common + L4)
Add stm32 common clock handling for the SAI1 PLL.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-08-20 09:28:02 +02:00
Mike J. Chen
d47353928c drivers: dma_mcux_lpc: fix missing peripheral case
Change 4e0e3c990d caused
a regression in that SPI_MCUX_FLEXCOMM_TX DMA
transfers weren't properly set to be a peripheral
transfer.

Signed-off-by: Mike J. Chen <mjchen@google.com>
2025-08-20 07:40:13 +02:00
Declan Snyder
0f66420cb2 drivers: mcux_edma: Fix dtcm desc kconfig dep
The syntax was wrong for the chosen dtcm node. Also fixing build error
on 1180 by re-allowing the symbol on some tests.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-08-20 07:39:54 +02:00
Dmitrii Sharshakov
3835d9ae0f sensor: adltc2990: correct emulator implementation
Fix an out of bounds access found by ASan.

Also remove mock_i2c_reg_error which seems to never be read.

Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
2025-08-20 02:17:53 +02:00
Dmitrii Sharshakov
81455310b3 fuel_gauge: sy24561: improve emulation
Fix issues found by ASan, log register writes for inspection using
console harness.

Fixes: 5f84be617e

Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
2025-08-20 02:17:37 +02:00
Jonas Berg
41a0060338 Drivers: GPIO: Allow AW9523 to be used without interrupts
There will be an compilation error if there is no interrupt GPIO defined
in the device tree file, as parts of the config and data structs
have #if that depends on the presence of interrupt GPIO.

Use the same #if constructs also on the functions that use those
structs.

Signed-off-by: Jonas Berg <jonas.s.t.berg@gmail.com>
2025-08-20 02:16:57 +02:00
Mahesh Mahadevan
95e274b866 drivers: pinctrl_mci_io_mux: Fix sleep output configuration
The sleep output configuration should be skipped for pins
22 to 28.
This was causing incorrect GPIO wakeups when entering
standby mode on RW612.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2025-08-19 23:36:38 +02:00
Jilay Pandya
1e34d479eb drivers: step_dir: refactor stepper_handle_timing_signal
1. Reduce the spinlock scope in stepper_handle_timing_signal
2. perform a step each time the timing signal is called
3. Increment/Decrement actual_position and steps using atomics

Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
2025-08-19 23:36:20 +02:00
Jilay Pandya
3314473589 drivers: stepper: move_by(dev,0) shall return steps_completed
move_by(dev,0) shall stop the timing source and trigger
STEPPER_EVENT_STEPS_COMPLETED event

Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
2025-08-19 23:36:20 +02:00
Mahesh Mahadevan
4da30d01b8 drivers: mcux_os_timer: Handle counter overflow in Power Mode 3
The counter that is used in Power Mode 3 to track System time could
overflow for large timeouts.
Add an API that the power system could use to ignore wakeup events
from the timer.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2025-08-19 23:35:32 +02:00
Pieter De Gendt
300016c801 drivers: ethernet: stm32: Set LAA bit on MAC address based on device ID
The MAC addressed derived from the device ID is not assigned by the
manufacturer and therefor the Locally Administered Address (LAA) bit should
be set.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2025-08-19 19:14:45 +02:00
Tim Pambor
120f5a073c serial: uart_native_pty: IRQ support
Add support for the interrupt-driven API. Interrupts are
emulated using a polling thread.

Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2025-08-19 19:14:21 +02:00