remove log for link up, as it would already be logged by the networking
subsystem, when
CONFIG_NET_L2_ETHERNET_LOG_LEVEL_DBG=y.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
the dsa subsystem now sets the carrier,
therefore setting it in the nxp dsa port driver is redundant
and it can be removed.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add HCI driver for Realtek Ameba BT controller. The driver bridges
the Realtek HAL HCI transport to the Zephyr BT HCI driver API.
Signed-off-by: minyuan xue <minyuan_xue@realsil.com.cn>
Reset the semaphore before each MDIO transfer to discard any stale
k_sem_give() from the ISR that may have arrived after a previous
timeout. Without this, the next transfer would consume the stale
semaphore immediately and return incorrect data.
Signed-off-by: Martin Oliver Pitoňák <martin.pitonak@nxp.com>
The nxp_enet_mdio_wait_xfer() function ignores the return value of
k_sem_take(), causing it to always return 0 (success) even when the
MDIO transaction times out. This leads to callers receiving stale
data (0x0000) as a successful read result.
Fixes#99905
Signed-off-by: Martin Oliver Pitoňák <martin.pitonak@nxp.com>
Fixed the issue of possible out-of-bounds
access if write_data_block function was misused.
Size argument of the function was only validated
against the maximum allowed value, not the real
size of the data struct to be read, what could
cause accessing data past the boundary of the struct.
Fixes#81930.
Signed-off-by: Marcin Lyda <elektromarcin@gmail.com>
Add missing k_spin_unlock() and irq_unlock() in rzt2m_module_start()
error path. When interface_id >= 5 the function returned -ENOTSUP
without releasing either the spinlock or the IRQ lock.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Move k_spin_lock() past argument validation checks that only
inspect function parameters, not shared state:
- i2c_smartbond_apply_configure(): speed and mode are derived
entirely from dev_config; lock only needed before hardware
register writes
- i2c_smartbond_transfer_cb(): cb == NULL check is a pure
parameter check; lock only needed before accessing data->cb
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Add missing k_spin_unlock() in ambiq_rtc_set_time() when
test_for_rollover() fails. The function returned -EINVAL without
releasing the spinlock acquired earlier.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
neorv32_uart_pm_action() returned -ENOTSUP for unsupported PM actions
without releasing the spinlock acquired at function entry. Restructure
to use a single unlock/return path at function exit.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Add a hardware-accelerated CRC32 IEEE driver for Ambiq Apollo510
SoCs using the SECURITY peripheral. The driver implements the
Zephyr streaming CRC API (begin/update/finish) with the following
features:
- Supports CRC32_IEEE only (0x04C11DB7, reflected input/output)
- Configurable seed for chained/incremental calculations
- Boundary-aware DMA splits at TCM 4 KB and memory region crossings
- 32-byte cache-line aligned DMA with staging buffer fallback for
unaligned input
- Power managed via CRYPTO power domain using pm_device_runtime
- Binary semaphore serialises concurrent CRC sessions
New files:
- drivers/crc/crc_ambiq.c: driver implementation
- drivers/crc/Kconfig.ambiq: Kconfig symbol CRC_AMBIQ
Updated files:
- drivers/crc/Kconfig: source Kconfig.ambiq
- drivers/crc/CMakeLists.txt: add crc_ambiq.c under CONFIG_CRC_AMBIQ
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Fix the endpoint attribute comparison logic in uhc_mcux_check_hal_ep()
to properly handle USB endpoint max packet size (MPS) fields.
The previous code compared the raw MPS value against maxPacketSize,
but the MPS field encodes both the packet size and the number of
additional transactions per microframe for high-speed endpoints.
Extract and compare these fields separately using USB_MPS_EP_SIZE()
and USB_MPS_ADDITIONAL_TRANSACTIONS() macros. This ensures endpoints
are correctly reinitialized when either the packet size or transaction
multiplier changes.
Also restructure the conditional logic for clarity: return early if
no endpoint exists, then check if attributes have changed and close
the endpoint if needed.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
If the kQTMR_Compare1Flag is set when setting the alarm, the callback
would fire immediately causing unwanted behaviour in the applcation.
This PR clears this flag before setting an alarm to prevent this
premature firing.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
The NXP HAL for the i.MX 8M family (MIMX8MM, MIMX8MN, MIMX8MQ,
MIMX8ML) exposes only kCLOCK_QspiClkRoot; kCLOCK_FlexspiClkRoot is
unavailable, so building the IMX_CCM_FLEXSPI_CLK case of
mcux_ccm_get_subsys_rate() fails for any board that adds a flexspi
node on an 8M SoC.
Select kCLOCK_QspiClkRoot on CONFIG_SOC_SERIES_IMX8M and keep
kCLOCK_FlexspiClkRoot for all other i.MX SoCs.
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
Adds full interrupt-driven UART support behind
CONFIG_UART_INTERRUPT_DRIVEN. Implements the Zephyr UART interrupt
API (FIFO fill/read, TX/RX enable/disable, TX-complete detection,
pending check, callback set). Extends the register map with
tx_trigger, error_pending, and error_enable fields and adds RX FIFO
count and error bit masks. Adds SERIAL_SUPPORT_INTERRUPT to Kconfig.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Implements interrupt support for the AESC GPIO driver.
Adds pin_interrupt_configure handling level (high/low) and edge
(rising/falling/both) trigger modes with proper
pending-clear-before-enable sequencing, manage_callback for
registering GPIO callbacks, and an ISR that aggregates all four
pending interrupt sources, clears them, and fires registered
callbacks. IRQ registration is done via a config function pointer
initialized at boot.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
The SF32LB MPI QSPI NOR write path uses DMA to feed the MPI data
register before issuing page program commands. If the source buffer
points into the same memory-mapped NOR window, DMA can fetch from
flash while the controller is programming it, which can hang the bus.
Add a page-sized aligned SRAM bounce buffer for such source buffers,
and use it as the DMA source for affected chunks. Also harden flash
range validation and reject partially overlapping mapped flash source
and destination ranges while treating an exact same-range write as a
no-op.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
- Replace the SDK-defined CMC0/CMC macro with DT_INST_REG_ADDR(0)
to obtain the CMC peripheral base address from the device tree
instead of from the NXP MCUX SDK header.
- Add a BUILD_ASSERT to catch missing or duplicate nxp,cmc nodes.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Wire the on-chip Ethernet MAC and MDIO controller on the ESP32-P4
into the eth_esp32 driver. Includes the DT nodes (eth, mdio),
espressif,esp32-eth binding refresh, board pinctrl entries for
RMII and SMI, board defconfig and Kconfig fragment enabling
NET_L2_ETHERNET, and the SoC P4 Kconfig options for buffer count
and size. Adds the related pinctrl table entries and GPIO signal
map values.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Move RMII data plane pin selection to the pinctrl-0 property using
the RMII_* macros from the SoC pinctrl header. The pads use dedicated
EMAC IOMUX, so the driver reads the (slot, GPIO) pairs and routes them
directly instead of through pinctrl_apply_state(). Update the esp32
ethernet kit board to use the new rmii_default group.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The NXP SCTimer's outInitState field defines the output levels applied at
initialization, before any PWM channel is configured. Needed for active
low loads to not flicker at startup
Signed-off-by: Johan Eklund <Johan@meck.se>
Add conditional GPIO selects for ST sensor drivers when their
bindings expose *-gpios properties, including properties inherited
from included common binding files.
This aligns Kconfig GPIO dependencies with devicetree binding data.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
rcar already had a function to map timing mode to a string. Move that
function into the shared header and use it from multiple drivers. Also
use a shared function to convert voltage to a string instead of open
coding it everywhere.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
The dma_suspend() implementation detected end-of-transfer based on
a software flag (stream->busy) rather than hardware status flags. This
is an issue because dma_suspend() is isr-ok and may thus be called while
IRQs are suspended; this prevents the DMA ISR from running and updating
software flags to reflect the actual hardware state.
This causes a deadlock if, while IRQs are suspended, a transfer on a
channel N completes then dma_suspend() is called to suspend channel N
while IRQs are still suspended. In this situation, the channel is idle
but stream->busy is still true because the DMA ISR could not execute.
Since suspending an idle channel has no effect, the SUSPF flag will
never become set and a deadlock occurs because both of the conditions
for exiting the loop in dma_suspend() will never be met.
Modify the function to rely exclusively on hardware flags to detect the
channel's current state, such that the loop will not deadlock even if
the DMA ISR cannot run because IRQs are suspended.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
On some STM32 SoCs, multiple comparators share a common NVIC interrupt
line, they can only be enabled at the same time with
CONFIG_SHARED_INTERRUPTS set. This means the IRQ handler can be called
even though the EXTI flag is not set.
This change makes shure the comparator trigger callback is only executed if
the EXTI line is pending.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
Nordic's nPM10 Series PMIC LED driver and Devicetree bindings.
LED driver outputs on nPM10 devices are multiplexed with GPIOs.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
On MCXW7x the clock controller does not auto-enable peripheral gates;
each driver enables its clock in init via device_is_ready() and
clock_control_on(), as already done by lpuart, lpi2c and gpio. Bring the
NXP CRC driver in line with that model: enable the CRC clock through the
clock-control framework when the node provides a "clocks" property
(guarded by COND_CODE_1, so MCXN/LPC parts without one are unchanged),
and add the clocks property to the MCXW70/MCXW71/MCXW72 CRC nodes.
The MCUX HAL CRC_Init() also ungates the clock, so the peripheral was
already functional; this expresses the clock dependency in devicetree
and lets the clock-control framework track it.
Tested with tests/subsys/crc on frdm_mcxw70 and frdm_mcxw71:
pass = 14, fail = 0.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The DMIC backend streams PCM samples from a host file via host-libc I/O
helpers, supports a command-line override for the input file path, is
documented in the native_sim board guide, and adds dmic to the supported
peripherals in native_sim.yaml.
Assisted-by: GitHub Copilot:GPT-5.4
Signed-off-by: Tomas Barak <tomas.barak@nxp.com>
Update common AIA coordinator shared by IMSIC and direct mode to
initialize based on which APLIC mode is configured in DT.
Signed-off-by: Omar Naffaa <onaffaa@qti.qualcomm.com>
Add ACP 7.X support to the AMD ACP SoundWire DAI driver
(drivers/dai/amd/sdw/acp_sdw_dai.c):
- Include ACP 7.X specific register headers (acp7x_chip_offsets.h,
acp7x_chip_reg.h) when CONFIG_ACP_7_X is selected
- Add a 4-instance SoundWire DMA channel map (SDW0-SDW3, 22 pins
each) for ACP 7.X
- Add acp_sdw_get_dma_channel() helper for per-instance channel
resolution, populating dma_hs_id for both DAI_DIR_RX and
DAI_DIR_TX directions
Signed-off-by: Sneha Voona <sneha.voona@amd.com>
Add ACP 7.X support to the AMD ACP interrupt controller driver
(drivers/interrupt_controller/intc_acp.c). When CONFIG_ACP_7_X is
selected the driver includes the ACP 7.X specific register headers
(acp7x_chip_offsets.h, acp7x_chip_reg.h) which define the interrupt
control and status register layouts for the ACP 7.X audio DSP.
Signed-off-by: Sneha Voona <sneha.voona@amd.com>
Add cellular modem driver for Nordic nRF93M1 Cat 1 bis module
The DTS binding was already submitted in #106289
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
Initialized new_cfg in adc_ad7124_channel_setup.
In order to determine if two channel configurations
are identical, memcmp is used. The channel configurations
are stored in structs, which means that there are padding
bytes which are also compared when using memcmp.
The proposed solution is to initialize the struct with 0,
which forces the padding bytes to also be zero. Later,
when assigning values to the actual fields of the structure,
the padding remains 0. This means that comparing two
zero-initialized structs with memcmp will only compare
the respective values of the fields inside the struct,
which is the expected behavior. A better idea might be
to actually compare field-by-field values.
Signed-off-by: Raluca Bozdog <raluca.bozdog@analog.com>
Added runtime selection of current-source: reselected before each
read operation, allowing channels to be read regardless of having
a shared current-source with another channel or not.
Multiple ADC channels share the same current-source pin,
which means that after the init of the ADC the current-source
which actually is set is the one of the last configured channel.
Reading from other channels in the same application will not
return correct values, because the current-sources of the other
channels are only shortly configured during init and then
written over by the last channel configuration.
To overcome this, the application would need to call the
channel_setup function before each sample read, which
essentially means that a runtime reconfiguration should be
handled by the user, which comes against the expected ADC behavior.
To solve this, the proposed method is to apply the current source pin
inside the driver, before each read. The current_source_pin, thus,
becomes a property of an adc_channel itself, instead of being an adc
global field. The iout index value is also added to make sure that IOUT0
fields of the IO_CONTROL_1 register are not overwritten when modifying
the values of IOUT01 fields of the same register.
Signed-off-by: Raluca Bozdog <raluca.bozdog@analog.com>
Modified ADC configuration slot allocation logic:
The ADC has only 8 slots available for storing
channel configurations. The previous slot
allocation logic always tried to fill a new slot.
If none was available, it checked for an already
existing similar configuration to be used instead.
This caused problems when trying to read 9 channels.
Once all the slots are filled, no distinct configurations can be added.
The fix proposes this logic instead:
check if any similar configuration is already stored;
if so, use the similar one; otherwise, try to find a new slot;
if all spots are filled, an error code is returned
Signed-off-by: Raluca Bozdog <raluca.bozdog@analog.com>
Replace DT_NODE_HAS_PROP() instead DT_PROP() to test presence of
st,timeout property since it's more consistent. The DT property min value
is 1 hence testing against value 0 makes no sense.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Replace a COND_CODE_1() logic with use of DT_INST_PROP_OR() to get
the wakeup-line DT property for STM32 UART devices.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add "long press" reset and SHPHLD wake-up configurations to the nPM10
Series MFD driver's Devicetree properties.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
The capture-related code in the FlexPWM driver unconditionally
references kPWM_CaptureA*Flag / kPWM_CaptureB*Flag and CVAL2..CVAL5
registers, which do not exist on SoCs whose FlexPWM only supports input
capture on the X channel (for example MCXA153, where
FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA/B are 0 and only CHANNELX is 1).
This caused a build failure as soon as CONFIG_PWM_CAPTURE was enabled
on such SoCs.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Implement the Zephyr PWM capture API using the CTIMER
capture-clears-timer feature.
One capture channel is configured to fire an IRQ on the active
edge while ENCC/SELCC clears TC+PC on the opposite (or same) edge so
that CR latches the period or pulse width directly with no software
subtraction. The INPUTMUX is configured at driver init from a new
inputmux-connections DT property that lists <captsel-index, connection>
pairs.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
CTIMER PWM mode emits LOW for MR[pulse_channel] ticks then HIGH for the
remainder of the period, so PWM_POLARITY_NORMAL must map pulse_cycles to
(period - pulse_cycles), not pass it through unchanged.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
