Set the Interrupt Mask Register (IMR) before the RX Control Register (RCR)
when initializing the DM9051 ethernet controller. This prevents potential
race conditions where the receiver is enabled before interrupt masking
is properly configured.
According to the DM9051A datasheet, IMR bit 7 (PAR - Pointer Auto-Return
Mode) affects memory read/write pointer behavior. Setting IMR first ensures
the memory pointer configuration is ready before RX is enabled.
Signed-off-by: Ching Ping Sun <tom_sun@davicom.com.tw>
Change STM32 I2C driver to report that I2C bus recovery is not supported
when there are no GPIO defined for the sequence instead of returning
a IO error, helper caller (possibly a tests samples) to handle this
specific error case.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
The CLOCK_ATTRIBUTES reply structure has a clock_enable_delay field
only in protocol v3.0. When the platform implements v2.0 (e.g.
RK3588), the reply is 24 bytes but the driver expects 28 bytes,
causing "bad message len" errors.
Fix the inverted comparison in scmi_core_protocol_negotiate() and
store the resolved version in proto->version. Split the reply struct
into version-specific variants and select the expected reply length
in scmi_clock_attributes() based on the negotiated protocol version.
Signed-off-by: Piter Zhang <zhangtdvip@163.com>
Prevent flooding the log when a bus error occurs without a mailbox
generating an interrupt.
Fixes: #110654
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add rpi_fw_transfer_list() to send multiple property tags to the
VideoCore firmware in a single mailbox transaction. Takes an array
of rpi_fw_tag_list descriptors, each holding a tag, data buffer,
and size. All buffers are updated in-place with the firmware response.
Lower RASPBERRYPI_FIRMWARE_INIT_PRIORITY from 60 to 45 to ensure
firmware is ready before dependent drivers.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add a Raspberry Pi framebuffer display driver for the
Broadcom BCM2711 SoC. The driver communicates with the
VideoCore firmware via the Broadcom VideoCore mailbox interface.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
In target mode, read_in_progress is only cleared on STOP_DET.
When a master issues a compound transaction with multiple repeated
STARTs that transitions from read back to write and then read again,
read_in_progress remains set from the first read phase. On the
second read phase the ISR takes the read_processed path instead of
read_requested, returning data from the wrong offset.
For example, an EEPROM-style compound transaction:
S addr+W ptr Sr addr+R [data1] NAK
Sr addr+W ptr Sr addr+R [data2] NAK P
Where S = START, Sr = repeated START, P = STOP, W = write,
R = read, NAK = not-acknowledge (last byte of a read).
data1 reads correctly, but data2 returns stale EEPROM content
because read_requested (which returns the byte at the current
pointer) is skipped in favor of read_processed (which increments
first, then returns the next byte).
Reset read_in_progress when entering a new write phase (RX_FULL
with state != CMD_SEND). This ensures the subsequent read phase
correctly calls read_requested to fetch data at the updated pointer.
The bug can be reproduced with the following C test program using
the I2C_RDWR ioctl against any I2C EEPROM target:
/* 4-message compound: set ptr + read + set ptr + read */
struct i2c_msg msgs[4] = {
{ .addr = 0x54, .flags = 0, .len = 1, .buf = &ptr },
{ .addr = 0x54, .flags = I2C_M_RD, .len = 1, .buf = &rd1 },
{ .addr = 0x54, .flags = 0, .len = 1, .buf = &ptr },
{ .addr = 0x54, .flags = I2C_M_RD, .len = 1, .buf = &rd2 },
};
ioctl(fd, I2C_RDWR, &(struct i2c_rdwr_ioctl_data){msgs, 4});
/* Before fix: rd1 correct, rd2 wrong (stale offset) */
/* After fix: rd1 == rd2 == expected value */
Tested with FT232H master and RP2040 EEPROM target at 400 kHz:
10000 compound w+r+w+r cycles with 0 failures. Also verified with
libmpsse userspace I2C.
Signed-off-by: Vincent Jardin <vjardin@free.fr>
Guard Apollo3P Blue-only HAL fields (write latency, DMA boundary,
timing control, instruction/address size runtime control) behind
CONFIG_SOC_APOLLO3P_BLUE ifdefs so the driver also compiles and
runs correctly on Apollo3 Blue.
Add a dedicated MSPI_AMBIQ_BUFF_RAM_LOCATION default for Apollo3
Blue (0x40000) to account for its smaller SRAM layout. Gate the
MSPI_TIMING imply on SOC_APOLLO3P_BLUE since the timing API is
not available on Apollo3 Blue.
mspi_ambiq_timing_config() returns -ENOTSUP on Apollo3 Blue.
mem_boundary and time_to_break return -ENOTSUP if non-zero
values are requested on that SoC.
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Replace the two-line pattern:
net_buf_unref(buf);
buf = NULL;
with net_buf_drop(&buf) which performs both operations
atomically in a single step. Since net_buf_drop() also handles NULL
pointers checks for those before the call can be removed.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The DTS binding documents fifo-depth range as 2-256, but the
struct field is uint8_t which silently overflows 256 to 0.
Widen to uint16_t so the full hardware range is representable.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Add support for interrup driven UART for the numicro uart driver
targeting the nuvoton m48x line.
This is mostly copied from the uart_numaker driver with some changes.
Signed-off-by: Fiona Behrens <me@kloenk.dev>
Use the new scc driver in the uart for the m48x numicro soc.
This removes quite a lot of calls into the nuvoton BSP and replaces
them with functions using the clock driver.
Signed-off-by: Fiona Behrens <me@kloenk.dev>
This code snippet was originally removed by #109163 but then incorrectly
re-introduced by #107850 (most likely due to a rebasing error).
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The default initialization priority of 79 causes the cellular modem
driver to initialize before the network stack (priority 90). Set the
default to 91 to ensure the modem initializes after the network stack
is ready.
Signed-off-by: Povilas Selevicius <povilas.selevicius@quadigi.com>
Adds the CSG MFD driver for the Infineon HPPASS block. The CSG contains
five slices containing a DAC and comparator. This MFD owns the combined
comparator interrupt and manages dispatches to each child comparator
device.
Assisted-by: Github Copilot:claude-opus-4.7
Signed-off-by: John Batch <john.batch@infineon.com>
Most STM32 platforms do not have CONFIG_GPIO enabled by default.
Some tests, such as tests/drivers/disk/disk_access, require this
configuration to be enabled; otherwise, an error like "device API
is not gpio" occurs when testing SDMMC.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Correct stm32 I2C driver that did not report failure and left a semaphore
taken on some bus runtime configuration failures.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
- Create a dummy codec stub driver for testing and development purposes.
- Implemented dummy functions to satisfy the audio codec sample
- Add an audio_codec node and alias to the native_sim.dts
- Add Kconfig option
- Create a dts binding for the dummy stub
Assisted-by: GitHub Copilot:GPT-5.4
Signed-off-by: Tomas Barak <tomas.barak@nxp.com>
The WUU driver supports:
- External pin wakeup sources with configurable edge detection
(rising, falling, or any edge) and event types (interrupt, DMA, trigger)
- Internal module wakeup sources with interrupt and DMA event types
- Up to 32 external pins and 9 internal modules
- Recording and checking of triggered wakeup sources
- Integration with the WUC (Wakeup Controller) subsystem
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Replace direct ethernet context manipulation with new
net_eth_set_if_type_wifi() API across all Wi-Fi drivers.
Signed-off-by: Madhab Sharma <madhabsharma94@gmail.com>
I2S_TRIGGER_DRAIN was setting state to I2S_STATE_STOPPING but never
actually stopping the hardware, so LRCK and BCLK continued toggling
indefinitely after the trigger.
Wait for the current DMA buffer to finish (tx_ready_sem) before
calling am_hal_i2s_dma_transfer_complete and am_hal_i2s_disable.
Signed-off-by: Sofian Elmotiem <sofianelmotiem@gmail.com>
inst_idx was set to the DT probe index n instead of the hardware
module index. On Apollo510, if only i2s1 is enabled, n=0 but the
HAL needs 1. am_hal_i2s_initialize ends up on the wrong hardware
block while the ISR and DMA stay wired to i2s1, so the ISR never
fires and the clocks on the wire are wrong.
Fix: derive the hardware module index from the interrupt number
relative to i2s0, matching the pattern in other Ambiq IOM drivers.
i2s_data_format and i2s_io_config were module-level globals mutated
by configure() on every call. Multiple instances stomp each other,
and a single instance carries stale fields across re-configure calls.
Fix: move both structs into i2s_ambiq_data and copy from const
defaults at the top of configure().
Signed-off-by: Sofian Elmotiem <sofianelmotiem@gmail.com>
Implement the counter guard-period callbacks for the MCUX LPTMR alarm
configuration so late absolute alarms can be detected instead of being
silently skipped by users of the generic counter API.
Absolute alarms now compare the requested tick against the current
counter value and return -ETIME when the target is inside the late
window. The late check is disabled when the guard period is zero,
preserving the counter API contract that zero means no protection.
Convert accepted absolute alarms to relative compare values using the
LPTMR counter top value, so targets around wrap are treated consistently
with the counter API absolute-alarm semantics.
If COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE is set, the driver keeps the
alarm active and pends the interrupt so wrappers such as rtc_counter
can treat the late alarm as an immediate expiry.
Keep the non-alarm configuration returning -ENOSYS for guard-period
setup, since that mode still reserves the compare register for
top-value operation.
Tested on frdm_mcxa153 with tests/drivers/counter/counter_basic_api
using CONFIG_COUNTER_MCUX_LPTMR_ALARM=y, the same test with the LPTMR
alarm option disabled, and tests/drivers/rtc/rtc_api using a temporary
zephyr,rtc-counter node backed by lptmr0.
Also validated the review case with a temporary app that sets an
absolute tick-0 alarm while stopped. With guard period 0 the alarm API
returns 0 and fires the callback; with a nonzero guard period it returns
-ETIME and fires the callback when EXPIRE_WHEN_LATE is set.
The LPTMR late-alarm counter tests now run instead of being skipped,
and the RTC API suite passed 5/5 with PROJECT EXECUTION SUCCESSFUL.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add helper code meant to be easily integrated into palette-backed display
drivers so that they can "automagically" expand their accepted input
formats to include RGB565 and RGB888, and automatically dither them down
to I_4 palette format.
Assisted-by: Copilot:gpt-5.4
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add helpers for the SCMI Reset Domain Management protocol and a Zephyr
Reset Controller driver that utilizes these helpers.
The update introduces protocol helper functions, a new driver,
relevant Kconfig and CMake entries, and device tree bindings.
Signed-off-by: Grygorii Strashko <grygorii_strashko@epam.com>
Signed-off-by: Svitlana Drozd <svitlana_drozd@epam.com>
Replace LL_UCPD_Init() usage, which requires building the LL UCPD `.c`
file, with plain variables and LL calls for portability. `uint8_t` is
used for lower footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Use the clock control API to enable the peripheral clock instead of
relying on LL_UCPD_Init().
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The lfclk_spinwait implementation is partially based on
k_cpu_atomic_idle() to idle the CPU while waiting for LFCLK events
if in ISR or in pre kernel. This implementation is fragile and
complex given k_cpu_atomic_idle() is a nop if in ISR, reducing it to
a polling check, and that IRQs are masked globally in pre kernel which
conflicts with the expected use of k_cpu_atomic_idle(), signified by
the need for manually calling NVIC_ClearPending().
This commit refactors the code to use a polling check, sleeping if
possible between checks. This simplifies the wait, without loosing
support for no multithreading since k_msleep() is available even
without threads.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Currently, restrict_tx_outside_tsp is false by default, and with that,
the NWP may transmit data during TWT sleep time. Many APs do not support
this also should not be the default behavior.
Signed-off-by: Muzaffar Ahmed <muzaffar.ahmed@silabs.com>
Add support for the ESP32-H2 SuperMini development board, a compact
board based on the ESP32-H2 RISC-V SoC with Thread/Zigbee and
Bluetooth 5 (LE) connectivity.
Signed-off-by: Ivan Shautsou <vano1002@gmail.com>
Ramdisk access fails with data abort when MMU is enabled, due to
using a physical address for the buffer instead of a mapped virtual
address.
Add support for MMU configurations by mapping the ramdisk
buffer to a virtual address space and storing this pointer in
the device's private data (`struct ram_disk_data`). Update all accesses
to use this virtual address when MMU is enabled.
With MMU disabled, the ramdisk continues to use
the original physical addressing as before.
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
Signed-off-by: Svitlana Drozd <svitlana_drozd@epam.com>
