When composite_channel_get() succeeds (rc == 0) for
FUEL_GAUGE_FULL_CHARGE_CAPACITY_UAH or FUEL_GAUGE_DESIGN_CAPACITY,
the function previously skipped assigning the fetched sensor_val into
val->full_charge_capacity_uah or val->design_cap. Handle rc == 0 to
correctly populate the property.
Assisted-by: Antigravity:gemini-3.6-flash
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The channel configure() helper rebuilt the config word from the
immutable base configuration on every call and applied only the
single bit being changed, so speed and strong pull-up settings
could not coexist and each bus lock reset them again. Track the
working configuration in the device data and mutate that, like the
ds2484 driver does.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The wait loop passed the HFCGCTRL register value to sys_test_bit(),
which expects a memory address, so the loop read from a wild address
instead of testing the CLK_CHNG bit. Test the register value with
IS_BIT_SET, as the npcx driver does.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The STM32 OTG (dwc2) core raises the incomplete-isochronous interrupt and
disables an isochronous endpoint when a transfer misses its (micro)frame,
for example when the endpoint ended up armed for the wrong even/odd frame.
The HAL handles this by disabling the endpoint and then invoking
HAL_PCD_ISOOUTIncompleteCallback(), but udc_stm32 never implemented it, so
the endpoint stayed disabled and was never re-armed.
As a result isochronous OUT reception stalls permanently after the first
missed frame: a UAC2 host-to-device (playback) stream delivers a few
zero-length packets and then goes idle, with the application seeing
data_recv with size 0. Isochronous IN (e.g. a UAC2 microphone) degrades
gracefully, so only the OUT direction was visibly broken.
Implement HAL_PCD_ISOOUTIncompleteCallback() to re-arm the pending
receive via HAL_PCD_EP_Receive(), which re-selects the correct even/odd
frame parity at arm time and resynchronises the endpoint. Recovering
isochronous IN requires going through the normal data-in completion path
and is left as a follow-up.
Verified on an STM32U575 (OTG-FS) UAC2 composite device: host playback now
reaches the peripheral continuously instead of stalling after a few frames.
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Peter Buchegger <peter.buchegger7@gmail.com>
The newly added PCA9530, PCA9531 and PCA9532 have a reset gpio pin. This
patch handles it, if set in device tree.
Signed-off-by: Juergen Werner <j.werner@aduart.de>
Extend PCA953x led driver implementation to include devices PCA9530,
PCA9531 and PCA9532 in addition to the original PCA9533.
Signed-off-by: Juergen Werner <j.werner@aduart.de>
Replacing all mentions of PCA9533 to implement more devices. Also
prepare a generalized device definition for the introduction of further
DT_DRV_COMPAT.
Signed-off-by: Juergen Werner <j.werner@aduart.de>
UC8253 has an undocumented quirk that swaps DTM registers after every
refresh. It was confirmed with Waveshare support and with tests.
Tested with the Waveshare SKU22698 e-paper HAT (UC8253) and
Waveshare SKU17575 (UC8175), connected to a Nucleo F446RE
via SPI.
Signed-off-by: Grabowski Łukasz <lukasz.grabowski@pcosa.com.pl>
This commit unifies border refresh logic for all drivers,
still allowing user to override CDI interval.
It settles for forcing Black2White LUT for border refresh.
It adds specific CDI function for uc8175, because it is handled
differently than in uc8176.
Since driver assumes auto-copy quirk enables when available it was fixed
to force it on init, when aplicable.
Tested with the Waveshare SKU22698 e-paper HAT (UC8253) and
Waveshare SKU17575 (UC8175), connected to a Nucleo F446RE
via SPI.
Signed-off-by: Grabowski Łukasz <lukasz.grabowski@pcosa.com.pl>
Added assert check for pitch equal width, because chip expects
continuous data and driver does not modify the buffer.
Added assert check for x position and window width to be aligned to
pixel per byte value.
Tested with the Waveshare SKU22698 e-paper HAT (UC8253) and
Waveshare SKU17575 (UC8175), connected to a Nucleo F446RE
via SPI.
Signed-off-by: Grabowski Łukasz <lukasz.grabowski@pcosa.com.pl>
This commit adds changes:
- mipi release on error
- check for ommited lut
- fix old/new data write to dtm logic
- check for undersized buffer on write
- change pixel format to MONO01
- rename shared functions for more generic name
Tested with the Waveshare SKU22698 e-paper HAT (UC8253) and
Waveshare SKU17575 (UC8175), connected to a Nucleo F446RE
via SPI.
Signed-off-by: Grabowski Łukasz <lukasz.grabowski@pcosa.com.pl>
1) Define the driver API and consequently enable K_OBJECT for this type
of device and fixes the build.
2) Check the device permission before executing code in kernel.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
Rename 'err_unlock' label to 'unlock' in can_mcan_send() to align with
the error cleanup label naming convention used throughout the file.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Remove unnecessary zero-init of 'nbtp' and 'dbtp' in
can_mcan_set_timing() and can_mcan_set_timing_data(), as they are
immediately assigned complete values.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
num_xfer is an output field the controller driver is contractually
required to populate - the struct i3c_ccc_payload documentation states
"It is expected for the driver to write to this after the transfer".
The Cadence RTIO driver does write it, but only from
cdns_i3c_rtio_irq_cmdd_emp(), which iterates the command responses
the IP actually retired. A command that is dropped without producing
a CMDR entry never updates num_xfer, and because sticky is only set
from responses that were seen, the transaction can still complete
successfully. The caller then reads a field the driver never wrote.
Added two helpers to i3c_cdns.c and call them before the transfer
is submitted.
Signed-off-by: Marek Borowski <marek@borowski.com>
The free-running 64-bit system counter with its absolute compare
register is a COMPARE_ORDERED backend. The driver keeps
timer_driver_cycle_get() (the counter) and timer_driver_set_compare()
(set the comparator and unmask), and the core takes over the tick
accounting, the deadline math, the range clamp and the announce.
smp_timer_init() primes the per-CPU comparator through
timer_core_smp_prime().
The driver's own cyc_per_tick cache goes: with
CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME the core precomputes the
value in timer_core_init().
The ISR keeps its hardware specifics: the Cortex-A9 erratum 740657
spurious-interrupt handling, and masking the level-asserted compare in
tickless mode, which the core's rearm unmasks again.
Declaring the counter's 64-bit width with TIMER_CORE_COUNTER_WIDTH
removes the driver's CONFIG_GDBSTUB-only widening of the cycle diff,
which existed only because the width was not stated.
timer_api and context pass on qemu_cortex_a53, UP and SMP.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
i2s_buf_write() acquires its memory block with K_FOREVER, so on a
multithreaded build the two error codes it documents for that step can
never be produced: -ENOMEM because K_FOREVER does not return it, which
also makes the error branch below the call dead code, and -EAGAIN
because nothing ever times out. An application that exhausts the slab
blocks forever instead of being told. Without CONFIG_MULTITHREADING the
slab treats every timeout as no-wait, so only -EAGAIN is unreachable.
The userspace path has its own copy. z_vrfy_i2s_buf_write() allocates
the same way and then flattens whatever it gets to -ENOMEM, which was
harmless only because that branch was equally unreachable. Both copies
now use SYS_TIMEOUT_MS(), which already maps SYS_FOREVER_MS itself, and
both return the slab's errno unchanged, so the two paths agree.
k_mem_slab_alloc() produces exactly the two documented codes: -ENOMEM
when told not to wait, which is what a configured timeout of 0 becomes,
and -EAGAIN when the wait expires.
One consequence is worth stating rather than leaving to be discovered:
drivers already apply the same configured timeout when enqueueing the
block, so this call can now spend it twice, once acquiring and once
enqueueing. Making it a single end-to-end deadline would need a way to
pass the remaining time into i2s_write(), which the API has no room for
today, so it is documented as a per-stage bound instead.
The in-tree suites are unaffected: the loopback test prefills exactly
NUM_TX_BLOCKS blocks into a slab of NUM_TX_BLOCKS, so every acquisition
succeeds without waiting.
Fixes#113333
Signed-off-by: Hsiu-Chi Tsai <hctsai@linux.com>
Add multicast filtering to both cores. The filter is rebuilt from
the joined multicast addresses using net_eth_mcast_addr_foreach().
Hash filtering is used when the hardware supports it, otherwise the
addresses are perfect filtered against the spare MAC address
entries, receiving all multicast should they not fit. The mode can
be selected in Kconfig and defaults to hash filtering when
available.
Assisted-by: Claude Code:claude-fable-5
Signed-off-by: Fin Maaß <info@finmaass.de>
CONFIG_I2C_DW_CLOCK_SPEED is defined in MHz in Kconfig.dw however
the HOLD_TIME_TO_TICKS macro is assuming it is in Hz resulting in
any configuration of i2c_sda_hold_time_ns defaulting to 1 tick.
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Manually trigger GPIO_IRQn after waking up from backup mode. Do not
disable retention ldo after waking up from backup mode as it causes
resets in standby mode.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Any gpio can be used to wakeup device from sleep/deepsleep modes
This commit add this feature inside driver.
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
The LP_TIMER_INT_ST_ALARM macro special-cases only ESP32-C5 to read
int_st.soc_wakeup_int_st. ESP32-P4 has the same LP timer register
layout: its int_st register has no alarm field, only
soc_wakeup_int_st, so enabling the rtc_timer node on ESP32-P4 fails
to compile.
Extend the condition to cover ESP32-P4.
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
Replace tcpci_tcpm_get_status_register() with type-safe, register-specific
helper functions.
Also fixed a bug in `tcpci_tcpm_get_snk_ctrl` and `tcpci_tcpm_get_src_ctrl`
where they were incorrectly passing the register address macro
`TCPC_REG_POWER_STATUS` instead of the enum `TCPC_POWER_STATUS` to the
old generic helper, which was causing those functions to always fail.
Fixes: #84719#84725#84732#84736#84746Fixes: #84747#84753#90722#90744#90725
Assisted-by: Gemini CLI
Signed-off-by: Keith Short <keithshort@google.com>
Remove tcpc_get_status_register() and tcpc_clear_status_register()
from the TCPC API and driver implementations as they are unused.
Assisted-by: Gemini CLI
Signed-off-by: Keith Short <keithshort@google.com>
Adding a new DMA driver for the PSE84 AXIDMAC hardware based on the
Infineon PDL driver. The AXIDMAC is a high performance DMA controller
that uses the AXI bus. It is typically used for large memory-to-memory
transactions.
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Brett Peterson <brett.peterson@infineon.com>
Add a sensor driver for the SoC die temperature on Raspberry Pi
BCM283x devices. The temperature is read through the VideoCore
firmware GET_TEMPERATURE property tag -- the source behind
`vcgencmd measure_temp` -- over the rpi_fw mailbox property
interface, and exposed as SENSOR_CHAN_DIE_TEMP.
The sensor owns no MMIO of its own, so it is modelled as a child of
the raspberrypi,bcm283x-firmware node.
Wire up the VideoCore mailbox (brcm,bcm2711-mbox) on the BCM2710, and
put the firmware (raspberrypi,bcm283x-firmware) node with its
shared-memory property buffer on the board, matching where rpi_4b
keeps them. Enable the sensor on the Zero 2 W and the Pi 4 B.
Signed-off-by: Jonathan E. Peace <jep@alphabetiq.com>
Add a DAC driver for the 10-bit, 30Msps DAC inside the PSC3 series'
HPPASS CSG. Each instance represents a single DAC inside a CSG slice.
This driver implements the Zephyr DAC API in direct-write only mode (no
LUT or slope generation). The driver handles DAC configuration and
output settings, as well as interrupt handling for the DAC interrupt.
The driver provides for deglitch properties (see TRM reference for
details) and sets an (optional) initial value for the DAC output.
Assisted-by: Github Copilot:claude-opus-4.7
Signed-off-by: John Batch <john.batch@infineon.com>
This commit moves pinctrl registers definition file to RTS5817
soc directory, because gpio driver will also include this file
Signed-off-by: Darcy Lu <darcy_lu@realsil.com.cn>
GITS_CBASER.Size is encoded as (number of 4KB pages) - 1 per the
GICv3 ITS specification. Write pages-1 instead of the raw page count.
Signed-off-by: Li Wan <wanli@kylinos.cn>
Update driver to use new HAL library that supports both
Series 2 and Series 3 SoCs that share the same IP.
Split the check for transfer doneness in the block append
function into semantically equivalent parts: Check CHSTATUS
to see if the channel is active when appending a block, and
check CHDONE in the ISR.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
GPIO index 32 belongs to GPIO_GRP1 bit 0, but the split used '> 32',
sending index 32 into a 32-bit shift on GPIO_GRP0 instead. Use '>=',
consistent with the gpio_idx - 32 addressing used for the high group.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The dma slot selection mapped any nonzero unit to the I2S1
trigger, so the esp32p4 i2s2 controller would bind its DMA
channel to the wrong peripheral. Compute the trigger from the
unit index and add the missing I2S2 trigger identifier.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
On esp32p4 the I2S_CLK_SRC_DEFAULT enumerator is an auto-select
sentinel with value zero instead of an alias of a concrete module
clock, so the clock tree resolved its rate to zero and every
i2s_configure() call failed with mclk_div equal to zero. Select
PLL_F160M explicitly on that soc and enable the source branch at
driver init. Transfers now execute; the remaining data-path
issues on esp32p4 are tracked separately.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a WS2812 LED strip driver on top of the pulse_io subsystem.
Pixel data is encoded as fixed-period cells with per-bit duty and
sent through a pulse_io transmit channel, so the driver runs on
any SoC with a pulse_io backend. Add a led_strip sample overlay
driving the on-board WS2812 of the esp32s3_devkitc through the
RMT backend, selected with the pulse_io file suffix.
Assisted-by: Claude Code:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add an RMT (Remote Control Transceiver) backend for the pulse_io
subsystem, derived from the standalone RMT driver proposal and
reworked around the vendor-neutral API. Channels map directly to
hardware channels, state is statically allocated and transfers
use the sync pulse_io calls with ping-pong refill and drain from
a shared interrupt. DMA is supported on ESP32-S3 through the last
transmit and receive channels.
Assisted-by: Claude Code:opus-4-8
Signed-off-by: Joel Guittet <joelguittet@gmail.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add tx_channel_mask and rx_channel_mask to the capability
descriptor so backends with dedicated transmit and receive
channels can expose which channel indexes support each
direction. The loopback backend reports all channels in both
masks.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a functional loopback backend that loops transmitted symbols
back on receive, with deferred async transmit completion and a
streaming receive path. Add ztest suites covering capabilities, the
channel lifecycle, configuration, codec encode/decode, sync and
async transfer, streaming receive, and the userspace syscall path.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the pulse_io subsystem API: the public header with the driver
vtable, capability and configuration structs, the SYMBOL and CELL
submission descriptors, sync and async transmit and receive entry
points, and the byte/symbol encoder and decoder helpers.
The channel lifecycle and transfer calls are exposed as syscalls
with userspace verification handlers. Includes the controller
binding, subsystem documentation, release note and maintainer entry.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
MSPI is read as an initialism, so it takes "an", not "a". Fix the
remaining occurrences across the MSPI headers, the JEDEC NOR flash
driver and the MSPI samples.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
move_by() and run() logged timing source update and start
failures but always returned success. Return the captured error
like the step_dir controller does.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
step_work_timing_source_start() and _stop() returned the raw
k_work_reschedule() and k_work_cancel_delayable() results, which are
positive on success, while the timing source API documents 0 on success
and a negative errno on failure. Normalize both so that callers can
propagate the return value unchanged.
Assisted-by: Claude:opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
adxl355_submit_stream() read route_to_int2 from the driver data
struct, which is never initialized and thus always false, so boards
wired to INT2 toggled the FIFO_FULL_EN1 bit instead of EN2. Use the
devicetree-derived value from the config struct, as the trigger code
does, and drop the dead data-struct member.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The call to adxl355_stream_irq_handler() was nested inside an
unrelated CONFIG_ADXL355_TRIGGER_OWN_THREAD guard, so with STREAM
enabled and the trigger mode at NONE or GLOBAL_THREAD the GPIO
callback disabled the interrupt and never completed the pending
stream request, hanging streaming forever. Guard the call only by
CONFIG_ADXL355_STREAM, matching the ADXL367/ADXL362 drivers.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
adxl355_decoder_has_trigger() returned false unconditionally when
CONFIG_ADXL355_STREAM was enabled, the only configuration in which the
buffer carries a struct adxl355_fifo_data header with status1. Invert
the guard to #ifndef, matching get_frame_count in the same file, so
streaming builds report FIFO trigger events and non-streaming builds
return false.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
adxl355_submit_stream() compared and stored the 0/1 FIFO-watermark IRQ
enable flag in data->fifo_watermark, the cached FIFO_SAMPLES watermark
count, corrupting the value reported by attr_get and triggering
spurious INT_MAP rewrites and FIFO flushes. Use the dedicated
data->fifo_watermark_irq field instead, as sibling drivers do.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
