Update the MCXW7x clock control driver to support future
MCXW70 non-secure board enablement.
No functional change for current upstream configurations.
Signed-off-by: Waqar Tahir <waqar.tahir@nxp.com>
The i2s_configure verifier skipped the K_SYSCALL_OBJ() check on
cfg->mem_slab whenever the caller passed frame_clk_freq == 0, leaving
that pointer unvalidated when it reached the driver.
Zero mem_slab and block_size in the copied-in config on that path
rather than requiring a valid slab, so a stream can still be
unconfigured without owning one, as the API documents.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
commit 98500853d9 ("drivers: timer: nrf_rtc_timer: fix RTC init issue")
added an unconditional 46 us busy wait between the CLEAR and START tasks,
so that a counter value left behind by a bootloader is gone by the time
timer_core_init() reads the counter. On a cold boot the counter is
already zero, and on the simulated nRF targets tasks take effect
immediately, so there the wait only starts the system clock 46 us later.
That shifts the kernel tick phase relative to the radio timeline, and on
nrf52_bsim it made tests.bsim.bluetooth.mesh.bridge (the
brg_net_key_refresh.sh scenario) fail with the seed CI uses; every pull
request's bsim-test run has failed on it since the commit merged.
Only clear the counter, and wait for the clear to take effect, when it
holds a non-zero value, which is the case the wait exists for. Verified on
an nRF52 DK with a PRE_KERNEL_1 hook that starts LFCLK and RTC1 and lets
the counter run before the driver initializes: the counter register keeps
returning the old value for up to 46 us after CLEAR, so with START issued
immediately timer_core_init() can read it, while after the wait it reads
zero; k_msleep() and the uptime clock behave the same as on a cold boot.
The bsim mesh scenario passes again with the default seed. That scenario
is timing sensitive on its own (it also fails for other seeds without this
change), which is tracked in #118188.
Assisted-by: Claude:claude-fable-5-1
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Add a dwc_mac platform glue driver for the Synopsys DesignWare MAC
integrated in the Infineon XMC4XXX SoC family. The driver applies
pinctrl, configures the port control, connects the interrupt and
provides a small clock-control shim reporting the Ethernet and PTP
clock frequencies from the SCU.
The new ETH_XMC_DWC_ETHER_1000 symbol depends on !ETH_XMC4XXX, so the
generic dwc_mac driver can be used as an alternative to the XMC4XXX
Ethernet driver.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
The Infineon XMC4XXX MDIO driver was tied to the SoC series, so it
was enabled on any XMC4XXX SoC regardless of the Ethernet driver in
use. Depend on ETH_XMC4XXX instead, so the MDIO driver is only built
together with the XMC4XXX Ethernet driver and is left out when the
generic dwc_mac driver is selected.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Introduce polling-based SPI driver for the NXP Kinetis-L series.
The driver implements spi_context and utilizes standard Zephyr
Clock Control and Pinctrl subsystems.
Signed-off-by: Gabriel Ivo <gabriel.bozi@usp.br>
The WCH ESIG unit holds a 96 bit unique ID. Expose via the hwinfo
driver.
The WCH RCC unit accumulates the recent reset causes. Expose via the
hwinfo APIs.
Tested on the `bluepillplus_ch32v203` by running
`tests/drivers/hwinfo/api` and verifying the ID matches minichlink, and
that pressing the reset button makes the cause change.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Missing support for POR code for nrf54h20, add it.
Also fix some issues around secure WDT reset reasons (enum value was used
in a `#if defined(` expression).
Signed-off-by: Noah Pendleton <noah.pendleton@nordicsemi.no>
The CH32V series has between 16 KiB and 480 KiB of in-place
programmable program flash. Add a driver that implements the Zephyr
flash API, the appropriate Devicetree nodes, and overlays for the
`flash_shell` sample.
For the sample, trim back the default settings to fit within the ~64
KiB of flash and 8 to 20 K of RAM and add test partitions.
Use Devicetree to define the erase value. For the 003 and 006, this is
the common 0xFF but for the 20x/30x this is 0xE339. The flash API
works correctly on the 20x/30x but systems that require the erase
value to be a single byte, or assume that it is 0xFF, will not. This
can be addressed in future PRs.
Tested on the ch32v00x_core and bluepillplus_ch32v203 board by loading
the sample and running `flash test ...`. The
tests/drivers/flash/common test passes on the bluepillplus except for
the erase test which fails due to the ch32v203's half word erase
pattern.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Move the stm32n6 specific axisram driver out of the drivers/misc
folder since soc specific drivers should be located into the
related soc folder instead of misc.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
On the stm32U3 series, the Voltage Scale 2 (lower-range) is
accessible for a system clock freq up and equal to 48MHz.
This is specified by the RefMan RM0487 and prefered to minimize
the power consumption.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The SCL/SDA stuck low hardware timer is limited to about 255ms.
Add a new devicetree property scl-sda-low-timeout-ms that allows
designs to either modify the SCL/SDA stuck low timer or to disable
the timer completely.
Signed-off-by: Keith Short <keithshort@google.com>
Assisted-by: Antigravity:gemini-1.5-pro
Remove the redundant default n from the STM32 RTC counter Kconfig.
Boolean Kconfig symbols already default to n when no default is set.
Signed-off-by: Yiming Sun <ys160@rice.edu>
The driver initialization routine has been changed to use the generic
`timer_core_init`. As per nRF52840 RTC specification / section section
TASK and EVENT jitter/delay, a delay of 46usec should be observed after
a TASK CLEAR event before the counter is reset to 0.
Failing to do so will cause a spurious RTC wrap under certain
conditions, such as on the Arduino Nano 33. The timer core logic will
incorrectly assume that the RTC has wrapped, setting the main thread's
initial timeslice far in the future. As a result, k_msleep() blocks for
a very, very long time.
This bug was present before the driver rework, but changes to the driver
initialization code likely exposed it.
Fixes: #117522
Signed-off-by: Loic Domaigne <tech@domaigne.com>
The driver meanwhile supports the MCX N and MCX A series as well,
but the help text still mentioned the MCX E series only. List all
currently supported families instead.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
The explanation about the MAC raising DMA transfer completion on the
dedicated tx/rx lines and everything else on the common line only
applies to the MCX E31 series. Move that part into the corresponding
#if block and keep the generic note outside of it, so the comment
matches the code it documents.
No functional change.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
zephyr/drivers/pinctrl.h was included unconditionally and pulls in
pinctrl_soc.h. SoCs without a pinctrl driver (for example Rockchip
RK3588) fail to build when enabling snps,dwmac-mdio without pinctrl-0.
Guard the include with CONFIG_PINCTRL to match other drivers. Keep
DWMAC_MDIO_PINCTRL_ENABLED for optional pinctrl config and apply paths.
Signed-off-by: Yanzhao Cui <cuiyanzhao@kylinos.cn>
The SENSOR_CHAN_MTCH9010_OUT_STATE fetch path called gpio_pin_get_dt()
unconditionally, dereferencing a NULL port when the optional
output-gpios property is absent (e.g. UART-only configurations). Return
-ENOTSUP in that case, mirroring the guard used by the other fetch path.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
config->sleep_time holds the devicetree enum index used as the UART
command argument, but the fetch timeout math treated it as seconds, so
any sleep period of 4 s or more timed out early. Store the period in
seconds separately and widen the timeout values to uint32_t, since
256 s no longer fits in uint16_t once converted to milliseconds.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The decode entry guard rejected any buffer whose first character was
not a digit, so DELTA-only packets carrying a negative delta (e.g.
"-99\n\r") always failed with -EINVAL. Allow a leading minus sign; the
per-format range checks still reject negative measurements.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The pinmux controller provides the total number of muxable pins.
Read this number during initialization and check against it
during each pin configuration.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
The soft-reset half of reset_status() placed the "!= 0" comparison
inside the sys_test_bit() call, so it was evaluated as the bit index
argument instead of testing the returned bit. For any reset line
whose bit index is >= 2 this read the wrong bit of SOFT_RESET_CR and
misreported the reset state.
Move the comparison outside sys_test_bit() so the SOFT_RESET_CR bit
for the requested line is tested, matching the SUBBLK_CLOCK_CR half.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Fix the MemoryMapped mode for the mspi_stm32_xspi driver
Co-authored-by: Sara Touqan <zephyr@exalt.ps>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix compilation warning when building the mspi_stm32_xspi driver
without DMA config enabled.
The dts can declare a DMA channel but CONFIG_MSPI_DMA not set should
not use the DMA.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
With the commit c3109b9ebe
("usb: device_next: cdc_acm: rx throughput improvements"),
the CDC implementation queues as many buffers as are available. This may
trigger an error log, "<err> udc_rpi_pico: Endpoint 0x01 busy".
There is nothing wrong with the driver, it is just that another transfer
is queued while an endpoint is busy.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add DEVICE_DT_GET_COMMA helper macro to include/zephyr/device.h to
easily get a device pointer followed by a comma when expanding
devicetree foreach iterators like DT_FOREACH_STATUS_OKAY.
Update samples, drivers, and tests to use the common definition.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Assisted-by: Antigravity:gemini-1.5-pro
With CONFIG_UART_NS16550_DW8250_DW_APB, uart_ns16550_irq_tx_ready()
reports the transmitter ready whenever USR.TFNF is set, i.e. as soon as
the TX FIFO has room, while uart_ns16550_fifo_fill() writes up to
fifo_size bytes without checking how much room there actually is. When
the ISR runs with data left in the FIFO, the excess bytes are written to
a full FIFO and lost.
On the Silicon Labs SiWx917 (ulpuart, ns16550 with the DW8250 option)
this happens right after boot and about once per thousand fills under
load: the UART ISR is entered with no interrupt pending (IIR reads 0xC1)
while the FIFO still holds 15 of the 16 bytes of the previous fill, so
the fill loses up to 15 bytes. With the Bluetooth monitor in
interrupt-driven mode on that UART the stream had a truncated New Index
frame after every boot and lost 15-byte chunks every 1-2 seconds, while
the polled mode was unaffected.
Stop the DW8250 fill loop as soon as USR.TFNF clears, so that the driver
never writes more than the FIFO can take and returns the number of bytes
it actually accepted.
Fixes#117777
Assisted-by: Claude:claude-fable-5
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The controller reset faults if it reaches the peripheral before
the bus clock enable has taken effect, and whether it does
depends on unrelated code layout. Poll the clock state before
issuing the reset and fail the setup if it never comes up.
Assisted-by: Claude:opus-5
Signed-off-by: Jonathan Beri <jmberi@gmail.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The driver always selected the XTAL reference, which only
exists on v3.0 and newer silicon. On v1.3 the clock source
switch falls through to abort() and the boot panics before any
output. Select the legacy PLL_F20M source and its 20 MHz rate
when the minimum supported revision is below v3.0.
Assisted-by: Claude:opus-5
Signed-off-by: Jonathan Beri <jmberi@gmail.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The NXP MCX A family integrates the same DWC Ethernet QoS
controller as the MCX N series, but uses different PHY interface
selection. Extend the driver to also support the MCX A family
by guarding the SoC-specific parts with CONFIG_SOC_FAMILY_MCXA.
Add the PTP clock source and a ptp_clock child node to the MCXA5x
ethernet controller node, so the dwc_mac PTP clock driver can be
used.
ETH_NXP_ENET_QOS does not support PTP for the MCX A family, so
use the dwc_mac driver by default for the MCX A family, if PTP
support is required.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
The NXP MCX N family integrates the same DWC Ethernet QoS
controller as the MCXE31X series, but uses different clocks, PHY
interface selection and interrupt lines. Extend the driver to
also support the MCX N family by guarding the SoC-specific parts
with CONFIG_SOC_FAMILY_MCXN.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Now that all in-tree users have been migrated to the inclusive SPI
terminology, formally deprecate the old names:
- SPI_OP_MODE_MASTER, SPI_OP_MODE_SLAVE and the SPI_MOSI_OVERRUN_*
compatibility aliases now emit a deprecation warning through
__DEPRECATED_MACRO.
- The "slave" member of struct spi_config and the
spi_context_is_slave() compatibility wrapper are marked
__deprecated.
- The SPI_CTX_RUNTIME_OP_MODE_MASTER/SLAVE aliases now emit a
deprecation warning through __DEPRECATED_MACRO.
- The SPI_SLAVE Kconfig shim now selects DEPRECATED.
Document the renames in the v4.5 migration guide and release notes.
Per the API lifecycle policy the deprecated names are kept for two
releases, and are scheduled for removal in Zephyr v5.0.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use the renamed peripheral member of struct spi_config in the
MIPI-DBI SPI configuration initializer and in the Bouffalo Lab and
ESP32 MIPI-DBI drivers, following coding guideline rule A.2.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral and SDO/SDI terminology in the remaining
SPI-using drivers (audio, auxdisplay, bluetooth HCI, dac, eeprom,
ethernet, flash, fpga, gpio, haptics, hdlc_rcp_if, ieee802154,
input, led, led_strip, lora, mfd, misc, mux, rtc, sdhc, stepper,
video, watchdog, wifi) and the ec_host_cmd SPI STM32 backend,
following coding guideline rule A.2: switch to
SPI_OP_MODE_CONTROLLER/PERIPHERAL and SPI_SDO_OVERRUN_DT, rename
Zephyr-owned identifiers (the HCI SPI header buffers, the winc1500
bus wrapper transfer parameters), and update comments, log messages
and Kconfig help prose.
Vendor and out-of-scope identifiers keep their names: STM32
LL_SPI_MODE_SLAVE in the ec_host_cmd backend, the ATWINC1500 SDK I2C
SLAVE_ADDRESS definition, and the I2S codec clock-role variable in
tlv320aic26.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral and SDO/SDI terminology in ADC drivers,
following coding guideline rule A.2: switch the SPI configuration
constants to SPI_OP_MODE_CONTROLLER and update comments and log
messages.
The AD7124 internal master clock identifiers refer to the ADC's
clock source as named in the Analog Devices datasheet, not to SPI
bus roles, and keep their names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral and SDO/SDI terminology in display drivers
and the NXP LCDIC MIPI-DBI driver, following coding guideline rule
A.2: switch the SPI configuration constants to
SPI_OP_MODE_CONTROLLER, rename the spi_config field access to
->peripheral, and update comments.
Display controller command and register names from the vendor
datasheets (Levetop LT7680_CCR_SPI_MASTER, Solomon Systech
SSD1325_SET_MASTER_CONFIG and SSD16XX_CMD_MASTER_ACTIVATION,
Sitronix ST75256_MULTI_MASTER/SLAVE multi-display commands) keep
their names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral and SDO/SDI terminology in sensor drivers,
following coding guideline rule A.2: switch the SPI configuration
constants to SPI_OP_MODE_CONTROLLER and update SPI wiring comments.
For the Broadcom AFBR-S50 sensor, the spi-sdi-gpios/spi-sdo-gpios
devicetree properties (named from the sensor's own perspective per
the OSHWA resolution) replace spi-mosi-gpios/spi-miso-gpios. The old
property names are still accepted, marked as deprecated in the
binding, and used as fallbacks; the Zephyr platform glue in
modules/hal_afbr is updated to the renamed fields. The Broadcom
Argus API names (s2pi_slave_t, S2PI_*) come from the vendor library
and keep their names.
Occurrences that concern I2C rather than SPI (I2C controller ACK
behavior comments in NXP drivers, the lsm6dso sensor-hub I2C master
code using ST HAL APIs and application note quotes) and vendor
register names (TDK MPUREG_MASTER_LOCK) are out of scope and keep
their wording.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Realtek RTS5817 SPI
driver, following coding guideline rule A.2: switch to the renamed
core symbols and update comments, log messages and Kconfig help
prose.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral and SDO/SDI terminology in the remaining
SPI drivers, following coding guideline rule A.2. These changes are
limited to uses of the renamed core symbols (SPI_OP_MODE_CONTROLLER/
PERIPHERAL, spi_config.peripheral, spi_context_is_peripheral(),
SPI_SDO_OVERRUN_DT), driver-local identifiers (e.g. the silabs
mosi_overrun config members renamed to sdo_overrun), comments and
log messages. The Kconfig.renesas_ra8 hardware chip-select prompt
and help prose are reworded as well.
Vendor HAL/SDK and datasheet register identifiers keep their names,
notably: Ambiq IOSLAVE* base macros, Telink spi_master_* HAL calls,
TI driverlib SSI_MODE_MASTER, GD32 SPI_MASTER register bit, Nuvoton
BSP SPI_MASTER/SPI_SLAVE/QSPI_*/USPI_MASTER/SPI_CTL_SLAVE_Msk,
Microchip MSS_QSPI_CONTROL_MASTER and XEC CHPA_MOSI/CHPA_MISO
register bits, Silabs emlib EUSART/USART init symbols, and the
Zephyr PCIe core PCIE_CONF_CMDSTAT_MASTER bus-master bit referenced
by spi_pw.c (out of scope for this migration).
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Infineon CAT1 (PDL and
HAL based), PSoC-6 and XMC4xxx SPI drivers, following coding
guideline rule A.2: switch to the renamed core symbols, rename
driver-local identifiers (is_slave, spi_psoc6_master_get_defaults),
and update comments and log messages.
All Cypress/Infineon PDL identifiers (CY_SCB_SPI_MASTER/SLAVE,
Cy_SCB_*Master* APIs, enableMisoLateSample, masterSlaveIntEnableMask)
keep their vendor names, along with the devicetree property tokens
that mirror them (enable-miso-late-sample,
master-slave-int-enable-mask, miso-src).
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the NXP MCUX SPI drivers
(flexcomm, dspi, ecspi, flexio, rv32m1 lpspi and nxp lpspi),
following coding guideline rule A.2: switch to the renamed core
symbols, rename driver-local callbacks, helpers and variables
(spi_mcux_master_transfer_callback, spi_flexio_master_init,
lpspi_master_setup_native_cs, master_config/slave_config locals),
and update comments and log messages.
All NXP MCUX SDK API names, types and enum flags (SPI_Master*,
DSPI_Master*, kDSPI_*, ECSPI_*, FLEXIO_SPI_Master*, LPSPI_Master*,
*_master_config_t, *_master_handle_t, enableMaster) and CMSIS
register field macros (LPSPI_CFGR1_MASTER_MASK, *_MASTER_PCS_SHIFT)
keep their vendor names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Nordic nrfx SPI/SPIM/
SPIS shim drivers, following coding guideline rule A.2: switch to the
renamed core symbols, make SPI_NRFX_SPIS select SPI_PERIPHERAL
instead of the deprecated SPI_SLAVE, and reword Kconfig prose,
comments and log messages.
The nrfx HAL API names keep their vendor names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
