Commit graph zephyr/drivers
Author SHA1 Message Date
Krzysztof Chruściński
4c939fb674 drivers: debug: nrf_etr: Fix tracepoint ID for no argument case
Tracepoint ID was missing adjustment for case without any arguments.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2026-06-26 07:45:15 -04:00
Enoch Richbert Jebakumar
a1d29d07b1 drivers: sdhc: microchip: Add G1 SDHC Driver
Add G1 SDHC driver for Microchip SDHC Peripheral.

Signed-off-by: Enoch Richbert Jebakumar <enochrichbert.jebakumar@microchip.com>
2026-06-25 22:18:44 +01:00
Michael Zimmermann
6c92db1979 soc: silabs: define clocks for gecko_sdk based SoCs in device tree
The main goal of this change is being able to use counter_gecko_rtcc.c and
leuart_gecko.c on boards without an LFXO. This is the case for tyzs3.
The main changes are in soc/silabs/common, the rest is just to migrate all
of the boards.

This uses the device tree for clock-initialization only. I did not
implement a clock_control driver, because I don't see a need for that. The
drivers use CMU_ClockEnable, which abstracts away SoC differences already.

The config SOC_GECKO_HAS_HFRCO_FREQRANGE was removed, because:
- This can be detected via macros provided by gecko_sdk.
- There is an alternative to that API which wasn't implemented previously,
  but is now (cmuHFRCOBand_*).

I don't own any of the boards except for tuya tyzs3, but did my best to
avoid mistakes. That being said, I found several issues, which were present
in some of the boards already:

- sltb004a: This board has a 38.4MHz HFXO crystal, but it was configured to
  40MHz. I fixed that.
- tomu: This board uses HFRCO as it's HF clock, even though the SoC does
  not support SOC_GECKO_HAS_HFRCO_FREQRANGE. So it was probably running at
  the initial 14MHz instead.
- Many boards enabled leuart and rtcc (counter) peripherals, which need(ed)
  LFXO, without ever enabling LFXO. These peripherals were probably not
  working before this change.

Noteworthy finds:
- slwrb4321a: This board uses HFRCO as it's HF clock, but has a board.c
  where it enables HFXO to use it as the RMII reference clock. I'm not sure
  if it's okay to do that without calling CMU_HFXOInit first. I did not
  modify that code to not change behavior that I don't understand.

Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
2026-06-25 22:18:27 +01:00
Sean Kyer
006441e251 dts: nxp: mcxn23x: enable ELS TRNG support
Add ELS TRNG devicetree nodes for MCXN23x, enabling
FRDM-MCXN236 entropy source.

Signed-off-by: Sean Kyer <sean.actor@gmail.com>
2026-06-25 22:17:52 +01:00
Aleksandr Khromykh
6019ea7f95 bluetooth: hci: reduce logging messaging
Mesh uses legacy packets with extended advertiser.
Dropping of ext adv events is normal behavior.
However, mesh samples ara spammed these error messages
on some platforms.

Signed-off-by: Aleksandr Khromykh <aleksandr.khromykh@nordicsemi.no>
2026-06-25 10:28:50 -07:00
Benjamin Cabé
6c09c97555 drivers: counter: remove legacy DS3231 driver
Remove the deprecated counter-based Maxim DS3231 driver and its
dedicated API, binding, sample, and test coverage.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2026-06-25 10:28:27 -07:00
David Jewsbury
601d436820 drivers: flash: mramc: Add singlethreaded support
Adds conditional usage of mutex's to allow building
when CONFIG_MULTITHREADING=n

Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
2026-06-25 10:26:58 -07:00
Tim Pambor
4254b8041c flash: spi_nand: add bad block cache
Add a bad block cache by keeping a bad block table in memory.
This will speed up bad block checking at the cost of slightly
increased memory usage of 1 bit per erase block.

Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
2026-06-25 10:24:35 -07:00
Yangbo Lu
ed66226a5d drivers: ethernet: netc: control timestamping via PTP_CLOCK_NXP_NETC
Let's use unified CONFIG_PTP_CLOCK_NXP_NETC to control PTP
timestamping enablement.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2026-06-25 15:23:45 +02:00
Yangbo Lu
69dd347525 drivers: eth_nxp_enet: control timestamping via PTP_CLOCK_NXP_ENET
Let's use unified CONFIG_PTP_CLOCK_NXP_ENET to control PTP
timestamping enablement.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2026-06-25 15:23:45 +02:00
Yangbo Lu
49dda652d3 drivers: ethernet: select NET_L2_PTP_TIMESTAMPING for PTP clock
For PTP clocks which are explicitly part of Ethernet device
to provide PTP timestamping. We can select NET_L2_PTP_TIMESTAMPING
to provide Ethernet device driver complete dependency for PTP
timestamping support.

User doesn't have to take care of NET_L2_PTP_TIMESTAMPING enablement
in other places, and Ethernet device driver can control PTP
timestamping enablement via its PTP clock Kconfig option.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2026-06-25 15:23:45 +02:00
Yangbo Lu
44a37b4744 drivers: ptp_clock: select NET_L2_PTP_TIMESTAMPING
For PTP clocks which are explicitly part of Ethernet device
to provide PTP timestamping. We can select NET_L2_PTP_TIMESTAMPING
to provide Ethernet device driver complete dependency for PTP
timestamping support.

User doesn't have to take care of NET_L2_PTP_TIMESTAMPING enablement
in other places, and Ethernet device driver can control PTP
timestamping enablement via its PTP clock Kconfig option.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2026-06-25 15:23:45 +02:00
Yangbo Lu
a7033b23e6 net: l2: use NET_L2_PTP_TIMESTAMPING
Renamed NET_L2_PTP Kconfig option to NET_L2_PTP_TIMESTAMPING,
to make its function clear to user. Also made it depend on
PTP_CLOCK which was more reasonable.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2026-06-25 15:23:45 +02:00
Fin Maaß
bb4b888542 drivers: ethernet: dwc_mac: 1000: save rx_pkt and bytes
save rx_pkt and bytes, like in the qos mac, in case
we got already got fragments of later packets.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-06-25 15:22:05 +02:00
Dhanoo Surasarang
c628a3dc26 drivers: memc: Add IS66WV PSRAM driver over MSPI
Generic MSPI driver for the ISSI IS66/67WV Serial PSRAM family
(both wrapped-burst WVS and continuous WVR variants).

Implements MEMC read/write for bus-transaction access via MSPI.
When CONFIG_MSPI_XIP=y and xip-config is present in DT with
enable=true, also implements get_mem_base so the memcpy path
is used automatically on controllers with a memory-mapped
aperture.

Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
2026-06-25 15:21:42 +02:00
Julien Panis
557215c923 drivers: reset: reset_arm_scmi: Fix missing argument error
Macro DT_INST_SCMI_PROTOCOL_DEFINE() requires 10 arguments,
but only 9 were given. This patch adds the missing one.

Signed-off-by: Julien Panis <jpanis@baylibre.com>
2026-06-25 06:19:50 -04:00
Tahsin Mutlugun
dd786bb816 drivers: counter: max32_wut: Disable counter before setting compare
Disable Wake-Up Timer before setting a new compare value to comply with
user guide recommendations.

Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
2026-06-25 06:19:35 -04:00
Iustin Stolniceanu
5d5d54e0bf drivers: ethernet: xlnx_gem: fix start/stop device signatures
The March-2026 Ethernet API migration (commit db984ee196) added
struct net_if *iface to the net_if_api start/stop declarations but
the eth_xlnx_gem_start_device and eth_xlnx_gem_stop_device definitions
were not updated, causing a build failure for any target that enables
the GEM driver (e.g. Zynq-7000 with zperf).

Add the missing parameter to both definitions.

Signed-off-by: Iustin Stolniceanu <iustin.stolniceanu@analog.com>
2026-06-25 06:19:27 -04:00
Jonas Spinner
e87b4427b2 drivers: mbox: stm32_hsem: add LOG_ERR
Add LOG_ERR to channel validation error path.

Signed-off-by: Jonas Spinner <jonas.spinner@burkert.com>
2026-06-25 06:18:38 -04:00
Eli Hughes
123c5082f8 flash: mcux flexspi nor: add IS25LP512M support
Add explicit JEDEC handling for the ISSI IS25LP512M. Configure the
FlexSPI LUT for 4-byte Quad I/O reads plus 4-byte page program, sector
erase, and block erase commands.

The IS25LP512M uses nonvolatile SR1 bit 6 as the QE bit, so enable quad
mode with the existing S1B6 helper before using the 1-4-4 read path.

Hardware was verified by clearing SR1 QE from 0x40 to 0x00, setting it
back to 0x40, and passing quad erase/program/readback.

Fixes #111686

Signed-off-by: Eli Hughes <eli.hughes@nxp.com>
2026-06-25 06:18:28 -04:00
Basile GRUNER
6c430754bf stm32: adc: Enable ADC differential on STM32N6 SoC series
Change calibration process to handle differential calibration
Configure channel 10 to differential for Nucleo N657X0-Q and
STM32N6570-DK in `adc_api` test
Pin PA10 (Arduino A2) is shared as positive input for channel 11
and negative input for channel 10, allowing to keep default pin
configuration to test single and differential input.

Signed-off-by: Basile GRUNER <basile.gruner@smile.fr>
2026-06-25 06:17:58 -04:00
Andrzej Głąbek
81e4918804 drivers: flash_mspi_nor: Fix definition of NON_XIP_DEV_CFG_MASK
This is a follow-up to commit d7d1a64e27.

The above commit added `MSPI_DEVICE_CONFIG_IO_MODE` to `XIP_DEV_CFG_MASK`,
but in consequence it removed that bit from `NON_XIP_DEV_CFG_MASK` since
the latter is defined with `& ~XIP_DEV_CFG_MASK`. And that bit must be
present in `NON_XIP_DEV_CFG_MASK`, otherwise the driver will not configure
IO mode as expected in `switch_to_target_io_mode()` and `_acquire()`.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2026-06-25 06:17:32 -04:00
Andrzej Głąbek
ed42a9faf3 Revert "drivers: flash_mspi_nor: fix io mode used by mspi_xip_config()"
This reverts commit 97bfea46a0.

Contrary to what the above commit description says, the change it brings
does not in fact cause IO mode to be switched in the MSPI controller.
That is because `switch_to_target_io_mode()` uses `NON_XIP_DEV_CFG_MASK`
in its call to `mspi_dev_config()` and after recent changes (see commit
d7d1a64e27) that mask does not actually
include the `MSPI_DEVICE_CONFIG_IO_MODE` bit.
Revert the commit as it unnecessarily doubles the operations related to
switching the flash chip to desired IO mode (like the `post_switch_mode`
quirk), without fixing the actual problem with IO mode incorrectly set
in the MSPI controller.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2026-06-25 06:17:32 -04:00
Muhammad Waleed Badar
3275bbe6ed drivers: gpio: add raspberry pi bcm283x GPIO expander driver
Add a GPIO expander driver for the Raspberry Pi BCM283x, using
the VideoCore firmware property interface.

Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
2026-06-25 06:16:31 -04:00
5fa48e776d drivers: gpio: ch32v00x: add output open drain support
Add support for output open drain mode which is used by the tests in
`tests/drivers/gpio/gpio_basic_api/`.

While there, switch some magic numbers to the corresponding HAL
defines and be stricter on invalid or unsupported configurations.

Signed-off-by: Michael Hope <michaelh@juju.nz>
2026-06-25 06:16:10 -04:00
Harini T
446470ac05 drivers: rtc: rtc_counter: forward calibration to counter driver
Forward rtc_set_calibration() and rtc_get_calibration to the underlying
counter device via counter_set_calibration and
counter_get_calibration().
Both APIs use parts per billion (ppb), so no conversion is needed.
Translate -ENOSYS from the counter layer to -ENOTSUP to preserve the
error code documented by the RTC API.
Select COUNTER_CALIBRATION from Kconfig when RTC_CALIBRATION is enabled
to ensure the counter calibration API is compiled in.

Signed-off-by: Harini T <harini.t@amd.com>
2026-06-25 06:15:41 -04:00
Harini T
c2f5499724 drivers: rtc: rtc_counter: handle -ENOTSUP from counter stop and start
Allow rtc_counter_set_time() to proceed when counter_stop() or
counter_start() returns -ENOTSUP. Both APIs may return -ENOTSUP for
always-on counters that cannot be stopped or started. Without this,
rtc_set_time() fails unconditionally on such hardware.

Signed-off-by: Harini T <harini.t@amd.com>
2026-06-25 06:15:41 -04:00
Harini T
3a1c6a83e2 drivers: rtc: rtc_counter: use counter_set_value in set_time
Set the counter tick value directly in hardware via counter_set_value()
instead of relying solely on a software offset.
Fall back to the existing software offset when the counter does not
implement set_value or the desired tick value exceeds 32 bits.

Signed-off-by: Harini T <harini.t@amd.com>
2026-06-25 06:15:41 -04:00
Zhiyuan Tang
115dc1fb1c drivers: flash: add Realtek Bee nor flash driver
Add nor flash drivers for Realtek Bee family SoCs (RTL8752H and RTL87x2G).
Supports read, write, erase operations with page layout support.

Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
2026-06-25 06:15:22 -04:00
Aksel Skauge Mellbye
2f00e38dae drivers: entropy: siwx91x: Enable power management
Implement device runtime power management for the SiWx91x
entropy driver. This ensures that the RNG is automatically
reenabled after deep sleep.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2026-06-24 13:58:44 -04:00
Guillaume Gautier
29396ff5fb drivers: spi: stm32: rtio: check buffer length and data size concordance
Check that the buffer length is a multiple of the data size, and return
an error if it's not the case.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2026-06-24 13:57:19 -04:00
Guillaume Gautier
3a50cbfd03 drivers: spi: stm32: rtio: do not store stack-allocated pointer
Do not store stack-allocated pointers in the SPI data structure.
Set current_tx and current_rx to NULL since they are not used in RTIO
anyway.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2026-06-24 13:57:19 -04:00
Guillaume Gautier
0632d1917f drivers: spi: stm32: make rtio work in both dma and interrupt modes
Adapt the STM32 SPI driver so that in RTIO, transactions can be done either
in interrupt or in DMA mode, for different instances (until now, once
CONFIG_SPI_STM32_DMA was enabled, all transactions had to be done with
DMA).
Also use the asynchronous DMA callback for RTIO since it shares a lot of
code.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2026-06-24 13:57:19 -04:00
Guillaume Gautier
e0ef139751 drivers: spi: stm32: factorize transceive functions
The transceive and transceive_dma functions had some similar code.
Factorize them to reduce code duplication. transceive_dma is now called
from the transceive function, and only the latter is called from the
.transceive and .transceive_async API functions.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2026-06-24 13:57:19 -04:00
Guillaume Gautier
8e5edbf619 drivers: spi: stm32: fix slave mode for non-st,stm32h7-spi compatibles
This commit fixes issues that could arise notably when only the slave was
sending data (and the master was only receiving). By keeping track of bytes
transmitted in both directions (the context may not keep track of a
direction if the associated buffer is NULL or the length is 0), we prevent
the master side to abort the transmission prematurely.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2026-06-24 13:57:19 -04:00
Guillaume Gautier
a963a50054 drivers: spi: stm32: fix slave mode for st,stm32h7-spi compatible
Fixes the slave mode for st,stm32h7-spi compatibles by setting the
transfer size also for the slave device, and also waiting for SPI to not be
busy before calling the "complete" function (or else the transaction might
end too early in case where only the slave sends data).

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2026-06-24 13:57:19 -04:00
Fin Maaß
df4b6e21ae drivers: ethernet: dw_mac: qos: update core
align code to the recently added 1000 core.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2026-06-24 13:56:58 -04:00
Paulo Santos
7b41cc91cd modem: cellular: recover when CMUX fails to connect
CONNECT_CMUX had no handler for CMUX_DISCONNECTED, so a modem that never
establishes CMUX (left in an unknown state, for example a wrong baud
rate after an interrupted firmware update) stalled the driver in
CONNECT_CMUX with no way out.

Route CMUX_DISCONNECTED through modem_cellular_enter_recovery_state(),
the same recovery the init script uses, pulsing the reset line when one
is present and enabled to return the modem to a known state.

Signed-off-by: Paulo Santos <pauloxrms@gmail.com>
2026-06-24 13:56:47 -04:00
Paulo Santos
77b9ee0450 modem: cellular: extract recovery-state selection helper
The init-script failure path picks between a reset pulse, a power pulse
and idle based on which control GPIOs the board wires and the
reset_on_recovery setting. Factor that selection into
modem_cellular_enter_recovery_state() so other failure paths reuse it
without duplicating the GPIO gating.

Signed-off-by: Paulo Santos <pauloxrms@gmail.com>
2026-06-24 13:56:47 -04:00
James Growden
637eb6d2d4 drivers: i3c: stm32: refactors
Apply suggested refactors based on PR/ static analysis

Signed-off-by: James Growden <jgrowden@tenstorrent.com>
2026-06-24 13:55:42 -04:00
James Growden
3f25487bd2 drivers: i3c: stm32: Target mode support
This change adds basic target mode support for STM32 products.
Controller writes to target, and reading from the target, is supported.

Signed-off-by: James Growden <jgrowden@tenstorrent.com>
2026-06-24 13:55:42 -04:00
Harini T
e77c781620 drivers: counter: add Xilinx ZynqMP RTC driver
Add a counter driver for the Xilinx Zynq Ultrascale+ MPSoC Real Time
Clock. The hardware provides a 32-bit seconds counter driven by an
external crystal oscillator, one alarm channel, and a calibration
register with integer and fractional tick adjustment.

The driver implements the Zephyr counter API and is intended to be used
with the rtc_counter wrapper to expose the standard RTC API.

The RTC oscillator runs continuously so start() and stop() return
-ENOTSUP. Calibration support is gated by CONFIG_COUNTER_CALIBRATION.

Signed-off-by: Harini T <harini.t@amd.com>
2026-06-24 13:55:01 -04:00
Harini T
ff3a0697b3 drivers: counter: add calibration API
Add optional set_calibration/get_calibration operations to the counter
driver API. Calibration is specified in parts per billion (ppb). The
operations are gated behind CONFIG_COUNTER_CALIBRATION and return
-ENOSYS if not implemented by the driver.

Signed-off-by: Harini T <harini.t@amd.com>
2026-06-24 13:55:01 -04:00
Abin Joseph
5022cd26e6 drivers: dma: Add Xilinx ADMA driver support
Introduce Xilinx ADMA driver.

Features:
- Support for Xilinx ZynqMP ADMA (xlnx,zynqmp-dma-1.0)
and AMD Versal2 ADMA (amd,versal2-dma-1.0)
- Simple mode for single block memory-to-memory transfers
- Scatter-Gather mode for multi-block linked descriptor transfers
- Configurable 64-bit and 128-bit bus width support
- Maximum burst length of 256 beats for source and destination
- 64-bit addressing capability
- Software-managed cache coherency via flush/invalidate operations
- Optional hardware cache-coherent mode (device tree configurable)
- Interrupt-driven transfers with completion callbacks
- Error detection and reporting (AXI errors, overflow)
- Channel filtering support

Signed-off-by: Abin Joseph <abin.joseph@amd.com>
2026-06-24 13:54:41 -04:00
Kevin Chan
54cf1b3bd5 drivers: wifi: infineon: fix supplicant compiler error
PR#107029 is merged, it provide supporting wpa_supplicant.
That means wifi shell sample should be able to support
two different mechanism. One use wpa_supplicant,
another one use wifi_mgmt_ops directly without wpa_supplicant.

Some structures like wpa_supp_event_supported_band or functions
in airoc_wifi.c belongs to wpa_supplicant only.
Therefore if we compile wifi shell without wpa_supplicant,
it causes build error.

Signed-off-by: Kevin Chan <kevin.chan3@infineon.com>
2026-06-24 07:44:02 -04:00
Felix Wang
0eb7d2fb79 drivers: clock_control: nxp_mc_cgm: Expose system clock rates
Extend mc_cgm_get_subsys_rate() with five new cases so the standard
clock_control API can return rates for the system and source clocks
that MCXE31 peripherals point at via a clocks = <&mc_cgm IDX> phandle:
MCUX_FIRC_CLK, MCUX_FXOSC_CLK, MCUX_CORESYS_CLK, MCUX_AIPSPLAT_CLK,
and MCUX_HSE_CLK.

Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
2026-06-24 07:41:07 -04:00
Felix Wang
18fb944430 drivers: clock_monitor: Add NXP CMU_FM driver
This driver supports CLOCK_MONITOR_MODE_MEASURE:
configure programs REF_CNT from the user's window_ns and the
reference clock rate queried via clock_control; start() triggers a
single measurement whose completion is delivered through the
configure-time callback, with the device auto-disarmed before the
callback runs so the callback may restart the next measurement from
ISR context. get_rate() returns the most recent completed result.
stop() is ISR-safe and aborts an in-flight measurement; a transient
CONFIGURING state guards configure()'s unlocked clock query and HAL
init against concurrent start().

Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
2026-06-24 07:41:07 -04:00
Felix Wang
76e9cf7c53 drivers: clock_monitor: Add NXP CMU_FC driver
This driver supports CLOCK_MONITOR_MODE_WINDOW:
configure programs HFREF and LFREF from the user's expected_hz +
tolerance_ppm (auto-derived from the monitored clock via
clock_control when expected_hz is 0), start begins the background
comparison and stop disables it.

Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
2026-06-24 07:41:07 -04:00
Felix Wang
0cb2f853b3 drivers: clock_monitor: Add clock_monitor driver framework
Introduce a clock_monitor driver class that abstracts hardware that
watches one clock against another - frequency-window checkers,
frequency meters, and stuck/lost detectors. The subsystem exposes five
syscalls (configure, start, stop, get_rate, set_source).

clock_monitor_start() begins operation of whatever mode was installed
by configure(): continuous threshold checking in WINDOW mode, or one
measurement in MEASURE mode, whose result is delivered through the
configure-time callback with the device auto-returning to the stopped
state before the callback runs. Repeating measurement is achieved by
calling start() again from the callback; start() and stop() are
ISR-safe. clock_monitor_get_rate() polls the most recent completed
result and is the retrieval path for user mode, where callbacks may
not be installed.

The public header at include/zephyr/drivers/clock_monitor.h documents
the operating modes (WINDOW, MEASURE) and the event bitmap
(EVT_FREQ_HIGH, EVT_FREQ_LOW, EVT_CLOCK_LOST, EVT_MEASURE_DONE),
delivered exclusively through the configure-time callback.

Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
2026-06-24 07:41:07 -04:00
Xinyu Hong
e5d0b311c8 drivers: wifi: nxp: fix compile issue
On mimxrt1060_evk, CONFIG_CODE_DATA_RELOCATION_SRAM
is enabled by the board configuration, which causes arm_core_mpu.c
to reference __ram_text_reloc_start and __ram_text_reloc_size.
These symbols are only generated when at least one function
is relocated to RAM_TEXT. Since no code was previously placed
there, the build fails with undefined reference errors.
Fix this by relocating hot-path functions from ipv6_fragment.c
and ipv4_fragment.c to RAM_TEXT using function-level FILTER,
Only throughput-critical functions in the RX/TX fragment path
are selected, which also improves throughput performance.

Signed-off-by: Xinyu Hong <xinyu.hong@nxp.com>
2026-06-24 07:40:30 -04:00