Add driver for Microchip PolarFire SoC (MPFS) peripheral clock and soft
reset control.
Normally, the peripheral clocks and reset state are controlled by the
Hart Software Services (HSS) running on the Monitor processor. As an
alternative to using HSS services, applications can now enable the reset
controller in a device tree overly, for example:
&reset {
status = "okay";
};
&uart4 {
resets = <&reset MSS_RESET_ID_MMUART4>;
};
Embedded the reset controller node in system controller node.
Signed-off-by: Frank Kühndel <frank.kuehndel@embedded-brains.de>
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Avoid accessing tx_bufs or rx_bufs when they are NULL by adding proper
conditional checks before dereferencing. This addresses Coverity issue
CID 516225 (CWE-476).
Signed-off-by: sudarsan N <sudarsansamy2002@gmail.com>
Recent changes to net_link_addr structure to not use pointers
have made it necessary to update the modem_cellular driver
to ensure compatibility with the new structure definition.
Otherwise, an assertion failure occurs in subsys/net/l2/ppp/ipv6cp.c:40.
This commit updates that link address is set to NET_LINK_ADDR_MAX_LENGTH
least significant bytes of IMEI instead of IMEI total length.
Signed-off-by: Jani Hirsimäki <jani.hirsimaki@nordicsemi.no>
According to the C standard it is undefined behavior to use preprocessor
directives inside macro invocations.
Cppcheck stops when it see this UB with an error message, and so this
change will improve Cppcheck analysis
This is a refactoring to fix UB, no logical change is intended.
Signed-off-by: Daniel Marjamäki <daniel.marjamaki@cppchecksolutions.com>
Always return exit code 0 when cmd_uart_read stopped reading
data from UART. Instead, return with a error code in case
reading from the UART interface failed.
Currently, this command might return with exit code -1 because
uart_poll_in didn't return data and the read duration expired.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
use DT_INST_PROP_OR for local-mac-address, so
that it is not required to be set in dt, as there are
other ways to se the mac address.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
make sure, that zephyr,random-mac-address
has a higher prio, than local-mac-address, as
documented in ethernet-controller.yaml.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
make sure, that zephyr,random-mac-address
has a higher prio, than local-mac-address, as
documented in ethernet-controller.yaml.
Also make sure, that no vaild mac address
doesn't lead to init fail, as it can still be
set later via set_config.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Do not synchronously wait for endpoint interrupt bits when disarming
endpoints. Introduce ep_disabled k_event that makes it possible for
application to wait for the action to take effect which is necessary
when handling SetFeature(ENDPOINT_HALT) or SetInterface() requests.
This change improves incomplete iso IN and OUT handling performance,
especially when there are multiple isochronous endpoints that need
servicing.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
At High-Speed there is at most 25 us handling window for incomplete iso
IN/OUT and therefore determining which endpoints are isochronous is too
wasteful. Add lookup variable holding which isochronous endpoints are
enabled and limit the search to only enabled endpoints. For applications
with just one OUT and one IN isochronous endpoint this is optimal.
The lookup variable is updated only when mutex is held. Interrupt
handler accesses the variable read-only and in general there is no
problem is incomplete iso handling interrupt hits when the lookup
variable is updated, because:
* when endpoint is just activated, it cannot be source of incomplete
iso interrupt because the endpoint is not armed yet
* when endpoint is just deactivated, it was first disabled
If there is more than one isochronous endpoint same direction then just
relying on endpoint enabled is not necessarily optimal. However, in
order to be able to limit the search to only armed endpoints, the lookup
variable would have to be updated on every transfer preparation and
completion which would require more time-expensive synchronization.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Replace irq_lock() with spin lock which is proper synchronization
primitive that should be used. Because non-SMP implementations are
allowed to optimize spin lock to just locking interrupts the resulting
code is the same on all currently supported DWC2 targets.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Constify vendor quirks structure to not keep it in RAM. Use constified
vendor quirks structure directly if there is only one snps,dwc2 instance
to allow compiler inlining quirk implementation.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
TI MSPM0 SoC series has General Purpose Timer and Advanced control timers
with Compare block which is used to generate time expiry and output
waveform like PWM. Add driver support for MSPM0 PWM output.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
When loopback mode is enabled, the output of transmit serial shifter
is connected to the input of receive serial shifter internally.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Two DMA channels are assigned to TX and RX respectively:
- A TX DMA single request is asserted when there is space in the FIFO.
- A RX DMA single request is asserted when data is in the FIFO.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Optimize sckc_get_rate() to be called without configurations in
parameter, the selection of slow clock of the timing domain directly
comes from the register.
Optimize sckc_get_status() with return value "CLOCK_CONTROL_STATUS_ON",
slow clock is always on either driven by the RC oscillator or by the
32.768 kHz crystal oscillator.
Signed-off-by: Tony Han <tony.han@microchip.com>
Create bus helpers that will send ccc commands as well as update
items within the i3c descriptor. These are different than the
direct ccc functions as these can give a bit of convience to also
updating the descriptor.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The issue is found when doing shell command "i2c scan" on sama7g54-ek.
In this case no data will be transferred besides START and STOP. Data
abort would occur on accessing "msg->buf[msg->idx++]" when MMU is
enabled and "msg->idx" is very large.
Signed-off-by: Tony Han <tony.han@microchip.com>
CS hold time parameter is not correct which may cause bus fault
randomly.
System hang during status register reading after flash progromming which
is caused by parameter accessing in XIP mode.
Add dummy delay for READ command according the flash datasheet which is
required for SDR mode.
Use FlexSPI internal divider for clock updating instead of register in
CCM to avoid potential risk caused by flash access during clock updating
procedure.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
MT35 flashes could run in octal mode, Now the driver doesn't support
octal mode, add octal mode support for MT35 flashes.
Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
