Cadence MSPI controller uses a FIFO for indirect access operations on the
device on bus. Right now we directly use the physical address provided via
DT. This does not work on cores with MMU like A53; hence, map the FIFO
address the same way base contrller register space is mapped.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Add the read delay field in the timing configuration to allow configuring
delay for read data capture. This is supposed to be set either by the
peripheral using this controller at runtime or the user.
Additionally, also make the related struct and parameters public by
separating out the header.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Add a mechanism to configure the CS timing based on the configured clock
frequency for the peripheral (SCLK) in reference clock cycles for the
controller (RCLK).
Signed-off-by: Amneesh Singh <amneesh@ti.com>
We configure address length as 'length - 1' in the controller. This
currently does not check if the length is 0, in which case it causes
unsigned integer underflow, so add a check for that.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Cadence OSPI controller allows dual byte opcodes which are used by the
flash on the bus for modes such as Octal SDR/DDR. Hence, allow
configuration for dual byte opcodes.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Cadence OSPI/QSPI controller allows peripherals on its bus to have
configurations like 8D-8D-8D or 4S-4D-4D which require DTR configuration
for dual transfer rate. Hence, allow having DTR configuration in the
driver.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Add a Cadence MSPI peripheral driver, used in the TI K3 platform. The
driver was tested in 1S-1S-1S and 4S-4S-4S mode with the onboard infineon
s25h flash of the am243x launchpad and a custom driver for the flash using
this interface.
The command and dummy cycles are always taken from the xfer request and
never from the devicetree since different commands might have different
latencies.
The driver is somewhat basic for now and lacks e.g. callback
implementation. This is something that can be added in the future. If a
non-supported / invalid request is detected a error code is returned.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
The free-running 64-bit wall clock (external to the CPUs, shared across
SMP) with its absolute comparator. Arming disarms the comparator, writes
both halves and rearms it, so a counter that reaches the target during
that sequence leaves the match unarmed, and on a 64-bit counter it never
comes round again. That makes this a COMPARE_EXACT backend: the core
rewrites through its verify loop until the target is genuinely ahead of
the counter, which is what the driver's MIN_DELAY floor used to
approximate.
The driver keeps timer_driver_cycle_get() (the counter) and
timer_driver_set_compare() (arm the comparator), and the core takes over
the tick accounting: the last_count baseline, the deadline math, the
range clamp and the announce. The ISR reduces to acknowledging the
trigger and announcing.
The wall clock is a genuine 64-bit counter on this 32-bit CPU, so
TIMER_CORE_COUNTER_WIDTH is set to 64 to use its full range.
The driver keeps both cycle getters: count32() reads the counter's low
half in a single access where the core's extend path takes three, and a
driver that supplies one getter supplies the other.
Build-tested on intel_adsp/cavs25 and intel_adsp/ace15_mtpm.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add error logs for failed interrupt GPIO initialization. This should make
it clearer as to why CAN driver driver initialization failed.
Fixes: #117799
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Hold the Ethernet MAC in reset while the pads, the PHY interface and
the clocks are configured, and release it once the setup is done. The
PHY interface selection is sampled when the MAC leaves reset, so it
has to be in place before that.
The MCXE31x has no reset line for the MAC, so its clocks are gated for
the same purpose there.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
z_vrfy_charger_get_prop left k_val uninitialized and copied the whole
union out on success, while a driver only writes the one member the
property selects. Every successful read therefore handed user mode up
to 15 bytes of kernel stack.
Zero the union first. The fuel gauge verifier avoids this by copying
the caller's value in beforehand.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:claude-opus-5
union charger_propval carries two function pointers, selected by
CHARGER_PROP_STATUS_NOTIFICATION and CHARGER_PROP_ONLINE_NOTIFICATION.
z_vrfy_charger_set_prop copied the whole union in without inspecting
prop, and drivers store those members and later call them.
z_vrfy_charger_get_prop copied the union back out the same way.
Reject both properties in both verifiers, including when the callback
is NULL: the notifiers are device state, so allowing a clear would let
user mode disable a notifier a supervisor thread installed. A
BUILD_ASSERT on CHARGER_PROP_COMMON_COUNT forces the list to be
revisited when a property is added. Supervisor mode is unaffected.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:claude-opus-5
Adds two API functions:
- haptics_set_trigger() to configure edge-triggered effects
- haptics_trigger() to trigger the effect
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
GPTIMER has no absolute compare register, only a relative reload, so it is
a RELOAD backend: subtimer 1 free-runs as the cycle source and subtimer 0
is loaded with the relative delay the core derives from a tick-aligned
deadline. The driver keeps timer_driver_cycle_get() (the free-running
counter) and timer_driver_set_reload() (program subtimer 0); the core takes
over the announce baseline, the deadline math, the range clamp and the
announce. The ISR reduces to acknowledging, one-shot stop when tickless and
keep periodic otherwise, and announcing.
The subtimers run at the system rate divided by the shared prescaler, so
the core works in that divided cycle domain and derives its cycles-per-tick
from it. sys_clock_cycle_get_32() stays the driver's own and scales the
subtimer count back up to the system cycle rate.
timer_api, context, sleep and tickless pass on qemu_leon3, and timer_api
passes there with CONFIG_TICKLESS_KERNEL=n (the periodic path).
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
counter_rpi_pico_timer_set_alarm() computed the alarm target using
only the low 32 bits of the hardware's free-running microsecond
counter (TIMERAWL), which wraps every ~71.6 minutes. Once uptime
exceeded this, every subsequent alarm target was computed against a
stale/wrapped "now", causing timer_hardware_alarm_set_target() to
always report the target as missed. This made counter_set_channel_alarm()
return -ETIME permanently until reboot.
Fix by reading the full 64-bit hardware time instead of the
truncated low word.
Fixes#115552
Signed-off-by: Rene Zeiml <renezeiml@hotmail.com>
Assisted-by: Claude:claude-sonnet-5
Add support for adding multiple CAN controller state change callbacks to a
single CAN controller driver instance.
The new state change callbacks must be initialized by the caller via
can_init_state_change_callback() and added/removed via new API functions
can_add_state_change_callback() and can_remove_state_change_callback().
Adapt the existing API can_set_state_change_callback() API function to be a
wrapper for the new API functions.
Replace the mandatory can_set_state_change_callback_t() driver ops with an
optional can_state_change_callbacks_enabled_t() driver ops, allowing CAN
controller drivers to enable/disable state change IRQs based on whether any
state change callbacks are added.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The GPIO callback forwarded its first argument, which is the GPIO
controller device, to the sensor trigger handler instead of the
HDC302x device. Store a back-pointer to the sensor device in the
driver data and pass that to the handler.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
In trigger-on-demand mode, sample_fetch() issued the measurement
command and immediately read the result, but the sensor NACKs the
read until the conversion completes (up to 12.5 ms in LPM0), so every
fetch failed. Sleep for the datasheet measurement duration of the
selected power mode before reading.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The forward conversion borrowed from the integer part on a negative
remainder, producing val1 negative with val2 positive, which violates
the struct sensor_value contract. Keep the integer part truncated
toward zero and let val2 carry the sign of the result.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The probe fused the CRC check and the ID comparison with &&, so init
only failed when both the CRC was bad and the ID mismatched, making the
identity check dead code for any CRC-valid response. Split it into two
independent guards returning -EIO and -EINVAL respectively.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
Added pm_action suspend/resume/turn_on routine for I2C
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
TIMER_CORE_COUNTER_WIDTH used __LONG_WIDTH__, a predefined macro that
doesn't exist with older toolchains such as the Xtensa xt-clang
(Clang 10.0.1).
Use (__SIZEOF_LONG__ * 8) instead, which every GCC/Clang defines and
yields the same width.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
A CONFIG_CODING_GUIDELINE_CHECK build compiles the driver with
-Wimplicit-fallthrough=2, which flags two case reaches. The await power
on handler means its one, so mark it. The RING case in await ppp dead
does not, and ending it makes no observable difference, checked by
driving RING into that state with the timeout pending.
Signed-off-by: Paulo Santos <pauloxrms@gmail.com>
Added pm_action suspend/resume/turn_on routine for DMA
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Handle PSC3M6 SCB naming differences in the PDL. Select the
multi-processor-mode field for the UART under SOC_DIE_PSC3M6.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Signed-off-by: Niranjan M <niranjan@aerlync.com>
Extend the fixed-clock driver for PSC3M6. Map the 250M DPLL LP0/LP1
paths under SOC_SERIES_PSC3, guard the WCO startup error path
against PSOC4.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Signed-off-by: Niranjan M <niranjan@aerlync.com>
Add DWC2 vendor quirk for xmc4xxx SoC family.
The driver does not seem to support DMA mode on the older core versions.
The symptoms are: stalled setup transfers, no responses to IN tokens on
control or other IN endpoints.
Disable internal DMA mode by default for XMC4XXX SoC series.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add the tickless Hexagon system timer driver on top of the generic
tickless core (system_timer_generic.h). The H2 hypervisor exposes a
free-running 64-bit nanosecond counter via vmtimerop(hvmt_gettime) and
an absolute-deadline timeout via vmtimerop(hvmt_settimeout); the driver
supplies only these cycle-domain primitives and lets the generic core
own all tick accounting.
hvmt_settimeout matches on equality only: a deadline at or before the
current time is mapped by the hypervisor to BIGBANG, which disables
the timer rather than firing it immediately. This classifies Hexagon
as a TIMER_CORE_BACKEND_COMPARE_EXACT backend, whose core-side verify
loop re-arms a deadline the counter has already passed, removing the
need for a driver-side minimum-delay fallback.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
The GEM driver cast pointers to and from uint32_t in several places,
which truncates on 64-bit targets such as the ZynqMP Cortex-A53 and
warns with -Wpointer-to-int-cast / -Wint-to-pointer-cast there.
Signed-off-by: Iustin Stolniceanu <iustin.stolniceanu@analog.com>
The HAL based stm32 ethernet driver has no support for PTP on the
stm32mp13, so use the dwc_mac driver when PTP support is needed,
like on the stm32f1, f2 and f4.
Assisted-by: Claude:claude-fable-5-1
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The STM32MP13 has two instances of the MAC, so rework the glue to
define a device per enabled devicetree instance, with the pins,
clocks, descriptor rings, MAC address configuration and interrupt in
a per-instance configuration wrapped around the core's one.
The PHY interface of each MAC is selected in SYSCFG_PMCSETR, which is
a set-only register with SYSCFG_PMCCLRR as its clear-only counterpart.
Both are written directly, as the PMCCLRR bits read back as the current
configuration and the read-modify-write the LL helpers do on it would
clear the bits of the other MAC. Which set of bits a MAC uses is
derived from its register address rather than its devicetree instance
number, so a board enabling only the second MAC keeps working. MII,
RMII and RGMII are supported, with st,ext-phyclk selecting the MAC
kernel clock as the RMII reference or RGMII 125 MHz clock.
The descriptor rings go into the nocache section like on the other
series, which the MMU maps strongly ordered, with the physical
addresses the core expects on MMU platforms filled in.
Assisted-by: Claude:claude-fable-5-1
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Report the rates of the ethernet kernel clocks and PTP clocks, which
all live in ETH12CKSELR, so the PTP clock drivers can derive the
timestamp increment from the actual rate. A PLL that is not ready
gives an error rather than a zero rate.
Assisted-by: Claude:claude-fable-5-1
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The ETHxMAC gates run on hclk6, the ETHxCK gates on the ETHx kernel
clock. The DWC MAC MDIO driver needs the former to derive the CSR
clock divider from.
Assisted-by: Claude:claude-fable-5-1
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add an auto-register boolean devicetree property to the regset target
library binding and call regset_target_lib_register() during
regset_target_lib_init() when enabled. This allows I2C target devices to
be automatically registered on the bus at init time without requiring
manual registration.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Assisted-by: Antigravity:gemini-1.5-pro
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
This driver called arm_gic_irq_set_pending() directly; the portable
API removes the GIC-specific dependency.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Thanks to the bindings reorganization, a variable is now generated
properly for `zephyr,dsa-port`: use it!
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
als31300_convert_to_gauss() built a scale factor by dividing the 500 G
from the part number by the 4096 codes of the 12-bit ADC. Both halves of
that are wrong.
The raw reading is a sign-extended 12-bit quantity, so it spans 2048
codes either side of zero, not 4096. That alone made every
sensor_channel_get() magnetometer reading half the actual field.
More fundamentally, the datasheet does not define the scale as a ratio
of range to code span. It gives sensitivity directly -- 4 LSB/G typical
for the ALS31300-500 -- and states the conversion as
gauss = raw / sensitivity
with a worked example of -1018 LSB / 4 LSB/G = -254 G. The 500 G in the
part number is the "Optimized Sensing Range" (BIN), not the endpoint of
the code range: at 4 LSB/G the 2048 codes actually reach 512 G. Deriving
the scale from 500/2048 therefore implies 4.096 LSB/G, leaving a
systematic 2.3% error in a part whose own sensitivity error spec is
2.5% (3 sigma) on X/Y.
Use the specified sensitivity instead. Raw -1018 now converts to
-254.5 G, reproducing the datasheet example, and raw 2000 lands exactly
on the 500 G range endpoint. Document while here that the driver only
supports the -500 variant, since the -1000, -2000 and -JOY parts are
trimmed to different sensitivities.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:claude-opus-5
The RTIO decoder encoded readings as (value << shift), but Zephyr's Q31
sensor convention is real = q31 * 2^shift / 2^31, so an encoder has to
scale by 2^(31 - shift) to agree with the shift it publishes in the
decoded data header.
The driver advertises a shift of 16 for both magnetic field and
temperature, so every reading came out of the decoder at twice its true
value. Encode with (31 - shift) instead, matching what e.g. the BME280
decoder already does.
On the magnetometer path this was masked until now: the scale factor in
als31300_convert_to_gauss() was low by the same factor of two, so the
two errors cancelled and only the streaming temperature channel was
visibly wrong. The next commit fixes the scale factor.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:claude-opus-5
MSI-X table is device memory. Map it with K_MEM_CACHE_NONE so
vector and control register writes are not cached on architectures
that require uncached MMIO for MSI-X programming.
Signed-off-by: Li Wan <wanli@kylinos.cn>
Convert the RISC-V machine timer to system_timer_generic.h. The mtime
counter with its absolute mtimecmp compare is a COMPARE_ORDERED backend:
the driver keeps only timer_driver_cycle_get() (mtime) and
timer_driver_set_compare() (set_mtimecmp), and the core takes over the
cycle-to-tick accounting, the deadline math, the range clamp and the
announce. smp_timer_init() primes the per-hart comparator through
timer_core_smp_prime() rather than reaching into the core's baseline.
The public cycle counter applies the DT clock divider to raw mtime, so
the driver keeps its own sys_clock_cycle_get_32/64() and says so with
TIMER_CORE_HAVE_CYCLE_GET_32/64.
Tested with timer_api and context on qemu_riscv64.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
MTIP is level sensitive: it stays asserted for as long as mtime is past
mtimecmp, and writing mtimecmp is the only way to clear it. The ISR never
did, relying instead on sys_clock_set_timeout() being called after the
announce to move the compare forward.
That holds only as long as something does call it. On SMP with a per-hart
mtimecmp, every hart takes the interrupt when a shared deadline expires,
but sys_clock_announce_locked() returns early on all but one of them, so
only the announcing hart gets its compare rewritten. The others return
from the ISR with the compare still in the past and take the interrupt
again immediately, once per hart until each has had a turn as announcer.
It is not specific to SMP either. Nothing guarantees the kernel arms
another deadline: with no timeout pending it may legitimately choose not
to, and a driver has no business depending on that to stop its own
interrupt.
Push the compare out of reach on entry instead, so the interrupt fires
once for the deadline it was armed with. The arming path overwrites it
with the real deadline in the normal case.
Fixes: #115442
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
ETHER_EVENT_RX_COMPLETE is driven by the EDMAC's FR (Frame Received)
bit in EESR, a level/sticky status bit meaning "at least one frame
arrived", not a count. If several frames complete reception between
two interrupt services, the ISR still only gives rx_sem one credit.
The RX thread drained exactly one frame per credit, so under bursty
traffic completed-but-undrained frames piled up in the 8-entry RX
descriptor ring until it filled, causing the EDMAC to genuinely drop
incoming frames.
Drain the RX ring in a loop per wakeup instead of assuming one credit
equals one frame; the loop is inherently bounded by the ring size.
Also fix a related bug this exposed: renesas_ra_eth_rx() fell through
to call R_ETHER_RxBufferUpdate() with an uninitialized buffer pointer
whenever R_ETHER_Read() legitimately reported no data available; it
now returns NULL immediately in that case.
Signed-off-by: Henrik Maier <hwmaier@gmail.com>
