drivers: i2s: siwx91x: I2S clock initialization for siwx91x
Clock driver changes required for initializing the I2S clock for the siwx91x driver Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
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d95ca654cc
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dcdc8e8a55
2 changed files with 66 additions and 14 deletions
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@ -17,9 +17,9 @@
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#include "clock_update.h"
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#include "sl_si91x_clock_manager.h"
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#define DT_DRV_COMPAT silabs_siwx91x_clock
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#define DT_DRV_COMPAT silabs_siwx91x_clock
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#define LF_FSM_CLOCK_FREQUENCY 32768
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#define XTAL_FREQUENCY 40000000
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LOG_MODULE_REGISTER(siwx91x_clock, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
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@ -89,6 +89,20 @@ static int siwx91x_clock_on(const struct device *dev, clock_control_subsys_t sys
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/* Already done in sl_calendar_init()*/
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RSI_PS_NpssPeriPowerUp(SLPSS_PWRGATE_ULP_MCURTC | SLPSS_PWRGATE_ULP_TIMEPERIOD);
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break;
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case SIWX91X_CLK_I2S0:
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
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break;
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case SIWX91X_CLK_STATIC_I2S0:
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MISC_CFG_MISC_CTRL1 |= (1 << 23);
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RSI_CLK_PeripheralClkEnable(M4CLK, I2SM_CLK, ENABLE_STATIC_CLK);
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break;
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case SIWX91X_CLK_ULP_I2S:
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RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_I2S);
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break;
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case SIWX91X_CLK_STATIC_ULP_I2S:
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ULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_MASTER_SLAVE_MODE_b = 1;
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RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_I2S_CLK, ENABLE_STATIC_CLK);
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break;
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default:
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return -EINVAL;
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}
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@ -118,6 +132,12 @@ static int siwx91x_clock_off(const struct device *dev, clock_control_subsys_t sy
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case SIWX91X_CLK_DMA0:
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RSI_CLK_PeripheralClkDisable(M4CLK, UDMA_CLK);
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break;
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case SIWX91X_CLK_STATIC_I2S0:
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RSI_CLK_PeripheralClkDisable(M4CLK, I2SM_CLK);
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break;
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case SIWX91X_CLK_STATIC_ULP_I2S:
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RSI_ULPSS_PeripheralDisable(ULPCLK, ULP_I2S_CLK);
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break;
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case SIWX91X_CLK_ULP_UART:
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case SIWX91X_CLK_I2C0:
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case SIWX91X_CLK_I2C1:
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@ -162,6 +182,33 @@ static int siwx91x_clock_get_rate(const struct device *dev, clock_control_subsys
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}
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}
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static int siwx91x_clock_set_rate(const struct device *dev, clock_control_subsys_t sys,
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clock_control_subsys_rate_t rate)
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{
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uintptr_t clockid = (uintptr_t)sys;
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ULP_I2S_CLK_SELECT_T ref_clk;
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uint32_t freq;
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int ret;
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switch (clockid) {
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case SIWX91X_CLK_I2S0:
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RSI_CLK_SetI2sPllFreq(M4CLK, *((uint32_t *)rate), XTAL_FREQUENCY);
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RSI_CLK_I2sClkConfig(M4CLK, I2S_PLLCLK, 0);
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return 0;
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case SIWX91X_CLK_ULP_I2S:
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ref_clk = ULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b;
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freq = RSI_CLK_GetBaseClock(ULPSS_I2S);
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ret = RSI_ULPSS_UlpI2sClkConfig(ULPCLK, ref_clk, freq / (*((uint32_t *)rate) / 2));
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if (ret) {
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return -EIO;
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}
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return 0;
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default:
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/* For now, no other driver need clock rate */
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return -EINVAL;
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}
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}
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static enum clock_control_status siwx91x_clock_get_status(const struct device *dev,
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clock_control_subsys_t sys)
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{
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@ -209,6 +256,7 @@ static DEVICE_API(clock_control, siwx91x_clock_api) = {
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.on = siwx91x_clock_on,
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.off = siwx91x_clock_off,
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.get_rate = siwx91x_clock_get_rate,
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.set_rate = siwx91x_clock_set_rate,
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.get_status = siwx91x_clock_get_status,
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};
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@ -4,18 +4,22 @@
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_SIWX91X_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_SIWX91X_CLOCK_H_
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#define SIWX91X_CLK_ULP_UART 0
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#define SIWX91X_CLK_ULP_I2C 1
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#define SIWX91X_CLK_ULP_DMA 2
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#define SIWX91X_CLK_UART0 3
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#define SIWX91X_CLK_UART1 4
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#define SIWX91X_CLK_I2C0 5
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#define SIWX91X_CLK_I2C1 6
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#define SIWX91X_CLK_DMA0 7
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#define SIWX91X_CLK_WATCHDOG 8
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#define SIWX91X_CLK_PWM 9
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#define SIWX91X_CLK_GSPI 10
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#define SIWX91X_CLK_QSPI 11
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#define SIWX91X_CLK_RTC 12
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#define SIWX91X_CLK_ULP_UART 0
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#define SIWX91X_CLK_ULP_I2C 1
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#define SIWX91X_CLK_ULP_DMA 2
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#define SIWX91X_CLK_UART0 3
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#define SIWX91X_CLK_UART1 4
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#define SIWX91X_CLK_I2C0 5
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#define SIWX91X_CLK_I2C1 6
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#define SIWX91X_CLK_DMA0 7
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#define SIWX91X_CLK_WATCHDOG 8
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#define SIWX91X_CLK_PWM 9
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#define SIWX91X_CLK_GSPI 10
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#define SIWX91X_CLK_QSPI 11
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#define SIWX91X_CLK_RTC 12
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#define SIWX91X_CLK_I2S0 13
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#define SIWX91X_CLK_STATIC_I2S0 14
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#define SIWX91X_CLK_ULP_I2S 15
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#define SIWX91X_CLK_STATIC_ULP_I2S 16
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#endif
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