The constraints API offered by TI HAL is meant to be used externally,
for example, when implementing a policy using their policy mechanism
(not used on Zephyr). The API is likely designed for systems where a
thin RTOS is used (e.g., FreeRTOS, TI-RTOS?), places where you basically
get a Kernel and a few services around, but not a system like Zephyr
where you also get, for example, a power management subsystem. This
means that it gets difficult for an RTOS like Zephyr to use such HAL
APIs while using its own constraints API. The first question is why we
allowed such kind of HAL code to be part of upstream Zephyr. It
certainly does useful things, but it is also uses a HAL infrastructure
which is hardly exportable to an RTOS like Zephyr. Part of the
Power_init() code, for example, should likely be in a clock controller
driver, where Zephyr APIs can be used.
The _solution_ that was done to workaround this case was allowing custom
full re-implementations of the constraints API. So we are basically
overwriting a functional API with custom HAL code because of poor HAL
designs. This is in general a bad design principle. If we allow this, we
can hardly offer any guarantees to the API users. For example, is
re-implemented as thread-safe? What is the API behavior then? ...
Platforms like TI that have incomplete support in Zephyr tend to leverage
to HAL code certain functions that should be proper Zephyr
drivers. Such platforms should not influence the design of APIs because
they lack solid foundations.
This patch removes the custom implementation since the HAL has been
patched so that it forwards PM state constraints to Zephyr.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Currently xenvm board/soc is configured to use GICv2 and there
is no clean way(without modifying the source code) to alter this
configuration to use GICv3.
Due to the increasing number of users wishing to use GICv3, add
a new configuration called xenvm_gicv3 that enables GICv3.
Create a Kconfig file and add a config XENVM_USE_GIC_V3 that,
if set, will cause SOC_XENVM to select GICv3 instead of GICv2.
Update documentation accordingly.
Take the opportunity to remove the unnecessary config options
from the defconfig files.
Signed-off-by: Michal Orzel <michal.orzel@arm.com>
Use CLINT to send interrupts to another CPU. SMP support is kinda
incomplete without it.
This patch only enables it for riscv-privilege platforms - specifically,
"virt" one.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Secondary CPUs are now initialised and made available to the system. If
the system has more CPUs than configured via CONFIG_MP_NUM_CPUS, those
are still left looping as before.
Some implementations of `soc_interrupt_init` also changed to use
`arch_irq_lock` instead of `irq_lock`.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Add a new board to support Intel Tiger Lake H PCH variant of cAVS2.5.
Move common Kconfig options for cavs25 to soc level. No need to
replicate these for every board.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Aligning with the rest of PM API, replace pm_power_state_exit_post_ops
with pm_state_exit_post_ops.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Commit 7cdd10bf89
("soc: arm: nordic: add NRF_DT_GPIOS_TO_PSEL_BY_IDX") added a use of
NRF_GPIO_PIN_MAP to soc_nrf_common.h without including the relevant
HAL header where it is defined, hal/nrf_gpio.h.
Unfortunately, including that header causes even more problems, since
it causes undefined NRFX_ASSERT() calls to appear elsewhere in the
tree.
It's not really worth bothering to use this macro. Just expand it
inline instead.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Extend initialization code for nRF5340 application core to iterate over
child nodes of GPIO pin forwarder node and pass control over detected
pins to the network core.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Add a macro that allows to retrieve pin's PSEL from its devicetree
representation taking into account its index into GPIO array.
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
With a number of the i.MX SoCs (e.g., the i.MX8M Plus), NXP has moved to
supporting the integrated Cortex-M cores with the MCUXpresso SDK (MCUX).
As a result, certain Zephyr drivers (such as the IPM driver) need to be
updated to utlize this new MCUX-based SDK.
This change adds support for the MCUX Messaging Unit driver pulled in by
this PR:
https://github.com/zephyrproject-rtos/hal_nxp/pull/130
Additionally, this change enables the new IPM_IMX_REV2 config for the
mimx8ml8_m7 SoC target which utilizes this new revision of the driver.
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
The current MCUX IGPIO driver assumes that the target SoC supports
the DR_SET, DR_CLEAR, and DR_TOGGLE functionality, but some do not
(namely, the M7 core of the i.MX8M Plus SoC). Current releases of
the MCUXpresso SDK IGPIO driver contain utility functions to set,
clear, and toggle pins which include provisions to support SoCs
with and without DR_SET, DR_CLEAR, and DR_TOGGLE, and this change
switches to using these utility functions.
Additionally, this change enables GPIO support on the mimx8ml8_m7
target.
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
This register is a pre-define hardware slave A and can be accessed
through I2C0. It is not currently used, so it can be disabled to
avoid illegal access.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The Xtensa implementation of arch_irq_offload() required that the user
select the correct interrupt manually, and would race with itself if
invoked from separate CPUs (it was saved here by the main
irq_offload() function which has a semaphore to serialize access).
Use the new gen_zsr.py script to automatically detect the highest
available software interrupt, and keep a per-CPU set of
callback/parameter pointers.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Introduce a new "zephyr,memory-region" compatible to be used when a new
memory region must be created in the linker script from the devicetree
nodes using the compatible.
Remove also the LINKER_DT_REGION_FROM_NODE macro and add a new
LINKER_DT_REGIONS macro to cycle through all the compatible regions.
In the same PR modify the DTS files and the linker scripts.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This enables the below configuration so the AP and EC are able to
communicate over eSPI:
CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
We are enabling logging in the SoC, this should be an application
decision, not a hardware decision.
Additionally, we are disabling logging defaults for testing, which
results in some tests failing on those platforms due to missing messages
in the test output.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not include psl-in related code is the status of vsby-psl-in-list is
disabled, which can help reduce a little RAM/flash size.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Failures to boot are not exclusive to the cavstool.py, they can happen
with the kernel driver and --log-only too. For such a situation this
commit adds a useful delay and these two log lines (before the mmap
crashes eventually):
INFO:cavs-fw:Waiting for firmware handoff, FW_STATUS = 0x81000012
WARNING:cavs-fw:Load failed? FW_STATUS = 0x1006701
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Intel's adsp needs to set, at a minimum, a clocking bit before the driver
can initialize the designware dma controller. In many ways it is the
designware dmac IP but with additional registers and functionality added
on top of it. So the code structure here follows how the hardware
appears to be designed, layered on top of the designware driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This patch adds GPIO and 96board LS (Low Speed)iexpansion connector
support for SiFive HiFive Unleashed and also enables GPIO basic test.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
The XEN_INITIAL_DOMAIN option was defined at board level, however, some
drivers such as the XEN serial driver has dependencies on
XEN_INITIAL_DOMAIN, meaning any new board has to define its own copy of
XEN_INITIAL_DOMAIN. Move the option to SoC Kconfig.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The help for MCHP_ECIA_XEC is defined in
drivers/interrupt_controller/Kconfig.xec. defconfig files must not
re-define prompts or help, just modify the default value.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The SoC Kconfig.defconfig.series files re-defined multiple Kconfig help
entries. The help for such symbols should only be present in places
where symbol is actually defined, not where the defaults are changed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The xtensa/sample_controller linker script is missing the necessary
include statements for linker snippets. So add them.
Fixes#42477
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
replacing usage of the ESPTOOLPY_FLASHSIZE config
by the equivalent dt property path
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
replacing usage of the ESPTOOLPY_FLASHSIZE config
by the equivalent dt property path
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Non-standard `jalr rd, rs` pseudo-instructions are used.
This commit changes them to `ret` for standard return pseudo-instruction
or `jalr rd, rs, 0` for no offset jump register and link.
Fixes#41100.
Signed-off-by: Henry Hsieh <r901042004@yahoo.com.tw>
The ADC driver now supports three different implementations. To maintain
readability, this patch implements an adc_fixup.h that permits more
generic access to relevant registers.
This patch also introduces support for a new third shape ADC - as found
in the SAML21 for example.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Modified Xtensa soc intel_adsp to use nul when building on Windows host
and /dev/null when on Linux.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Divisor must be set to calculate SD host controller clock frequency in
clock driver.
Fixes#42380
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added basic support for the RP2040 SoC. Support
includes booting and starting the kernel, on one
core only.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add handling of secure-only code with TF-M enabled that can only be done
from secure processing environment.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
