So far board name was used as IDF target. This worked, as the only board
in tree that is based on 'esp32' SoC is actually 'esp32'.
Use CONFIG_SOC instead of CONFIG_BOARD, so that new boards based on
'esp32' SoC can be successfully introduced both downstream or upstream.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Many ARM SoCs included <devicetree.h> likely due to:
1. nvic.h not being self-contained
2. As a result of copy-paste
Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:
sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h
soc.h files that make a legitimate usage of the API have not been
changed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The header was not self-contained: it uses DT and utility macros but
<devicetree.h> and <sys/util_macro.h> were not included.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The source file uses boolean types internally, however, <stdbool.h> was
not included. It was likely included indirectly before via
<devicetree.h> -> <sys/util.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Almost none of the soc_*.h headers were self-contained. This patch adds
all necessary includes to improve the situation.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The default I2C channel 3 is used by alternate function of GPIO H1/H2
Krabby uses GPIO F2/F3 as I2C channel 3, so we need to add the
compatibility of the GPIO F2/F3.
TEST=test on it8xxx2_evb:
zmake configure -b zephyr/projects/it8xxx2_evb/
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Enable CONFIG_RISCV_PMP in qemu virt soc. Use this SoC as CI testing
platform of RISC-V PMP and Userspace.
Signed-off-by: Jim Shu <cwshu@andestech.com>
NPCX7/9 has a different ADC register structure. NPCX7 has 3 threshold
detectors from offset 0x14 & has 10 input channels. NPCX9 has 6
threshold detectors from offset 0x60 & has 12 input channels.
This commit fixes the NPCX ADC register structure.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
This got broken during the cpu_init unification pass. I appear to
have copied that zero out of code that initialized Zephyr on a
uniprocessor config somewhere. But what it means is that any use of
the S32C1I instruction to store to any memory type will trap an
exception! And even when CONFIG_MP_NUM_CPUS==1, we will emit code to
do that in the atomics layer when SMP=y.
That configuration ("SMP" with 1 cpu) is actually exercised by some
tests, including important ones like timer_api. These got broken.
Fix.
Really it's never correct to have anything but 1:1:1 ("external RCW
transaction") on these CPUs. All Intel cAVS processors have hardware
atomics support. We owe it to all the code we'll run to make sure it
works as documented and doesn't explode.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When running under a simulator, it's difficult to extract output from
the window (it's difficult with hardware too!). Add "SIMCALL" output
to stderr (it's literally just 3 extra instructions) as an optional
feature so this subsystem itself can be debugged without herculean
effort.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Reword the symbols to make it clear what they mean ("INIT_LPSRAM"
instead of "RESET_MHE_AT_BOOT") and use them correctly instead of
SOC_SERIES_* kconfigs.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
We don't define a MemoryException handler, nor is one appropriate for
this hardware as it stands. And the empty section keeps causing
linker warnings we have to work around. Remove.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Single-core instantiations of this hardware and single-core builds of
firmware still exist, so we should support that without needless
bloat.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The MP startup code had a hardcoded INTLEVEL field of 5 in the initial
value of PS. That's needless, INTLEVEL is a full 4 bit field even if
the number of hardware interrupt levels is lower (and in fact 0xf is
the documented hardware reset state). Set that instead, so that this
code will work with any XEA2 hardware. This also matches the similar
code path in boot startup.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Most of soc.c is actually interrupt handling glue for the intc_cavs
driver. Give it its own file so that SOC initialization and bringup
can live separately.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
XCHAL_HAVE_ICACHE_DYN_ENABLE is not set for any Intel cAVS
hardware, so MEMCTL configuration is not done properly leaving
icache disabled. This can be seen as ~10X slowness when running
code on non-primary cores. Fix the issue by using XCHAL_USE_MEMCTL
to check for MEMCTL usage.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Set TF-M option for nordic HAL library path to use the included
nordic HAL instead of the version that TF-M downloads.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
If there are no console messages input at an interval of 15
seconds, the system will be able to enter suspend mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Copy/paste/diverge struck again; I should have known better.
Fixes very recent and incomplete commit 9a1c5ec78e ("soc/intel_adsp:
cavs-link.ld: add *(.trace_ctx) sections"), see that commit for details.
Part of the fix for thesofproject/sof/issues/5032
This commit does not change `soc/xtensa/sample_controller/linker.ld`
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Having DWT-based NULL-pointer detection enabled by default trips a lot
of users since it will make any debugging fail when enabled. Disable it
by default and let users enable it if they desire to.
Fixes#39216.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Change the settings to support pinctrl on the GD32VF103.
- Split soc/arm/gigadevice/common/pinctrl_soc.h
and put it into include/dt-bindings.
- Leave some definitions that can't handle with device tree compiler
in pinctrl_soc.h.
- Remove dependency to SOC_FAMILY_GD32 because always enabled it
if GD32_HAS_AF(IO)_PINMAX was selected.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
GD32V processor core is used non-standard bitmask
for mcause register. Add option to configure the bitmask
to support GD32V.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
In this commit, the driver sets the PM constraint to prevent the system
from entering the suspend state for a CONFIG_UART_CONSOLE_INPUT_EXPIRED
period when data come in. The constraint releases after the
CONFIG_UART_CONSOLE_INPUT_EXPIRED time expires, .
With this change, the PM policy doesn't have to check the timestamp
by calling npcx_power_console_is_in_use() explictly. So the related
npcx_power_console_is_in_use*() functions can be removed.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Select configuration when mcuboot is enabled.
At this moment, only UNSIGNED image is supported as per
Espressif's mcuboot porting.
This also updates esp32 runner to use proper bin_file name
and updates default bootloader check.
Move CMakeLists.txt content from board to soc directory
as this support is for esp32 architecture and not board
specific.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Booting ESP32 without 2nd stage bootloader is not supported.
Hence, ifdefs in startup code are removed
Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
By enabling SMP option plus the APPCPU, also
completes the SMP port by adding the esp32
specific arch_sched_ipi() function
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
RT11xx can peripheral had incorrect clocking configuration in SOC clock
init code and DTS. Fix peripheral configuration.
Fixes#41251
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The CAVS linker scripts in Zephyr and "plain" (XTOS) SOF seem to share
the same origin and they mostly duplicate each other so they naturally
keep diverging from each other. This commit catches up with the SOF
commit ef43899c580f (thesofproject/sof/pull/2996) which added
the *(.trace_ctx) sections as part of the runtime log filtering
implementation (feature request thesofproject/sof/issues/2172)
Paraphrasing that commit, the goal is to create at link time a C-like
array by regrouping scattered trace contexts so they can be iterated on.
Together with some other changes in SOF, these 3 additional lines are
enough change in Zephyr to fix SOF bug thesofproject/sof/issues/5032
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
The fix for xcc build failures yesterday forgot to preserve the
squashing of stderr from the objcopy steps. As mentioned in the
comments, there are deliberate empty sections in this link that
binutils warns about, but which are actually required, Cadence has
some vector sections in their standard exception table that don't get
populated and rimage has non-code sections that may be left empty for
non-audio-driver applications like tests.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add board support for NXP i.MX8M Plus EVK. This board has the following
features:
Processor : i.MX8M Plus Quad applications processor
Memory : 32-bit LPDDR4 w/6 GB
eMMC 5.0/5.1 w/32 GB
SD/MMC connector
QSPI w/32 MB
Connectivity : MIMO 2x2 Wi-Fi 802.11b/g/n/ac and BT 4.2
2x Ethernet (1x w/ TSN)
PCIe M.2
2x CAN FD DB9 Female connectors
USB : USB 3.0 Type C for Power
USB 3.0 Type A
USB 3.0 Type C
Debug : JTAG connector
MicroUSB for debug console
More information about this board can be found in NXP website: https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
Recent linker changes got ahead of the toolchain and started using
features not available in the binutils 2.23-based Xtensa toolchain.
Specifically:
+ The section arguments to objcopy don't accept wildcards.
+ It's not legal to have an ALLOC section emitted to a region outside
a declared MEMORY space. So various non-mapped sections populated
by C structs have to be put somewhere with an explicit address.
+ The older linker won't automatically create an empty section just
because you assigned to ".", so the Zephyr tests that lack a
.fw_metadata section get rejected by rimage. The fix here is a
little clumsy: copy the section out of zephyr.elf into a
(potentially-zero-length) temporary file, then add it back to
main.mod as a final step.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The module copy was clearing BSS sections from the module list, but we
already clear the full memory space immediately after SRAM power-up so
that's needless, just like the legacy reset vector bss clear that got
removed earlier. (Yes: that means that this code used to be writing
zeros to .bss three times!)
Similarly, put a symmetric clear on the LP-SRAM bank for safety (it's
not currently used by Zephyr but we do start it up). And move the
cache flush to the end of initialization immediately before OS
handoff.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Both soc.h and adsp/cache.h were very small headers, there's no good
reason to have a separate header just for two one-line inlines.
Merge.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is some SOF code that got imported into Zephyr. But it's not a
Zephyr API and Zephyr doesn't use it. Unfortunately, the Zephyr
definition is now the one actually used at runtime in SOF, so we can't
remove it.
Put a guard around the definition so nothing else uses it until we get
it moved back home.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
