Commit graph

926 commits

Author SHA1 Message Date
Anas Nashif
27ff3f15f6 drivers: counter: remove qmsi counter driver
No users of this driver after dropping quark platforms.

COUNTER_0_NAME was only defined by the QMSI driver and was defined but
not used in DTS fixup files of ateml_sam0 SoCs. Removing those leftover
defines as well.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-09-18 11:06:18 -05:00
Francisco Munoz
20748fbb1b soc: microchip: mec1501: Add PS/2 support in Kconfig
Turn on PS/2 XEC Kconfig in terms of a generic Kconfig

Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-09-18 13:23:52 +08:00
Francisco Munoz
cb833ff18f soc: microchip: mec1501: Add dts fixup for PS/2 instances
Introduce DT fix up for autogenerated PS/2 definitions

Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-09-18 13:23:52 +08:00
Charles E. Youse
3038209695 drivers/timer/hpet.c: migrate to devicetree
This driver was still using CONFIG_* values to determine its address,
IRQ, etc. Add a binding for an "intel,hpet" device and migrate this
driver to devicetree.

Fixes: #18657

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-17 22:37:09 +08:00
Watson Zeng
fd17b86b94 arc: hsdk: add lvgl support for hsdk board
The ARC HSDK board provides an Arduino shield interface,
we can use it for TFT TOUCH SHIELD.

Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
2019-09-17 20:40:38 +08:00
Watson Zeng
9eb379f2bf arc: hsdk: add pinmux driver support and doc enhancement
* add pinmux driver. hsdk board has arduino, mikrobus and
  pmod interfaces, which can be confiured for different function,
  such as: gpio, spi, uart, iic.
* add introduction for arduino, mikrobus and pmod interfaces.

Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
2019-09-17 20:40:38 +08:00
Loic Poulain
9608a8e64e soc: nxp:rt: Add DATA_OCRAM config
Enable config for On-Chip RAM data.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-09-16 14:55:20 -05:00
Loic Poulain
f78f7076aa soc: nxp: rt: Add custom memory areas to linker script
RT SOCs have several memory areas (OCRAMs, DTCM, ITCM, SDRAM, FLASH...)
but only two are selected for FLASH (code) and RAM (data).
It would be good to let the linker be aware about other regions, which
could then be used by drivers or application to create dedicated
sections and relocate memory. For example if we have code in ITCM and
data in DTCM, we still need a dma-able region/section for e.g.
video/camera buffers.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-09-16 14:55:20 -05:00
Charles E. Youse
640c5a5e95 boards/x86: add Intel64 (64-bit long-mode) QEMU target board
Add qemu_x86_long board (with CONFIG_X86_LONGMODE=y) for testing.

This requires adding support to soc/ia32 for long mode (trivial),
and adding a quick 64- to 32-bit ELF conversion before invoking
QEMU, which apparently doesn't like 64-bit kernel files.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-15 11:33:47 +08:00
Charles E. Youse
3cf1bff71c arch/x86: complete 64-bit linker script
The previous linker script was barebones and non-standard. It is
replaced with a script conforms to the rest of the Zephyr arches,
utilizing include/linker headers and standard macros.

link-tool-gcc.h is updated to account for the "i386:x86-64" arch and
the generation of 64-bit ELF binaries.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-15 11:33:47 +08:00
Charles E. Youse
34307a54f0 arch/x86: initial Intel64 bootstrap framework
This patch adds basic build infrastructure, definitions, a linker
script, etc. to use the Zephyr and 0.10.1 SDK to build a 64-bit
ELF binary suitable for use with GRUB to minimally bootstrap an
Apollo Lake (e.g., UpSquared) board. The resulting binary can hardly
be called a Zephyr kernel as it is lacking most of the glue logic,
but it is a starting point to flesh those out in the x86 tree.

The "kernel" builds with a few harmless warnings, both with GCC from
the Zephyr SDK and with ICC (which is currently being worked on in
a separate branch). These warnings are either related to pointer size
differences (since this is an LP64 build) and/or dummy functions
that will be replaced with working versions shortly.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-15 11:33:47 +08:00
Charles E. Youse
239ceb4c5b soc/x86/apollo_lake: architecture is goldmont
Update the -march flag passed to the compiler to reflect the
underlying microarchitecture is 'goldmont'.

Fixes: #17104

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-15 11:33:47 +08:00
Kumar Gala
29e55d74e8 rtc: Remove old rtc functionality
Remove the old rtc functionality as its been deprecated for 2 releases
now.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-09-14 07:33:38 -05:00
Tomasz Bursztyka
403e6f1b99 soc/arm: Add a fixup for counter/alarm sample to compile with MEC1501
There are 2 other timers that could be selected, let's just take the
first 32bits one. This should be sufficient to verify the driver.

Enabling the timer in relevant board's dts file as well.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2019-09-14 12:13:49 +08:00
Tomasz Bursztyka
c6fe94a6f1 soc/arm: Enable XEC counter driver relevantly for MEC1501
Enabling XEC counter driver when CONFIG_COUNTER is set.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2019-09-14 12:13:49 +08:00
Tomasz Bursztyka
41c93a589c driver/counter: Add support for Microchip's XEC basic timer devices
Such basic timer is found on MEC150x for instance.
Since instances have dedicated data, let's define specifice instance
based on unique DT base address definition.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-09-14 12:13:49 +08:00
Maureen Helm
f646f8d0cf soc: nxp_kinetis: Refactor flash configuration field to a common place
Refactors the kinetis flash configuration field so it can be shared
across all kinetis SoCs. Defaults are overridden for the k8x and ke1xf
series to preserve values used prior to this refactoring.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-09-13 13:58:46 -05:00
Maureen Helm
2bc700f66e soc: nxp_kinetis: Make kinetis flash configuration field configurable
Kinetis SoCs have a 16-byte flash configuration field that must be
loaded at a specific address in flash. This field is not needed if we
are building an image to be chainloaded by MCUboot or a RAM-only image,
so we can exlude it in these cases and recover some wasted flash.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-09-13 13:58:46 -05:00
Kumar Gala
2632647ea0 kconfig: nxp_imx: rt: Convert to use new kconfigfunctions
Convert use of dt_int_val/dt_hex_val to dt_node_reg_{addr,size}.  As
we want to remove dt_int_val/dt_hex_val.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-09-13 11:42:34 -05:00
Kumar Gala
8ce0cf0126 kconfig: Convert device tree chosen properties to new kconfigfunctions
Convert how we get the various chosen properties like "zephyr,console"
to use the new kconfig functions like dt_chosen_to_label.

Because of how kconfig parses things we define a set of variables of the
form DT_CHOSEN_Z_<PROP> since comma's are parsed as field seperators in
macros.

This conversion allows us to remove code in gen_defines.py for the
following chosen properties:

zephyr,console
zephyr,shell-uart
zephyr,bt-uart
zephyr,uart-pipe
zephyr,bt-mon-uart
zephyr,uart-mcumgr
zephyr,bt-c2h-uart

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-09-13 11:42:34 -05:00
Scott Worley
6be78f36df soc : arm : microchip_mec Move custom busy wait config to MEC1501 SoC
Configuration item custom busy wait is required for all MEC1501
series if its RTOS timer driver is enabled. We moved the selection
of the timer from board level to MEC1501 SoC level.
Frequency selection remains at the board level.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2019-09-13 09:55:59 +02:00
Maureen Helm
b948fe6037 soc: nxp_lpc: Enable mpu on the lpc54114 m4 core
Enables the arm v7m mpu on the lpc54114 m4 core. Reuses the mpu
configuration from the i.mx rt, which has the same mpu.

Tested on hardware with tests/kernel/mem_protect

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-09-13 09:16:26 +02:00
Piotr Mienkowski
c249782bbc soc: add DTS PIO module nodes for sam3x series
This commit adds DTS PIO nodes for sam3x series SoCs.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-09-12 13:25:30 -05:00
Robert Weber
17f545be7d soc: stm32wb: Add support for STM32 IWDG
The driver for STM32's independent watchdog already exists and is
compatible with the stm32wb SoC. Enable the independent watchdog
for the stm32wb series for use with this driver.

Signed-off-by: Robert Weber <robertweber95@gmail.com>
2019-09-12 13:21:06 -05:00
Andrew Boie
6fd6b7e50a xtensa: remove legacy arch implementation
We re-wrote the xtensa arch code, but never got around
to purging the old implementation.

Removed those boards which hadn't been moved to the new
arch code. These were all xt-sim simulator targets and not
real hardware.

Fixes: #18138

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-12 01:26:34 -04:00
Ioannis Konstantelias
414e4d30a0 drivers: watchdog: stm32: Add implementation for WWDG
Added drivers for System Window Watchdog of STM32 platform.

Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
2019-09-11 22:13:36 -05:00
Ioannis Konstantelias
f9152adc81 soc: stm32: Add fixups for WWDG EWI and clock info
Extended the WWDG fixups to support early wake interrupt handling and
clock information.

Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
2019-09-11 22:13:36 -05:00
Andrew Boie
9df9994572 x86: fix XIP SOC support and defaults
XIP support in x86 was something of a mess. This
patch does the following:

- Generic ia32 SOC no longer defines a "flash" region
  as generic X86 devices don't have a microcontroller-
  like concept of flash. The same has been done for apollo_lake.
- Generic ia32 and apollo_lake SOCs starts memory at 1MB.
- Generic ia32 SOC may optionally have CONFIG_XIP enabled.
  The board definition must provide a flash region definition
  that gets exposed as DT_PHYS_LOAD_ADDR.
- Fixed definitions for RAM/ROM source addresses in ia32's
  linker.ld when XIP is turned off.
- Support for enabling XIP on apollo_lake SOC removed, there's
  no use-case.
- acrn and gpmrb boards have flash and XIP related definitions
  removed.
- qemu_x86 has a fake flash region added, immediately after system
  RAM, for use when XIP is enabled. This used to be in the ia32 SOC.
  However, the default for qemu_x86 is to now have XIP disabled.
- Fixed tests/kernel/xip to run by default on boards that enable
  XIP by default, plus an additional test to exercise XIP on
  qemu_x86 (which supports it but has XIP switched off by default)

The overall effect of this patch is to:

- Remove XIP configuration for SOC/boards where it does not make
  any sense to have it
- Support testing XIP on qemu_x86 via tests/kernel/xip, but leave
  it off by default for other tests, to ensure it doesn't bit-rot
  and that the system works in both scenarios.
- XIP remains an available feature for boards that need it.

Fixes: #18956

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-11 21:11:38 -04:00
Kumar Gala
57b10d0922 dts: nxp: ke1xf: Introduce nxp,kinetis-ke1xf-sim
The KE1xF SoC family SIM unit differs from the other Kinetis family
SoCs.  Add a unique compatiable and binding for it.

Fixes #18160

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-09-11 11:18:35 -05:00
Filip Brozovic
38125b8b49 soc: arm: k8x: add NXP Kinetis K8x SoC series support
Add initial support for the NXP Kinetis K8x SoC series (MK80F25615
and MK82F25615).

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2019-09-11 09:23:28 -05:00
Joris Offouga
ccd6bf1d07 soc/mcimx7_m4: Add i.MX7 Dual Kconfig SoC partnumber define
Adds the proper Kconfig entries for the i.MX7D partnumber presented
on Pico-pi board.

Signed-off-by: Joris Offouga <offougajoris@gmail.com>
2019-09-11 08:47:53 -05:00
Andy Liu
b888f8f892 dts: arm: nxp_rt: Fix typo in DT_PWM_MCUX_3_INDEX definition
DT_NXP_IMX_4PWM_03DC000_PWM3_INDEX should be
DT_NXP_IMX_PWM_403DC000_PWM3_INDEX.

Signed-off-by: Andy Liu <andy@madmachine.io>
2019-09-10 14:35:43 -05:00
Neill Kapron
6225592e27 SOC: Boards: NXP: Enable ethernet for mimxrt1060_evk
This enables ethernet functionality on the mimxrt1062 SOC
and mimxrt1060_evk board.

Signed-off-by: Neill Kapron <nkapron@gmail.com>
2019-09-10 07:44:08 -05:00
Kumar Gala
95f78bcacf interrupt: Convert RISC-V plic to use multi-level irq support
Utilize the multi-level irq infrastructure and replace custom handling
for PLIC on riscv-privilege SoCs.  The old code offset IRQs in drivers
and various places with RISCV_MAX_GENERIC_IRQ.  Instead utilize Zephyr's
encoded IRQ and replace offsets in drivers with the IRQ define from DTS.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-09-10 07:34:57 -05:00
Kumar Gala
d6e6a2be38 irq: intel_s1000: Fixup IRQ values for multi-level IRQ handling
Remove the handcoded multi-level IRQ values in device tree.  We now are
able to generate the encoded multi-level IRQ value.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-09-10 07:34:57 -05:00
Andrzej Głąbek
916bf0e682 modules: hal: nordic: Update the module revision
Update the module revision so that the following commits become
effective:

* nrfx_config: Use common mappings of Kconfig options to nrfx macros
* nrfx_config: Unify the way of enabling instances in nrfx drivers
* nrfx_config: Add missing mappings of Kconfig option symbols
* CMakeLists: Add missing inclusions of driver implementation files

The above changes require a minor correction in the nrf91/soc.h file,
so it is also modified in this commit.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2019-09-10 13:23:44 +02:00
Vincent Wan
e059eb3336 soc: ti_simplelink: add CC3235SF to the CC32xx series
This commit adds the TI CC3235SF SoC to the CC32xx series.

Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
2019-09-10 10:22:30 +03:00
Markus Fuchs
750a30296f soc: stm32: add SWO logger backend support
This patch adds HAS_SWO selections to all STM32 SoCs supporting Serial
Wire Output via the Trace Port Interface Unit (TPIU).

Signed-off-by: Markus Fuchs <markus.fuchs@de.sauter-bc.com>
2019-09-08 12:43:09 +02:00
Daniel Leung
04ae38085c intel_s1000: implement z_soc_irq_is_enabled()
This provides an implemention for z_soc_irq_is_enabled()
as it is needed for multi-level interrupts.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-09-07 10:20:51 -04:00
Charles E. Youse
6767563f94 arch/x86: remove support for IAMCU ABI
This ABI is no longer required by any targets and is deprecated.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-07 10:07:42 -04:00
Tomasz Bursztyka
0d37373196 soc/arm: Add the watchdog DTS fixup for mec1501
This is required to get the watchdog test and sample working since the
required wdt device name macro is generic there.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2019-09-07 09:56:58 -04:00
Charles E. Youse
c02288b245 docs: fix errors/ambiguities in docs for Apollo Lake boards
The documentation for the GPMRB incorrectly made reference to the
up_squared board in its high-speed UART configuration section. We
consolidate the related documentation for all boards based on the
Apollo Lake SoC and adjust the language to be more generic.

Fixes: #18808

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-04 10:02:25 +02:00
Vincent Wan
ae2742dc6b soc: arm: ti_simplelink: Fix number of interrupt lines on CC3220SF
There are only 178 interrupt lines on CC3220SF. Hence we should not set
NUM_IRQS to a value exceeding that value. We are changing it to 178.

Fixes #18593

Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
2019-08-23 22:39:45 +02:00
Anas Nashif
12438e1047 ext: hal: Make NXP HALs a Zephyr module
Moved to an external repo, https://github.com/zephyrproject-rtos/hal_nxp

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-08-21 21:05:23 -04:00
Peter Bigot
4a470114fa arc: rearrange for standard use of extern "C"
Consistently place C++ use of extern "C" after all include directives,
within the negative branch of _ASMLANGUAGE if used.

Remove extern "C" support from files that don't declare objects or
functions.

In arch/arc/arch.h the extern "C" in the including context is left
active during an include to avoid more complex restructuring.

Background from issue #17997:

Declarations that use C linkage should be placed within extern "C"
so the language linkage is correct when the header is included by
a C++ compiler.

Similarly #include directives should be outside the extern "C" to
ensure the language-specific default linkage is applied to any
declarations provided by the included header.

See: https://en.cppreference.com/w/cpp/language/language_linkage
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2019-08-20 00:49:15 +02:00
Peter Bigot
ddf9b144ce soc/arm/nxp*: rearrange for standard use of extern "C"
Consistently place C++ use of extern "C" after all include directives,
within the negative branch of _ASMLANGUAGE if used.

Remove extern "C" support from files that don't declare objects or
functions.

Background from issue #17997:

Declarations that use C linkage should be placed within extern "C"
so the language linkage is correct when the header is included by
a C++ compiler.

Similarly #include directives should be outside the extern "C" to
ensure the language-specific default linkage is applied to any
declarations provided by the included header.

See: https://en.cppreference.com/w/cpp/language/language_linkage
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2019-08-20 00:49:15 +02:00
Peter Bigot
0ddcf49b85 soc/arm/silabs_exx32: clean up use of extern "C"
Remove extern "C" support from files that don't declare symbols subject
to language linkage effects.

Consistently place C++ use of extern "C" after all include directives,
within the negative branch of _ASMLANGUAGE if used.

Background from issue #17997:

Declarations that use C linkage should be placed within extern "C"
so the language linkage is correct when the header is included by
a C++ compiler.

Similarly #include directives should be outside the extern "C" to
ensure the language-specific default linkage is applied to any
declarations provided by the included header.

See: https://en.cppreference.com/w/cpp/language/language_linkage
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2019-08-20 00:49:15 +02:00
Peter Bigot
bd87121180 soc/arm/ti_lm3s6965: remove unnecessary extern C block
This header doesn't define any symbols with linkage.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2019-08-20 00:49:15 +02:00
Peter Bigot
8101ca8f2c soc/arm/arm: rearrange for standard use of extern "C"
Move the tail include file outside the extern "C" block.

Background from issue #17997:

Declarations that use C linkage should be placed within extern "C"
so the language linkage is correct when the header is included by
a C++ compiler.

Similarly #include directives should be outside the extern "C" to
ensure the language-specific default linkage is applied to any
declarations provided by the included header.

See: https://en.cppreference.com/w/cpp/language/language_linkage
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2019-08-20 00:49:15 +02:00
Peter Bigot
b3862e93ae soc/arm/xilinx_zynqmp: clean up use of extern "C"
Remove extern "C" support from files that don't declare symbols subject
to language linkage effects.

Background from issue #17997:

Declarations that use C linkage should be placed within extern "C"
so the language linkage is correct when the header is included by
a C++ compiler.

Similarly #include directives should be outside the extern "C" to
ensure the language-specific default linkage is applied to any
declarations provided by the included header.

See: https://en.cppreference.com/w/cpp/language/language_linkage
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2019-08-20 00:49:15 +02:00