drivers/timer/hpet.c: migrate to devicetree
This driver was still using CONFIG_* values to determine its address, IRQ, etc. Add a binding for an "intel,hpet" device and migrate this driver to devicetree. Fixes: #18657 Signed-off-by: Charles E. Youse <charles.youse@intel.com>
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a78e5a267f
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3038209695
17 changed files with 65 additions and 41 deletions
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@ -39,3 +39,6 @@
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current-speed = <115200>;
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};
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&hpet {
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status = "okay";
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};
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@ -5,7 +5,6 @@ CONFIG_SOC_ATOM=y
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CONFIG_BOARD_MINNOWBOARD=y
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CONFIG_CPU_ATOM=y
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CONFIG_HPET_TIMER=y
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CONFIG_HPET_TIMER_IRQ=2
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CONFIG_PIC_DISABLE=y
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CONFIG_LOAPIC=y
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CONFIG_CONSOLE=y
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@ -73,6 +73,10 @@
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current-speed = <115200>;
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};
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&hpet {
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status = "okay";
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};
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&flash_sim0 {
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/*
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* For more information, see:
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@ -5,7 +5,6 @@ CONFIG_SOC_IA32=y
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CONFIG_BOARD_QEMU_X86=y
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CONFIG_CPU_MINUTEIA=y
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CONFIG_HPET_TIMER=y
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CONFIG_HPET_TIMER_IRQ=2
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CONFIG_PIC_DISABLE=y
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CONFIG_LOAPIC=y
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CONFIG_CONSOLE=y
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@ -5,7 +5,6 @@ CONFIG_SOC_IA32=y
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CONFIG_BOARD_QEMU_X86=y
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CONFIG_CPU_MINUTEIA=y
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CONFIG_HPET_TIMER=y
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CONFIG_HPET_TIMER_IRQ=2
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CONFIG_PIC_DISABLE=y
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CONFIG_LOAPIC=y
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CONFIG_CONSOLE=y
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@ -5,7 +5,6 @@ CONFIG_SOC_IA32=y
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CONFIG_BOARD_QEMU_X86=y
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CONFIG_CPU_MINUTEIA=y
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CONFIG_HPET_TIMER=y
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CONFIG_HPET_TIMER_IRQ=2
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CONFIG_PIC_DISABLE=y
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CONFIG_LOAPIC=y
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CONFIG_CONSOLE=y
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@ -31,13 +31,6 @@ endif # I2C
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config APIC_TIMER
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default y if !HPET_TIMER
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if HPET_TIMER
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config HPET_TIMER_IRQ
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default 2
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endif # HPET_TIMER
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if APIC_TIMER
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config APIC_TIMER_IRQ
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@ -69,27 +69,6 @@ menuconfig HPET_TIMER
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This option selects High Precision Event Timer (HPET) as a
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system timer.
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if HPET_TIMER
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config HPET_TIMER_BASE_ADDRESS
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hex "HPET Base Address"
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default 0xFED00000
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help
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This options specifies the base address of the HPET timer device.
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config HPET_TIMER_IRQ
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int "HPET Timer IRQ"
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default 2
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help
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This option specifies the IRQ used by the HPET timer.
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config HPET_TIMER_IRQ_PRIORITY
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int "HPET Timer IRQ Priority"
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default 4
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help
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This option specifies the IRQ priority used by the HPET timer.
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endif #HPET_TIMER
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menuconfig LOAPIC_TIMER
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bool "LOAPIC timer"
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depends on LOAPIC && X86
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@ -8,7 +8,7 @@
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#include <spinlock.h>
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#define HPET_REG32(off) (*(volatile u32_t *)(long) \
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(CONFIG_HPET_TIMER_BASE_ADDRESS + (off)))
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(DT_INST_0_INTEL_HPET_BASE_ADDRESS + (off)))
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#define CLK_PERIOD_REG HPET_REG32(0x04) /* High dword of caps reg */
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#define GENERAL_CONF_REG HPET_REG32(0x10)
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@ -69,10 +69,11 @@ int z_clock_driver_init(struct device *device)
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extern int z_clock_hw_cycles_per_sec;
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u32_t hz;
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IRQ_CONNECT(CONFIG_HPET_TIMER_IRQ, CONFIG_HPET_TIMER_IRQ_PRIORITY,
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IRQ_CONNECT(DT_INST_0_INTEL_HPET_IRQ_0,
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DT_INST_0_INTEL_HPET_IRQ_0_PRIORITY,
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hpet_isr, 0, 0);
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set_timer0_irq(CONFIG_HPET_TIMER_IRQ);
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irq_enable(CONFIG_HPET_TIMER_IRQ);
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set_timer0_irq(DT_INST_0_INTEL_HPET_IRQ_0);
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irq_enable(DT_INST_0_INTEL_HPET_IRQ_0);
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/* CLK_PERIOD_REG is in femtoseconds (1e-15 sec) */
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hz = (u32_t)(1000000000000000ull / CLK_PERIOD_REG);
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18
dts/bindings/timer/intel,hpet.yaml
Normal file
18
dts/bindings/timer/intel,hpet.yaml
Normal file
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@ -0,0 +1,18 @@
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# Copyright (c) 2019 Intel Corp.
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# SPDX-License-Identifier: Apache-2.0
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title: HPET
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description: >
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This binding represents the High-Precision Event Timer
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compatible: "intel,hpet"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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@ -227,5 +227,15 @@
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status = "okay";
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};
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hpet: hpet@fed00000 {
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label = "HPET";
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compatible = "intel,hpet";
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reg = <0xfed00000 0x400>;
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interrupts = <2 IRQ_TYPE_EDGE_RISING 4>;
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interrupt-parent = <&intc>;
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status = "okay";
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};
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};
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};
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@ -65,5 +65,15 @@
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status = "disabled";
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};
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hpet: hpet@fed00000 {
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label = "HPET";
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compatible = "intel,hpet";
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reg = <0xfed00000 0x400>;
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interrupts = <2 IRQ_TYPE_EDGE_RISING 4>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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};
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};
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@ -39,7 +39,6 @@
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compatible = "simple-bus";
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ranges;
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uart0: uart@3f8 {
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compatible = "ns16550";
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reg = <0x000003f8 0x100>;
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@ -61,5 +60,15 @@
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status = "disabled";
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};
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hpet: hpet@fed00000 {
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label = "HPET";
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compatible = "intel,hpet";
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reg = <0xfed00000 0x400>;
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interrupts = <2 IRQ_TYPE_EDGE_RISING 4>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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};
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};
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@ -27,7 +27,7 @@ MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4 * 1024, MMU_ENTRY_WRITE);
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MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, 1024 * 1024, MMU_ENTRY_WRITE);
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#ifdef CONFIG_HPET_TIMER
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MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
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MMU_BOOT_REGION(DT_INST_0_INTEL_HPET_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
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#endif /* CONFIG_HPET_TIMER */
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/* for UARTs */
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@ -38,7 +38,7 @@ MMU_BOOT_REGION(0xB0700000, 4*1024, MMU_ENTRY_WRITE);
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MMU_BOOT_REGION(0xB0500000, 256*1024, MMU_ENTRY_WRITE);
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#ifdef CONFIG_HPET_TIMER
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MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
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MMU_BOOT_REGION(DT_INST_0_INTEL_HPET_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
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#endif /* CONFIG_HPET_TIMER */
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#endif /* CONFIG_X86_MMU */
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@ -23,8 +23,9 @@
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#ifdef CONFIG_X86_MMU
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MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
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MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, MB(1), MMU_ENTRY_WRITE);
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#ifdef CONFIG_HPET_TIMER
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MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
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MMU_BOOT_REGION(DT_INST_0_INTEL_HPET_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
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#endif
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#ifdef CONFIG_ETH_E1000
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@ -48,7 +48,7 @@
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* is not defined in platform, generate an error
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*/
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#if defined(CONFIG_HPET_TIMER)
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#define TICK_IRQ CONFIG_HPET_TIMER_IRQ
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#define TICK_IRQ DT_INST_0_INTEL_HPET_IRQ_0
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#elif defined(CONFIG_APIC_TIMER)
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#define TICK_IRQ CONFIG_APIC_TIMER_IRQ
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#elif defined(CONFIG_LOAPIC_TIMER)
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