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drivers/timer/hpet.c: migrate to devicetree

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This driver was still using CONFIG_* values to determine its address,
IRQ, etc. Add a binding for an "intel,hpet" device and migrate this
driver to devicetree.

Fixes: #18657

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This commit is contained in:
Charles E. Youse 2019-09-11 16:45:43 -04:00 • committed by Anas Nashif
commit 3038209695
17 changed files with 65 additions and 41 deletions
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3
boards/x86/minnowboard/minnowboard.dts
View file

@ -39,3 +39,6 @@
current-speed = <115200>;
};
&hpet {
status = "okay";
};

1
boards/x86/minnowboard/minnowboard_defconfig
View file

@ -5,7 +5,6 @@ CONFIG_SOC_ATOM=y
CONFIG_BOARD_MINNOWBOARD=y
CONFIG_CPU_ATOM=y
CONFIG_HPET_TIMER=y
CONFIG_HPET_TIMER_IRQ=2
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y

4
boards/x86/qemu_x86/qemu_x86.dts
View file

@ -73,6 +73,10 @@
current-speed = <115200>;
};
&hpet {
status = "okay";
};
&flash_sim0 {
/*
* For more information, see:

1
boards/x86/qemu_x86/qemu_x86_coverage_defconfig
View file

@ -5,7 +5,6 @@ CONFIG_SOC_IA32=y
CONFIG_BOARD_QEMU_X86=y
CONFIG_CPU_MINUTEIA=y
CONFIG_HPET_TIMER=y
CONFIG_HPET_TIMER_IRQ=2
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y

1
boards/x86/qemu_x86/qemu_x86_defconfig
View file

@ -5,7 +5,6 @@ CONFIG_SOC_IA32=y
CONFIG_BOARD_QEMU_X86=y
CONFIG_CPU_MINUTEIA=y
CONFIG_HPET_TIMER=y
CONFIG_HPET_TIMER_IRQ=2
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y

1
boards/x86/qemu_x86/qemu_x86_nommu_defconfig
View file

@ -5,7 +5,6 @@ CONFIG_SOC_IA32=y
CONFIG_BOARD_QEMU_X86=y
CONFIG_CPU_MINUTEIA=y
CONFIG_HPET_TIMER=y
CONFIG_HPET_TIMER_IRQ=2
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y

7
boards/x86/up_squared/Kconfig.defconfig
View file

@ -31,13 +31,6 @@ endif # I2C
config APIC_TIMER
default y if !HPET_TIMER
if HPET_TIMER
config HPET_TIMER_IRQ
default 2
endif # HPET_TIMER
if APIC_TIMER
config APIC_TIMER_IRQ

21
drivers/timer/Kconfig
View file

@ -69,27 +69,6 @@ menuconfig HPET_TIMER
This option selects High Precision Event Timer (HPET) as a
system timer.
if HPET_TIMER
config HPET_TIMER_BASE_ADDRESS
hex "HPET Base Address"
default 0xFED00000
help
This options specifies the base address of the HPET timer device.
config HPET_TIMER_IRQ
int "HPET Timer IRQ"
default 2
help
This option specifies the IRQ used by the HPET timer.
config HPET_TIMER_IRQ_PRIORITY
int "HPET Timer IRQ Priority"
default 4
help
This option specifies the IRQ priority used by the HPET timer.
endif #HPET_TIMER
menuconfig LOAPIC_TIMER
bool "LOAPIC timer"
depends on LOAPIC && X86

9
drivers/timer/hpet.c
View file

@ -8,7 +8,7 @@
#include <spinlock.h>
#define HPET_REG32(off) (*(volatile u32_t *)(long) \
(CONFIG_HPET_TIMER_BASE_ADDRESS + (off)))
(DT_INST_0_INTEL_HPET_BASE_ADDRESS + (off)))
#define CLK_PERIOD_REG HPET_REG32(0x04) /* High dword of caps reg */
#define GENERAL_CONF_REG HPET_REG32(0x10)
@ -69,10 +69,11 @@ int z_clock_driver_init(struct device *device)
extern int z_clock_hw_cycles_per_sec;
u32_t hz;
IRQ_CONNECT(CONFIG_HPET_TIMER_IRQ, CONFIG_HPET_TIMER_IRQ_PRIORITY,
IRQ_CONNECT(DT_INST_0_INTEL_HPET_IRQ_0,
DT_INST_0_INTEL_HPET_IRQ_0_PRIORITY,
hpet_isr, 0, 0);
set_timer0_irq(CONFIG_HPET_TIMER_IRQ);
irq_enable(CONFIG_HPET_TIMER_IRQ);
set_timer0_irq(DT_INST_0_INTEL_HPET_IRQ_0);
irq_enable(DT_INST_0_INTEL_HPET_IRQ_0);
/* CLK_PERIOD_REG is in femtoseconds (1e-15 sec) */
hz = (u32_t)(1000000000000000ull / CLK_PERIOD_REG);

18
dts/bindings/timer/intel,hpet.yaml Normal file
View file

@ -0,0 +1,18 @@
# Copyright (c) 2019 Intel Corp.
# SPDX-License-Identifier: Apache-2.0
title: HPET
description: >
This binding represents the High-Precision Event Timer
compatible: "intel,hpet"
include: base.yaml
properties:
reg:
required: true
interrupts:
required: true

10
dts/x86/apollo_lake.dtsi
View file

@ -227,5 +227,15 @@
status = "okay";
};
hpet: hpet@fed00000 {
label = "HPET";
compatible = "intel,hpet";
reg = <0xfed00000 0x400>;
interrupts = <2 IRQ_TYPE_EDGE_RISING 4>;
interrupt-parent = <&intc>;
status = "okay";
};
};
};

10
dts/x86/atom.dtsi
View file

@ -65,5 +65,15 @@
status = "disabled";
};
hpet: hpet@fed00000 {
label = "HPET";
compatible = "intel,hpet";
reg = <0xfed00000 0x400>;
interrupts = <2 IRQ_TYPE_EDGE_RISING 4>;
interrupt-parent = <&intc>;
status = "disabled";
};
};
};

11
dts/x86/ia32.dtsi
View file

@ -39,7 +39,6 @@
compatible = "simple-bus";
ranges;
uart0: uart@3f8 {
compatible = "ns16550";
reg = <0x000003f8 0x100>;
@ -61,5 +60,15 @@
status = "disabled";
};
hpet: hpet@fed00000 {
label = "HPET";
compatible = "intel,hpet";
reg = <0xfed00000 0x400>;
interrupts = <2 IRQ_TYPE_EDGE_RISING 4>;
interrupt-parent = <&intc>;
status = "disabled";
};
};
};

2
soc/x86/apollo_lake/soc.c
View file

@ -27,7 +27,7 @@ MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4 * 1024, MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, 1024 * 1024, MMU_ENTRY_WRITE);
#ifdef CONFIG_HPET_TIMER
MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_INST_0_INTEL_HPET_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
#endif /* CONFIG_HPET_TIMER */
/* for UARTs */

2
soc/x86/atom/soc.c
View file

@ -38,7 +38,7 @@ MMU_BOOT_REGION(0xB0700000, 4*1024, MMU_ENTRY_WRITE);
MMU_BOOT_REGION(0xB0500000, 256*1024, MMU_ENTRY_WRITE);
#ifdef CONFIG_HPET_TIMER
MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_INST_0_INTEL_HPET_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
#endif /* CONFIG_HPET_TIMER */
#endif /* CONFIG_X86_MMU */

3
soc/x86/ia32/soc.c
View file

@ -23,8 +23,9 @@
#ifdef CONFIG_X86_MMU
MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, MB(1), MMU_ENTRY_WRITE);
#ifdef CONFIG_HPET_TIMER
MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_INST_0_INTEL_HPET_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
#endif
#ifdef CONFIG_ETH_E1000

2
tests/kernel/context/src/main.c
View file

@ -48,7 +48,7 @@
* is not defined in platform, generate an error
*/
#if defined(CONFIG_HPET_TIMER)
#define TICK_IRQ CONFIG_HPET_TIMER_IRQ
#define TICK_IRQ DT_INST_0_INTEL_HPET_IRQ_0
#elif defined(CONFIG_APIC_TIMER)
#define TICK_IRQ CONFIG_APIC_TIMER_IRQ
#elif defined(CONFIG_LOAPIC_TIMER)